OSCh9

Chapter 9: Memory Management ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Background ,[object Object],[object Object],[object Object]

Binding of Instructions and Data to Memory ,[object Object],[object Object],[object Object],Address binding of instructions and data to memory addresses can happen at three different stages.

Multistep Processing of a User Program

Logical vs. Physical Address Space ,[object Object],[object Object],[object Object],[object Object]

Memory-Management Unit ( MMU ) ,[object Object],[object Object],[object Object]

Dynamic relocation using a relocation register

Dynamic Loading ,[object Object],[object Object],[object Object],[object Object]

Dynamic Linking ,[object Object],[object Object],[object Object],[object Object],[object Object]

Overlays ,[object Object],[object Object],[object Object]

Overlays for a Two-Pass Assembler

Swapping ,[object Object],[object Object],[object Object],[object Object],[object Object]

Contiguous Allocation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Hardware Support for Relocation and Limit Registers

Contiguous Allocation (Cont.) ,[object Object],[object Object],[object Object],[object Object],OS process 5 process 8 process 2 OS process 5 process 2 OS process 5 process 2 OS process 5 process 9 process 2 process 9 process 10

Dynamic Storage-Allocation Problem ,[object Object],[object Object],[object Object],How to satisfy a request of size n from a list of free holes. First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

Fragmentation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Paging ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Address Translation Scheme ,[object Object],[object Object],[object Object]

Address Translation Architecture

Free Frames Before allocation After allocation

Implementation of Page Table ,[object Object],[object Object],[object Object],[object Object],[object Object]

Associative Memory ,[object Object],[object Object],[object Object],[object Object],Page # Frame #

Effective Access Time ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Memory Protection ,[object Object],[object Object],[object Object],[object Object]

Valid (v) or Invalid (i) Bit In A Page Table

Page Table Structure ,[object Object],[object Object],[object Object]

Hierarchical Page Tables ,[object Object],[object Object]

Two-Level Paging Example ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],page number page offset p i p 2 d 10 10 12

Address-Translation Scheme ,[object Object]

Hashed Page Tables ,[object Object],[object Object],[object Object]

Inverted Page Table ,[object Object],[object Object],[object Object],[object Object]

Inverted Page Table Architecture

Shared Pages ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Segmentation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Logical View of Segmentation 1 3 2 4 user space physical memory space 1 4 2 3

Segmentation Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Segmentation Architecture (Cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Segmentation Architecture (Cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Segmentation with Paging – MULTICS ,[object Object],[object Object]

MULTICS Address Translation Scheme

Segmentation with Paging – Intel 386 ,[object Object]

Intel 30386 Address Translation

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