12 low power techniques

LOW POWER TECHNIQUES IN NANOMETER
TECHNOLOGY

Name : Rama Krishna P.
Reg No : CGB0911012
Course : M.Sc. [Engg.] in VLSI System Design
Module : Integrated Circuit Analysis and Design
Module Leader : Prof. Cyril Prasanna Raj P.

M.S.Ramaiah School of Advanced Studies, Bangalore 1

Discussion
Why low power?
Types of power consumption
• Dynamic power
• Static power
Low power techniques
• Clock gating
• Multi vdd
• Multiple vth
• Power gating
Trade off
Future scope
Conclusion
References


Why low power...?

 Desirability of portable devices.
 Advent of hand held battery operated devices.
 Large power dissipation requires larger heat sinks hence increased area.
 Cost of providing power has resulted in significant interest in power reduction
of non portable devices.
 Lowering transistor threshold voltage.

Pavg=Pswitching+Pshort-circuit + Pleakage
=α0 1CL Vdd2 fclk + Vdd Isc +Ileakage Vdd


Types of Power Consumption

Dynamic power
During the switching of transistors
Depends on the clock frequency and switching activity
Consists of switching power and internal power.

Static Power
Transistor leakage current that flows whenever power is applied to the device
Independent of the clock frequency or switching activity.


Dynamic power
( Pswitching =CL Vdd2 fclk )

capacitance

Vdd 1) Output node capacitance of the logic gate: due to the drain
diffusion region.
A 2) Total interconnects capacitance: has higher effect as
PMOS
technology node shrinks.
Vout
B Cdrain+ 3) Input node capacitance of the driven gate: due to the gate
NMOS CloadCinterconnect+
Cinput
oxide capacitance.
Input voltage
Internal node voltage swing can be only Vi which can be smaller than
Fig 1:cmos inverter
the full voltage swing of Vdd leading to the partial voltage swing.
Frequency
F increases then power automatically increases.


(Pshort-circuit =Vdd Isc )

More rise/fall timemore short circuit
Both PMOS and NMOS are
Lower threshold voltagemore short
conducting for a short duration of time circuit
Vdd- |Vthp|
short between supply power and
2.5V
PMOS
ground
curve

Vout Vthn<Vin<Vdd-|Vthp|

NMOS
curve

0V Vthn
Vin 2.5V
Fig 3:Trance analysis of cmos
Fig 2:shorte circuit

To get equal rise/fall  balance transistor sizing
Vdd<Vthn+|Vthp|


Static power
(Pleakage =Ileakage Vdd)

1). Diode reverse bias–I1 2). Sub threshold current – I2
Vgs <~ Vth carrier diffusion causes sub
threshold leakage.

Vgs <=0  accumulation mode.
0< Vgs << Vth depletion mode.
Vgs ~ Vth  weak inversion.
Vgs > Vth  Inversion.
Fig 4:Diode reverse bias
3). Gate induced drain leakage – I3 4).Gate oxide tunneling – I4
Higher supply voltage. high electric field across a thin

thinner oxide. gate oxide.
Direct tunneling through the
increase in Vdb and Vdg.
silicon oxide layer if it is less than
3–4 nm thick.
Fig 5:leakage currents


Low power design techniques

Table 1:low power design techniques

Clock gating

× Clock tree consume more than 50 % of dynamic power
 Used for synchronous circuits
 Clock gating works by taking the enable conditions attached to registers, and uses them to
gate the clocks.
 Save significant die area as well as power.
 Clock gating logic is generally in the form of "integrated clock gating" (ICG) cells.

Logic added into the design

 Coded into the RTL code as enable conditions--clock gating logic (fine grain clock gating).
Inserted into the design manually by the RTL designers (typically as module level clock gating)
Semi-automatically inserted into the RTL by (automated clock gating tools)


Two types of clock gating styles

Latch-based clock gating Latch-free clock

En D Q
D Q

CK Gated CK
clock
clk

Fig 6:Latch-based clock gating Fig 6:Latch-free clock gating

Uses a simple AND or OR gate Level-sensitive latch
Glitches are inevitable Less glitch
Less used Easy adoption by EDA tools


Multi Vdd (Voltage)

SVS DVFS AVS

Different but fixed Voltage as well as When high
voltage is applied to frequency is speed of  Voltage areas
different blocks or dynamically varied operation is with variable VDD.
subsystems of the SoC as per the different required Voltage is
design. working modes of voltage is controlled using a
the design increased control loop.


Multiple threshold

Use Hvt and Lvt cells Vdd

standby High Prevents leakage
Called as “sleep transistor” Vt in standby mode

Extensively used in CMOS Logic High speed
Power gating Low/Nom Vt operation

standby High Prevents leakage
Vt in standby mode

Fig 6:Sleep transistor


Variable threshold

Vdd Vdd
Vbias1
General
variable substrate
design:
bias voltage from a
substrate is
control circuitry to
tied to power
Vbias2 vary threshold
or ground
voltage

Fig 7:substrate bias voltage in cmos
Pros
Considerable power reduction
Negligible area overhead
Cons
Requires either twin well or triple well technology to achieve different substrate bias
voltage levels at different parts of the IC


Power gating

Circuit blocks that are not in use are temporarily turned off
Affects design architecture more compared to the clock gating
It increases time delays as power gated modes have to be safely entered and exited

CMOS
High Vt PMOS logic
Power switching Header switch
control signal Power switching
control signal High Vt NMOS
Footer switch
CMOS
logic

A power switch (header or footer) is
added to supply rails to
shut-down logic
(MTCMOS switches)
Fig 8:power gating by sleep transistor


Fine-grain power gating Coarse-grain power gating

Fig 9:Fine grain power gating Fig 10:Coarse grain power gating

 Add a sleep transistor to every cell
 Less sensitive to PVT variation
 Switching transistor as a part of the  Introduces less IR-drop variation
standard cell logic  Imposes a smaller area overhead

 ~10X leakage reduction
 Ring based methodology
 Column based methodology

Fig 11:switces for reducing the power

Low-power design requires new cells with multiple power pins
Additional modeling information in “.lib” is required to
automatically handle these cells


Trade –off for low power techniques

Table 2:trade-off analysis of power reducing techniques


Future low power strategy…?

Asynchronous Design - Solution to Dynamic Power?
›Let’s get rid of the clock
›Micro pipeline: A Simple Asynchronous Design Methodology
Is Hi-k sufficient for 22nm and 16nm?
Whether this type of transistor structure (hi-k, metal gate) will continue to scale to the
next two generations—22 nm and 16 nm—is a question for the future.
Is there a simple, coherent power strategy that unifies the best of DVFS, power gating,
asynchronous ?
How do we represent and verify very complex power intent such as asynchronous ?
Carbon nano tubes…….?
Spintronics…..?


conclusion

Power is becoming the restraining factor in further miniaturization and
scaling. Various methodologies available but still a lot of scope for improvement.
Need for developing of infrastructure. Combining of discrete power saving
techniques into a single integrated system.


References

[1] Keshava Murali, “Low power techniques”, SNUG 2007 and 2008
presentations on low power, Retrieved on 17 oct 2011.
[2] Jan.M.Rabey and Massoud Pedram Kluwer academic publishers, “low
power design methodologies”, Retrieved on 17 oct 2011.


Thank you…….


12 low power techniques

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12 low power techniques