Mahesh Dananjaya

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low power electronic design vlsi design low power techniques semiconductors soc mpsoc power gating clock gating asic eda sopc power reduction processor architecture nfv computer architecture sdn machine learning power estimation mini-batch processing complex event processor sgd optimizationn distributed systems deep learning data analytics data sciences high performance flow matching flow caching data plane parallel systems risc mips high performance computing routing placement floorplanning digital ic electronic physical design physical design digital integrated circuit normalized cut graph cut segmentation machine vision image processing fpga static power

Aktivität
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Mahesh Dananjaya

Präsentationen

VLSI Power in a Nutshell

Low Power VLSI Design

SOC Power Estimation

SoC Power Reduction

Clock Gating

Power Gating

Vlsi power estimation

VLSI Power Reduction

Low Power VLSI Designs

Low power electronic design

High Performance Flow Matching Architecture for Openflow Data Plane

Dokumente

Low power electronic design

Image segmentation using normalized graph cut

Digital Integrated Circuit (IC) Design

OpenFlow Aware Network Processor

Proposal for google summe of code 2016

Gefällt mir

P4: Programming Protocol-Independent Packet Processor

Adapting to a Cambrian AI/SW/HW explosion with open co-design competitions and Collective Knowledge

Verilator: Fast, Free, But for Me?

Open VSwitch on Android

Tutorial on SDN data plane evolution

LTE Testing | 4G Testing

Open Flow Tutorial Series - Set 1

Set review 1

Open stack with_openflowsdn-torii