2. 2
Outline
• Simple PLL
• VCO, PD
• PLL transfer function
• Phase Margin
• Type-I PLL
• Type-II PLL
• PFD
• Charge Pump
• CP PLL transfer function
• CP PLL stability
• Open loop bandwidth
• Design strategy
• Higher order PLL transfer function
• Higher order PLL design rule of thumb
3. 3
Local Oscillator
• Local oscillator (LO) is an electronic oscillator used with a mixer to change the
frequency of a signal.
• LO is used to up convert signal (BB or IF to RF) and down convert it (RF to IF or BB).
LO Problems
• Output signal frequency is affected by noise, temperature and process variations.
• Therefore we need a system to stabilize LO’s frequency.
• Typical LO has phase noise and with using PLL we can decrease the phase noise.
Why We Need PLL
4. 4
What is PLL
• A phase-locked loop or PLL is a control system that generates an output signal whose phase is
related to the phase of an input signal.
• Keeping the input and output phase in lock means keeping the input and output frequencies
the same. (If phase difference varies with time, the frequencies of two signals are not equal).
• Consequently, in addition to synchronizing signals, a PLL can track an input frequency, or it can
generate a frequency that is a multiple of the input frequency.
6. 6
Simple PLL
• In its simplest form, a PLL is a negative feedback loop consisting of a VCO and a
“phase detector” (PD).
• PD converts phase difference to voltage which changes the frequency and
phase of VCO and pushes it to follow the ideal reference.
7. 7
Simple PLL Problem
• If the control voltage (Vctrl) has ripple it modulates the VCO and produces side bands.
• Assuming only the first harmonic of Vctrl.
15. 15
Bode plots of type-I PLL showing the effect of higher KVCO
Phase Margin (2)
16. 16
Phase Margin (3)
KVCO PM
Summary:
• Increasing KVCO or KPD will cause stability problems.
• Decreasing ߱LPF for having less ripple will cause stability problems.
• Damping factor expression confirms these.
18. 18
Practical PLL
• We have an ideal reference crystal oscillator (low phase noise compared to VCO) which operates
at low frequency.
• Then with using a frequency divider we translate VCO output to lower frequencies.
߱ݐݑ = ܯ × ߱݅݊
CMOS VCTCXO
1 GHz
22. 22
• Solving problem of limited acquisition range.
• Phase detectors produce little information if they sense unequal frequencies at their inputs.
• Solution? the acquisition range can be widened if a frequency detector (FD) is added to the loop.
• Thus, it is desirable to seek a circuit that operates as an FD if its input frequencies are not equal
and as a PD if they are. Such a circuit is called a “phase/frequency detector” (PFD).
Type-II PLL
38. 38
Open Loop Bandwidth
Wu provides us with valuable information about PLL system:
• System stability.
• How is the system response for slow and fast phase variations ?
• How much phase noise could be suppressed by PLL ?
• Wu will be used for PLL system design.
42. 42
Some Example and Design Rule (1)
BW
Step1. fix ߞ reach desirable stability
Step2. ߱݊
So M , BW
M , loop gain
43. 43
Change BW still maintain stability (same PM) that we want !
Some Example and Design Rule (2)
44. 44
Close Loop Transfer Function (1)
Goal: find 3dB BW
Why do we need to calculate close loop transfer function ?
• We can find the poles and 3dB bandwidth of system.
• ߱3dB will be used for phase noise calculation.
• With tuning ߱3dB we can adjust the bandwidth (spur cancellation).
49. 49
High Order PLL
• Why do we need high order PLL ?
• Do to same non-ideal effects in PLL circuit analysis, Vcontrol will have some ripple
and this ripple causes side bands (spur) at the output of VCO.
• In order to suppress Vcontrol ripple and therefore suppress spurs we need to have
higher order filters.