Personal Information
Unternehmen/Arbeitsplatz
Bhopal Area, India India
Branche
Education
Webseite
rntu.ac.in%2520Rabindranath%2520Tagore%2520University%2520-%2520Bhopal,%2520Madhya%2520Pradesh
Info
July 2015 to till date: Assistant Professor at the Electronics and Communication Engineering Department,
Coordinator-Centre of excellence for Incubation and Entrepreneur and startups (CIES), Rabindranath Tagore University (RNTU), Bhopal.
June 2007 to July 2015: Assistant Professor in Electronics and Communication Engineering
Department, Bansal College of Engineering, Mandideep.
Aug. 2006 to Jun.2007: Lecturer, Electronics, and Communication Engineering Department, All Saint’s
College of Engineering, Bhopal.
Tags
ravitesh mishra
design of analog cmos integrated circuits
razavi
ec-605
ec-802
charged pump plls
datapath subsystem-multiplication
flip-flops
non ideal effects of pll
shivendra singh
cmos vlsi design
rom
Mehr anzeigen
Präsentationen
(12)Gefällt mir
(3)Electromagnetic Field Theory Lecture Notes
FellowBuddy.com
•
Vor 8 Jahren
Design and Implementation of an Advanced DMA Controller on AMBA-Based SoC
Rabindranath Tagore University, Bhopal
•
Vor 11 Jahren
Non ideal effects of pll
Rabindranath Tagore University, Bhopal
•
Vor 11 Jahren
Personal Information
Unternehmen/Arbeitsplatz
Bhopal Area, India India
Branche
Education
Webseite
rntu.ac.in%2520Rabindranath%2520Tagore%2520University%2520-%2520Bhopal,%2520Madhya%2520Pradesh
Info
July 2015 to till date: Assistant Professor at the Electronics and Communication Engineering Department,
Coordinator-Centre of excellence for Incubation and Entrepreneur and startups (CIES), Rabindranath Tagore University (RNTU), Bhopal.
June 2007 to July 2015: Assistant Professor in Electronics and Communication Engineering
Department, Bansal College of Engineering, Mandideep.
Aug. 2006 to Jun.2007: Lecturer, Electronics, and Communication Engineering Department, All Saint’s
College of Engineering, Bhopal.
Tags
ravitesh mishra
design of analog cmos integrated circuits
razavi
ec-605
ec-802
charged pump plls
datapath subsystem-multiplication
flip-flops
non ideal effects of pll
shivendra singh
cmos vlsi design
rom
Mehr anzeigen