Fpga implementation of high speed 8 bit vedic multiplier using barrel shifter(1)

FPGA IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER USING
BARREL SHIFTER
SPHOORTHY ENGINEERING COLLEGE Page 1
FPGA Implementation of high speed 8-bit Vedic
multiplier using barrel shifter
TABLE OF CONTENTS
List of figures
List of tables
ABSTRACT
Chapter 1 INTRODUCTION
1.1 INTRODUCTION
1.2 ACCOMPLISHMENTS
Chapter 2 LITERATURE REVIEW
Chapter3 Vedic multiplier using barrel shifter IN VERILOG
3.1 VEDIC SUTRAS
3.1.1 NikhilamNavatascaramamDasatah sutra
3.2 BARREL SHIFTER
3.3 DESIGN OF VEDIC MULTIPLIER
3.3.1 Baseselectionmodule.
3.3.1 Powerindex determinant.
3.3.3 Multiplier Architecture
3.4 MODIFIED VITERBIALGORITHM

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Chapter 4 Introduction to FPGA design Flow
4.1 FPGA DESIGN FLOW
4.1.1 Design Entry
4.1.2 Synthesis
4.1.3. Implementation
4.1.3.1 Translate
4.1.3.2 Map
4.1.3.3 Place and Route
4.1.4 Device Programming
4.1.5 Design Verification
4.1.6 Behavioral Simulation
4.1.7 Functional simulation
4.1.8. Static Timing Analysis
Chapter 5 XILINX ISE 12.1 Design Suite Tutorial
Chapter 6 Simulation Results
Chapter 7 Conclusion and Future Scope
Bibliography and References

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List of figures

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Abstract
Multipliers are the most important units for processers. A multiplier is one of the key hardware
blocks in most of applications such as digital signal processing, encryption and decryption
algorithms in cryptography and in other logical computations. With advances in technology,
many researchers have tried to design multipliers which offer either of the following high
speed, low power consumption, regularity of layout and hence less area or even combination
of them in multiplier. The Vedic multiplier is considered here to satisfy our requirements.
Multipliers are the core component of any DSP applications and hence speed of the processor
largely depends on multiplier architecture. Up to now we have so many of multipliers is
implemented like array multiplier, Braun multiplier, modified booth multiplier and Wallace
tree multiplier but they cannot meet the high speed requirements in some applications.
Nowadays, Field Programmable Gate Array (FPGA) technology is widely used in digital
signal processing area because FPGA-based solution can achieve high speed due to its parallel
structure and configurable logic, which provides great flexibility and high reliability in the
course of design and later maintenance.
This project describes the implementation of an 8-bit Vedic multiplier enhanced in terms of
propagation delay when compared with conventional multiplier . In our design we have
utilized 8-bit barrel shifter which requires only one clock cycle for ‘n’ number of shifts.The
design is implemented and verified using FPGA and ISE Simulator. The core was
implemented on Xilinx Spartan-6 family xc6s1x75T-3-fgg676 FPGA. The propagation delay
comparison was extracted from the synthesis report and static timing report as well. The
design could achieve propagation delay of 6.781ns using barrel shifter in base selection
module and multiplier.

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CHAPTER 1
INTRODUCTION
Arithmetic operations such as addition, subtraction and multiplication are deployed in various
digital circuits to speed up the process of computation. Arithmetic logic unit is also
implemented in various processor architectures like RISC , CISC etc., In general, arithmetic
operations are performed using the packed-decimal format. This means that the fields are first
converted to packed-decimal format prior to performing the arithmetic operation, and then
converted back to their specified format (if necessary) prior to placing the result in the result
field. Vedic mathematics is an ancient technique with unique approach and it has got different
sutras. Vedic mathematics has proved to be the most robust technique for arithmetic
operations. In contrast, conventional techniques for multiplication provide significant amount
of delay in hardware implementation of n-bit multiplier. Moreover, the combinational delay of
the design degrades the
performance of the multiplier. Hardware-based multiplication mainly depends upon
architecture selection in FPGA or ASIC.
Vedic mathematics [1] is an ancient technique which was used in the time of Vedas. It has got
as many as 16 Sutras that can be used for different Arithmetic calculation. Vedic Sutras apply
to and cover almost every branch of Mathematics. They apply even to complex problems
involving a large number of mathematical operations. Vedic mathematics has proved to be the
most robust
technique for arithmetic operations. In contrast, conventional techniques for multiplication
provide significant amount of delay in hardware implementation of n-bit multiplier. Moreover,
the combinational delay of the design degrades the performance of the multiplier. Hardware-
based multiplication mainly depends upon architecture selection in fpga or asic. Application of
the Sutras saves a lot of time and effort in solving the problems, compared to the formal
methods presently in vogue. Though the solutions appear like magic, the application of the
Sutras is perfectly logical and rational. Since the ever growing technology and increased

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complexity in the design demands for the optimized area and delay. Researchers are constantly
working on towards the designing of optimized multiplier architecture. Critical path delay is
the key factor in determining the speed of the multiplier, In simpler form multiplication can be
developed using successive addition, subtraction and shifting operation as in literature.
Different algorithms are implemented for the multiplier and each technique has got its own
advantage and trade off in terms speed, area, and power consumption. Multiplier
implementation using Fpga has already been reported using different multiplier architectures
but the performance of multiplier was improved in proposed design by employing Vedic
multiplier using
modified “Nikhilam Navatascaramam Dasatah” sutra. The architecture in [1] is modified using
barrel shifter by which significant amount of clock cycles are reduced by virtue of which the
speed increases. The performance of the proposed multiplier is compared with the previously
implemented multipliers on Fpga. In this work we have put into effect a high speed Vedic
multiplier using barrel shifter. The sutra was implemented by modified design of “Nikhilam
Sutra” due to its feature of reducing the number of partial products. The barrel shifter used at
different levels of design drastically reduces the delay when compared to conventional
multipliers. The hardware implementation of Vedic multiplier using barrel shifter contributes
to adequate improvement of the speed in order to achieve high outturn.
1.2 ACCOMPLISHMENTS:

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This section describes the work done in the project. The accomplishments are categorized in to
four main phases of the project in chronological order:
1. Literature Review
a. Abrupt introduction of Vedic sutras.
b. describes the modified Nikhilam sutra architecture
c. Initially done a pen and paper work and designed a top level block diagram of
Multiplier consisting of different sub modules like BSM, PID, Adders, substractor.
2. Design Phase
a. Designed a top level module of Multiplier in Verilog HDL.
b. The sub modules are BSM, PID, Adders, Substractor. in
Verilog HDL.
3. Verification Phase
a. Wrote a self checking test bench consisting of a driver, monitor, checker
components in verilog.
b. Applied different test cases for the multiplier in the driver
section of the test bench and performed behavioral simulation
for the top level module.
4. Synthesis Phase
a. Performed logic synthesis, Translate, Map, Place and Route
processes and synthesis report is generated.

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Chapter 2
LITERATURE REVIEW
Present
In this paper we have described the implementation of a 8-bit Vedic multiplier which is enhanced in terms
of propagation delay when it is compared with conventional multiplier like modified booth multiplier,
Wallace tree multiplier , Braun multiplier, array multiplier. We use various Vedic multiplication techniques
for arithmetic operation .It has been found that the most efficient of all the sutra is Urdhva-triyagbhyam,
which gives minimum delay for multiplication of all types of numbers, either small or large numbers. For
‘n’ number of shifts only one clock cycle is required in our design, using 64-bitbarrel shifter. The design is
implemented and verified using ISE simulator and FPGA. Synthesis report and static timing report are used
for the comparison of propagation delay. The design uses barrelshifter in base selection module and
multiplier which achieves propagation delay of 6.781ns.
There are many applications of Vedic techniques. In this thesis we have focused more on speed and area as
the Vedic techniques are faster and occupy less space as compared to others.
Future
In future, we try to extend our project on,
FPGA Implementation of 64-bit fast multiplier using barrel shifter.
Future development in this proposed work is given as:

Pipelined Architecture: This architecture mainly focuses on reduced delay and increased speed.

Use of technique in signed multiplier: Vedic multipliers can also be used for signed numbers which
reduces the problem of calculation for large numbers.

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Chapter 3
Vedic multiplier using barrel shifter IN VERILOG
3.1 VEDIC SUTRAS
Vedic Sutras apply to and cover almost every branch of Mathematics. They apply even to
complex problems involving a large number of mathematical operations. Application of the
Sutras saves a lot of time and effort in solving the problems, compared to the formal methods
presently in vogue. Though the solutions appear like magic, the application of the Sutras is
perfectly logical and rational. The computation made on the computers follows, in a way, the
principles underlying the Sutras. The Sutras provide not only methods of calculation, but also
ways of thinking for their application.
Application of the Sutras improves the computational skills of the learners in a wide area of
problems, ensuring both speed and accuracy, strictly based on rational and logical reasoning.
Application of the Sutras to specific problems involves rational thinking, which, in the
process, helps improve intuition that is the bottom - line of the mastery of the mathematical
geniuses of the past and the present such as Aryabhatta, Bhaskaracharya, Srinivasa
Ramanujan, etc.,
Multiplier implementation using FPGA has already been reported using different multiplier
architectures but the performance of multiplier was improved in proposed design. By
employing Vedic multiplier using modified “Nikhilam Navatascaramam Dasatah” sutra. The
architecture in [1] is modified using barrel shifter by which significant amount of clock cycles
are reduced by virtue of which the speed increases. The performance of the proposed
multiplier is compared with the previously implemented multipliers on FPGA.
What we call “Vedic mathematics” is comprised of sixteen simple mathematical formulae
from the Vedas .
1. Ekadhikena Purvena
2. Nikhilam navatascaramam Dasatah
3. Urdhva - tiryagbhyam

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4. Paravartya Yojayet 978-
5. Sunyam Samya Samuccaye
6. Anurupye - Sunyamanyat
7. Sankalana - Vyavakalanabhyam
8. Puranapuranabhyam
9. Calana - Kalanabhyam
10. Ekanyunena Purvena
11. Anurupyena
12. Adyamadyenantya - mantyena
13. Yavadunam Tavadunikrtya Varganca Yojayet
14. Antyayor Dasakepi
15. Antyayoreva
16. Gunita Samuccayah.
3.1.1 NikhilamNavatascaramamDasatah sutra
The Nikhilam Sutra literally means “all from 9 and last from 10”. It is more efficient when the
numbers.
The formula can be very effectively applied in multiplication of numbers, which are nearer
to bases like 10, 100, 1000 i.e., to the powers of 10 . The procedure of multiplication using the
Nikhilam involves minimum number of steps, space, time saving calculation. The numbers
taken can be either less or more than the base considered.
The difference between the number and the base is termed as deviation. Deviation may be
positive or negative. Positive deviation is written without the positive sign and the negative
deviation, is written using Rekhank (a bar on the number). Now observe the following table.

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Number Base Number – Base Deviation
14 10 14 - 10 4
_
8 10 8 - 10 -2 or 2
__
97 100 97 - 100 -03 or 03
112 100 112 - 100 12
___
993 1000 993 - 1000 -007 or 007
1011 1000 1011 - 1000 011
Some rules of the method (near to the base) in Multiplication
a) Since deviation is obtained by Nikhilam sutra we call the method as Nikhilam
multiplication.
Eg : 94. Now deviation can be obtained by ‘all from 9 and the last from 10’ sutra i.e.,
the last digit 4 is from 10 and remaining digit 9 from 9 gives 06.
b) The two numbers under consideration are written one below the other. The deviations
are written on the right hand side.
Eg: Multiply 7 by 8.
Now the base is 10. Since it is near to both the numbers,
7
we write the numbers one below the other. 8

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-----
Take the deviations of both the numbers from the base and
represent _
7 3
_
the minus sign before the deviations 8 2
------
------
or 7 -3
8 -2
-------
-------
or remainders 3 and 2 implies that the numbers to be multiplied are both less than 10
c) The product or answer will have two parts, one on the left side and the other on the right.
A vertical or a slant line i.e., a slash may be drawn for the
demarcation of the two parts i.e.,
(or)
d) The R.H.S. of the answer is the product of the deviations of the numbers. It shall contain
the number of digits equal to number of zeroes in the base.
_
i.e., 7 3
_
8 2
_____________
/ (3x2) = 6
Since base is 10, 6 can be taken as it is.
e) L.H.S of the answer is the sum of one number with the deviation of the other. It can be
arrived at in any one of the four ways.

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i) Cross-subtract deviation 2 on the second row from the original number 7 in
the first row i.e., 7-2 = 5.
ii) Cross–subtract deviation 3 on the first row from the original number8 in the
second row (converse way of (i))
i.e., 8 - 3 = 5
iii) Subtract the base 10 from the sum of the given numbers.
i.e., (7 + 8) – 10 = 5
iv) Subtract the sum of the two deviations from the base.
i.e., 10 – ( 3 + 2) = 5
Hence 5 is left hand side of the answer.
_
Thus
7 3
_
8 2
¯¯¯¯ ¯¯¯¯¯¯¯¯
5 /
Now (d) and (e) together give the solution
_
7 3 7
_

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8 2 i.e., X 8
¯¯¯¯¯¯¯ ¯¯¯¯¯¯
5 / 6 56
Eg :
As shown in Fig.1, the multiplier and the multiplicand are written in two rows followed by the
differences of each of them from the chosen base, i.e., their compliments. There are two
columns of numbers, one consisting of the numbers to be multiplied (Column 1) and the other
consisting of their compliments (Column 2). The product also consists of two parts which are
demarked by a vertical line for the purpose of illustration. The right hand side (RHS) of the

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product can be obtained by simply multiplying the numbers of the Column 2 i.e., (2x9=18).
Common difference is found by subtracting either (91-2=89) or (98-9).
Assume that the multiplier is ‘X’ and multiplicand is ‘Y’. Though the designation of the
numbers is different but the architecture implemented is same to some extent for evaluating
both the numbers.
The mathematical expression for modified nikhilam sutra is given below.
P=X*Y= (2^k2)*(X+Z2*2^(k1-k2))+Z1*Z2. – (1)
Where k1, k2 are the maximum power index of input numbers X and Y respectively.
Z1 and Z2 are the residues in the numbers X and Y respectively.
3.2 BARREL SHIFTER
Basic BarrelShifter
A barrel shifter is simply a bit-rotating shift register. The bits shifted out the MSB end of the
register are shifted back into the LSB end of the register. In a barrel shifter, the bits are shifted
the desired number of bit positions in a single clock cycle. For example, an eight-bit barrel
shifter could shift the data by three positions in a single clock cycle. If the original data was
11110000, one clock cycle later the result will be 10000111.

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8-bit logical right shifter.
8 bit barrel shifter by using of mux

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3.3 DESIGN OF VEDIC MULTIPLIER
1. Design objectives
a. Designed a top level module of Multiplier in Verilog HDL.
b. The sub modules are BSM, PID, Adders, Substractor. in
Verilog HDL.
2. Wrote a self checking test bench consisting of a driver, monitor,
checker
components in verilog.
3. Applied different test cases for the multiplier in the driver section of
the test bench and performed behavioral simulation for the top level
module.
4. Performed logic synthesis, Translate, Map, Place and Route processes
and synthesis report is generated.
The hardware deployment of the above expression is partitioned into three blocks.
i. Base Selection Module
ii. Power index Determinant Module
iii. Multiplier.
3.3.1 Baseselectionmodule.
The base selection module has power index determinant (PID) as the sub-module along
with barrel shifter, adder, average determinant, comparator and multiplexer.
Operation:
An input 8-bit number is fed to power index determinant (PID) to interpret
maximum power of number which is fed to barrel shifter and adder. The output
of the barrel shifter is ‘n’ number of shifts with respect to the adder output and
the input based to the shifter. Now, the outputs of the barrel shifter are given to

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the multiplexer with comparator input as a selection line. The outputs of the
average determinant and the barrel shifter are fed to the comparator. The
required base is obtained in accordance with the multiplexer inputs and its
corresponding selection line.
Fig.1 Base Selection Module, BSM
3.3.1 Powerindex determinant.

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The input number is fed to the shifter which will shift the input bits by one clock cycle. The
shifter pin is assigned to shifter to check whether the number is to be shifted or not. In this
power index determinant (PID) the sequential searching has been employed to search for first
‘1’ in the input number starting from MSB. If the search bit is ‘0’ then the counter value will
decrement up to the detection of input search bit is ‘1’. Now the output of the decrementer is
the required power index of the input number.
Fig.2 Power Index Determinant
3.3.3 Multiplier Architecture
The base selection module and the power index determinant form integral part of multiplier
architecture. The architecture computes the mathematical expression in equation1.Barrel
shifter used in this architecture.
The two input numbers are fed to the base selection module from which the base is obtained.
The outputs of base selection module (BSM) and the input numbers ‘X’ and ‘Y’ are fed to the
subtractors. The subtractor blocks are required to extract the residual parts z1 and z2. The

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inputs to the power index determinant are from base selection module of respective input
numbers.
The sub-section of power index determinant (PID) is used to extract the power of the base and
followed by subtractor to calculate the value. The outputs of subtractor are fed to the
multiplier that feeds the input to the second adder or subtractor. Likewise the outputs of power
index determinant are fed to the third subtractor that feeds the input to the barrel shifter. The
input number ‘X’ and the output of barrel shifter are rendered to first adder/subtractor and the
output of it is applied to the second barrel shifter which will provide the intermediate value.
The last sub-section of this multiplier architecture is the second adder/subtractor which will
provide the required result.

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Fig.3 Multiplier Architecture
CHAPTER 4
FPGA DESIGN FLOW
4.1 FPGA DESIGN FLOW
FPGA contains a two dimensional arrays of logic blocks and interconnections between logic blocks.
Both the logic blocks and interconnects are programmable. Logic blocks are programmed to implement
a desired function and the interconnects are programmed using the switch boxes to connect the logic
blocks. To be more clear, if we want to implement a complex design (CPU for instance), then the
design is divided into small sub functions and each sub function is implemented using one logic block.
Now, to get our desired design (CPU), all the sub functions implemented in logic blocks must be
connected and this is done by programming the interconnects.
Internal structure of an FPGA is depicted in the following figure.

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FPGAs, alternative to the custom ICs, can be used to implement an entire System On one Chip (SOC).
The main advantage of FPGA is ability to reprogram. User can reprogram an FPGA to implement a
design and this is done after the FPGA is manufactured. This brings the name “Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when produced in bulk
amounts. But FPGAs are easy to implement with in a short time with the help of Computer Aided
Designing (CAD) tools (because there is no physical layout process, no mask making, and no IC
manufacturing).
Some disadvantages of FPGAs are,they are slow compared to custom ICs as they can’t handle vary
complex designs and also they draw more power.
Xilinx logic block consists of one Look Up Table (LUT) and one FlipFlop. An LUT is used to
implement number of different functionality. The input lines to the logic block go into the LUT and
enable it. The output of the LUT gives the result of the logic function that it implements and the output
of logic block is registered or unregistered out put from the LUT.
SRAM is used to implement a LUT.A k-input logic function is implemented using 2^k * 1 size SRAM.
Number of different possible functions for k input LUT is 2^2^k. Advantage of such an architecture is
that it supports implementation of so many logic functions, however the disadvantage is unusually
large number of memory cells required to implement such a logic block in case number of inputs is
large.
Figure below shows a 4-input LUT based implementation of logic block.

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LUT based design provides for better logic block utilization. A k-input LUT based logic block can be
implemented in number of different ways with trade off between performance and logic density.
An n-LUT can be shown as a direct implementation of a function truth-table. Each of the latch holds
the value of the function corresponding to one input combination. For Example: 2-LUT can be used to
implement 16 types of functions like AND , OR, A+not B .... etc.
A B AND OR NAND ...... ....
0 0 0 0 1
0 1 0 1 1
1 0 0 1 1
1 1 1 1 0
Interconnects
A wire segment can be described as two end points of an interconnect with no programmable
switch between them. A sequence of one or more wire segments in an FPGA can be termed as
a track.

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Typically an FPGA has logic blocks, interconnects and switch blocks (Input/Output blocks).
Switch blocks lie in the periphery of logic blocks and interconnect. Wire segments are
connected to logic blocks through switch blocks. Depending on the required design, one logic
block is connected to another and so on.
FPGA DESIGN FLOW
In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified
version of design flow is given in the flowing diagram.
4.1.1 DesignEntry
There are different techniques for design entry. Schematic based, Hardware Description
Language and combination of both etc. . Selection of a method depends on the design and
designer. If the designer wants to deal more with Hardware, then Schematic entry is the better
choice. When the design is complex or the designer thinks the design in an algorithmic way

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then HDL is the better choice. Language based entry is faster but lag in performance and
density.
HDLs represent a level of abstraction that can isolate the designers from the details of the
hardware implementation. Schematic based entry gives designers much more visibility into
the hardware. It is the better choice for those who are hardware oriented. Another method but
rarely used is state-machines. It is the better choice for the designers who think the design as a
series of states. But the tools for state machine entry are limited. In this documentation we are
going to deal with the HDL based design entry.
4.1.2 Synthesis
The process which translates VHDL or Verilog code into a device netlist formate. i.e a
complete circuit with logical elements( gates, flip flops, etc…) for the design.If the design
contains more than one sub designs, ex. to implement a processor, we need a CPU as one
design element and RAM as another and so on, then the synthesis process generates netlist for
each design element
Synthesis process will check code syntax and analyze the hierarchy of the design which
ensures that the design is optimized for the design architecture, the designer has selected. The
resulting netlist(s) is saved to an NGC( Native Generic Circuit) file (for Xilinx® Synthesis
Technology (XST)).

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4.1.3. Implementation
This process consists a sequence of three steps
1. Translate
2. Map
3. Place and Route
4.1.3.1 Translate
This process combines all the input netlists and constraints to a logic design file. This
information is saved as a NGD (Native Generic Database) file. This can be done using NGD
Build program. Here, defining constraints is nothing but, assigning the ports in the design to
the physical elements (ex. pins, switches, buttons etc) of the targeted device and specifying
time requirements of the design. This information is stored in a file named UCF (User
Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor etc.

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4.1.3.2 Map
This process divides the whole circuit with logical elements into sub blocks such that they can
be fit into the FPGA logic blocks. That means map process fits the logic defined by the NGD
file into the targeted FPGA elements (Combinational Logic Blocks (CLB), Input Output
Blocks (IOB)) and generates an NCD (Native Circuit Description) file which physically
represents the design mapped to the components of FPGA. MAP program is used for this
purpose.
4.1.3.3 Place and Route
PAR program is used for this process. The place and route process places the sub blocks from
the map process into logic blocks according to the constraints and connects the logic blocks.
Ex. if a sub block is placed in a logic block which is very near to IO pin, then it may save the
time but it may effect some other constraint. So trade off between all the constraints is taken
account by the place and route process. The PAR tool takes the mapped NCD file as input and
produces a completely routed NCD file as output. Output NCD file consists the routing
information.

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Place and Route PAR program is used for this process. The place and route process places
the sub blocks from the map process into logic blocks according to the constraints and
connects the logic blocks. Ex. if a sub block is placed in a logic block which is very near to IO
pin, then it may save the time but it may effect some other constraint. So trade off between all
the constraints is taken account by the place and route process. The PAR tool takes the
mapped NCD file as input and produces a completely routed NCD file as output. Output NCD
file consists the routing information.

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4.1.4 Device Programming
Now the design must be loaded on the FPGA. But the design must be converted to a format so
that the FPGA can accept it. BITGEN program deals with the conversion. The routed NCD
file is then given to the BITGEN program to generate a bit stream (a .BIT file) which can be
used to configure the target FPGA device. This can be done using a cable. Selection of cable
depends on the design.
4.1.5 DesignVerification
Verification can be done at different stages of the process steps.
4.1.6 Behavioral Simulation (RTL Simulation) This is first of all simulation steps; those are
encountered throughout the hierarchy of the design flow. This simulation is performed before
synthesis process to verify RTL (behavioral) code and to confirm that the design is functioning
as intended. Behavioral simulation can be performed on either VHDL or Verilog designs. In
this process, signals and variables are observed, procedures and functions are traced and
breakpoints are set. This is a very fast simulation and so allows the designer to change the
HDL code if the required functionality is not met with in a short time period. Since the design
is not yet synthesized to gate level, timing and resource usage properties are still unknown.

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4.1.7 Functional simulation (Post Translate Simulation) Functional simulation gives
information about the logic operation of the circuit. Designer can verify the functionality of
the design using this process after the Translate process. If the functionality is not as expected,
then the designer has to made changes in the code and again follow the design flow steps.
4.1.8. Static Timing Analysis This can be done after MAP or PAR processes Post MAP
timing report lists signal path delays of the design derived from the design logic. Post Place
and Route timing report incorporates timing delay information to provide a comprehensive
timing summary of the design.
Chapter 5
XILINX ISE 12.1 Design Suite Tutorial
1 . Click on Xilinx ISE Design Suite 12.1 Icon on desktop

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2 . ISE Project Navigator (M53 D) - ISE Design Suite Info center window will be
opened.
3. Press Ok .Then go to File menu . Select the New project .

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1. New Pop up window named New Project wizard appeared.
2. Enter the Project name in Name field.

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3. Select the location where you want to store the project by selecting the Location field
4. Working Directory is automatically select same location .
5. Select the HDL in Top Level Source Type present at bottom of window.

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6. Then press the NEXT .
7. Then it goes to Project Settings .

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8. In this project settings you can select the product details used to dump our program.

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9. After selecting the values click NEXT.
10. It goes to Project Summary tab .Then Click Finish.

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11. After that it Can back to ISE Project Navigator (M53 D) window .
12. Go to Project tab open the New Source.

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13. New Source Wizard pup up will be opend.
14. H

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ere we can select verilog Module.
15. Then enter the file name for new source.

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20.

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III. SIMULATION RESULTS AND DESIGN ANALYSIS
Comparison between conventional multipliers and proposed design is been projected below.
Around 75% of reduction in delay can be observed from the proposed design with respect to
array multiplier in Table I. whereas the conventional Vedic multiplier contributes to 43% of
reduction in delay with respect to array multiplier. The analysis provides much in depth
coverage between conventional multipliers and modified Vedic multiplier architecture.
TABLE-I.
DELAY COMPARISON BETWEEN VARIOUS MULTIPLIERS IMPLEMENTED ON
FPGA
Multiplier
type
Conventional
Multiplier(Arr
ay)
Vedic
Multiplie
r
Proposed
Multiplier
Delay(ns) 43.42 27 6.781
A. Timing summary
Speed grade: -3
Minimum period: 6.781ns (Maximum frequency: 147.4 MHz)
Maximum input arrival time before clock: 5.876 ns
Maximum output required time after clock: 17.682 ns
Maximum combinational path delay: 16.753ns
B. Timing Details
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for clock ‘clk’
Clock period: 6.781ns (frequency: 147.47 MHz)
Total no of paths / destination ports: 22313 / 104
Delay: 6.781ns (levels of logic=7)
Source: rsu2/power_index_determinant/temp_pow_0_1 (FF)
Destination: exponent2/ temp_5 (FF)
Source clock: clock rising
Destination clock: clock rising.

BARREL SHIFTER
C. Power Report
TABLE.II
POWER REPORT OF PROPOSED DESIGN
total Dynamic Quiescent
Supply
power(
mW)
64.21 0.4
7
63.74

BARREL SHIFTER
Fig.4 Post-Route Simulation
Fig.5 RTL schematic of multiplier

BARREL SHIFTER
Chapter 7
Conclusion and Future Scope
In our design, efforts have been made to reduce the propagation delay and achieved an
improvement in the reduction of delay with 45% when compared to array multiplier, booth
multiplier and conventional Vedic multiplier implementation on FPGA [4]. The high speed
implementation of such a multiplier has wide range of applications in image processing,
arithmetic logic unit and VLSI signal processing .
The future scope of this particular work can be extended in design of ALU’s in RISC
processor. We try to extend our project on
FPGA Implementation of 64-bit fast multiplier using barrel shifter.
Future development in this proposed work is given as:

Pipelined Architecture: This architecture mainly focuses on reduced delay and increased speed.

Use of technique in signed multiplier: Vedic multipliers can also be used for signed numbers which
reduces the problem of calculation for large numbers.

BARREL SHIFTER
REFERENCES
[1] Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, “High speed ASIC design of complex
multiplier using vedic mathematics” , Proceeding of the 2011 IEEE Students' Technology Symposium 14 -16
January, 2011, lIT Kharagpur, pp. 237-241.
[2] Shamsiah Suhaili and Othman Sidek, “Design and implementation of reconfigurable alu on FPGA”, 3rd
International Conference on Electrical & Computer Engineering ICECE 2004, 28-30 December 2004, Dhaka,
Bangladesh, pp.56-59.
[3] Sumit Vaidya and Deepak Dandekar, “Delay-power performance comparison of multipliers in vlsi circuit
design”, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010,
pp.47-56.
[4] P. Mehta, and D. Gawali, "Conventional versus Vedic mathematical method for Hardware implementation of
a multiplier," in Proceedings IEEE International Conference on Advances in Computing, Control, and
Telecommunication Technologies, Trivandrum, Kerala, Dec. 28-29, 2009, pp. 640-642.
[5] J. S. S. B. K. T. Maharaja, Vedic mathematics, Delhi: Motilal Banarsidass Publishers Pvt Ltd,(2010).
17

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