Personal Information
Unternehmen/Arbeitsplatz
Puducherry Area, India India
Branche
Electronics / Computer Hardware
Webseite
www.nxfee.com
Info
Product development experience on more than 5+years
Development product on:
1.Power consumption
2.High speed data transmission
3.Secure video processing
4.Secure digital modulation and demodulation
5.Signal processing application
Tags
vlsi ieee transaction 2018
vlsi design of an ml based power efficient motion
noise insensitive pll using a gate-voltage-boosted
vector processing aware advanced clock-gating tech
ulv turbo cache for an instantaneous performance b
the implementation of the improved omp for aic rec
sram circuits for true random number generation us
securing the present block cipher against combined
multilevel half rate phase detector for clock and
low power and fast full adder by exploring new xor
low complexity vlsi design of large integer multip
low complexity methodology for complex square-root
low phase noise ku band vco with optimal switched-
feedback based low-power soft-error-tolerant desig
fast neural network training on fpga using quasi n
extending 3 bit burst error-correction codes with
efficient fpga mapping of pipeline sdf fft cores
design of temperature aware low voltage 8 t sram i
design of an area efficient million-bit integer mu
design and fpga implementation of a reconfigurable
combating data leakage trojans in commercial and a
basic set trellis min max decoder architecture for
approximate sum of-products designs based on distr
approximate hybrid high radix encoding for energy-
approximate error detection with stochastic checke
high-throughput ldpc decoders
analysis and design of cost effective
an energy efficient programmable many core acceler
an efficient fault tolerance design for integer pa
algorithm and vlsi architecture design of proporti
a variable size fft hardware accelerator based on
a residue to-binary converter for the extended fou
a reconfigurable ldpc decoder optimized applicatio
a high accuracy programmable pulse generator with
a flexible wildcard pattern matching accelerator v
low-jitter pulse width control loop for high-speed
a fast locking
a fast and low complexity operator for the computa
a closed form expression for minimum operating vol
a 588 gbs ldpc decoder based on finite-alphabet me
a 128 tap highly tunable cmos if finite impulse re
vlsi ieee projects 2018
custom electronics board design
secure digital demodulation
signal processing and applications
secure video processing
high speed data transmission
ip development
semiconductor product
semiconductor ip design
nxfee innovation
nxfee
Mehr anzeigen
Dokumente
(27)Personal Information
Unternehmen/Arbeitsplatz
Puducherry Area, India India
Branche
Electronics / Computer Hardware
Webseite
www.nxfee.com
Info
Product development experience on more than 5+years
Development product on:
1.Power consumption
2.High speed data transmission
3.Secure video processing
4.Secure digital modulation and demodulation
5.Signal processing application
Tags
vlsi ieee transaction 2018
vlsi design of an ml based power efficient motion
noise insensitive pll using a gate-voltage-boosted
vector processing aware advanced clock-gating tech
ulv turbo cache for an instantaneous performance b
the implementation of the improved omp for aic rec
sram circuits for true random number generation us
securing the present block cipher against combined
multilevel half rate phase detector for clock and
low power and fast full adder by exploring new xor
low complexity vlsi design of large integer multip
low complexity methodology for complex square-root
low phase noise ku band vco with optimal switched-
feedback based low-power soft-error-tolerant desig
fast neural network training on fpga using quasi n
extending 3 bit burst error-correction codes with
efficient fpga mapping of pipeline sdf fft cores
design of temperature aware low voltage 8 t sram i
design of an area efficient million-bit integer mu
design and fpga implementation of a reconfigurable
combating data leakage trojans in commercial and a
basic set trellis min max decoder architecture for
approximate sum of-products designs based on distr
approximate hybrid high radix encoding for energy-
approximate error detection with stochastic checke
high-throughput ldpc decoders
analysis and design of cost effective
an energy efficient programmable many core acceler
an efficient fault tolerance design for integer pa
algorithm and vlsi architecture design of proporti
a variable size fft hardware accelerator based on
a residue to-binary converter for the extended fou
a reconfigurable ldpc decoder optimized applicatio
a high accuracy programmable pulse generator with
a flexible wildcard pattern matching accelerator v
low-jitter pulse width control loop for high-speed
a fast locking
a fast and low complexity operator for the computa
a closed form expression for minimum operating vol
a 588 gbs ldpc decoder based on finite-alphabet me
a 128 tap highly tunable cmos if finite impulse re
vlsi ieee projects 2018
custom electronics board design
secure digital demodulation
signal processing and applications
secure video processing
high speed data transmission
ip development
semiconductor product
semiconductor ip design
nxfee innovation
nxfee
Mehr anzeigen