Gene's law, Common gate, kernel Principal Component Analysis, ASIC Physical Design Post-Layout Verification, TSMC180nm, 0.13um IBM CMOS technology, Cadence Virtuoso, FPAA, in Spanish, Bruun E,

1. Wafer come with certain type of doping : n-type wafer, p-type wafer (tub).
CMOS technology (3um thick p-type wafer) need n-type substrate called n-well to build PMOS
NMOS its drain can not be lower than gate by one threshold, for PMOS drain can not be higher
than gate by absolute of one threshold voltage.
Automative radar for self driving car (blind spot detection, parking aid, cruse control)
Radar inspired from bats (echo location-> round trip time).
Doppler effect (speed doubler shift in the frequency)
silicon is not good for emitting light. Thus such as Gallium arsenide (GaAs) in light emitting diode.
Biasing provides proper current and voltage to make proper amplification in absence of signal.
Operating point: biasing values of current and voltage chosen in biasing task.
Common gate as TIA (OTRA).

2. 1.1 Activation Functions, ReLu, Hyperbolic Tangent, Logistic/Sigmoid Activation function, Pooling
Layers, SoftMax 0 Error Metrics ,Squared Error ,Log-loss ,00Training methods , Backpropagation/
Stochastic Backpropagation , Non-linear solvers (BFGS and variants) , MADALINE Rule (III) ,
000 Quantization and Sparseness ,Regularization ,Pruning ,Deep Compression ,
LITERATURE REVIEW 26 2.1 Network Topologies 26 2.1.1 Deep vs Shallow 26 2.1.2
Convolutional neural networks 28 1.4.4 BinaryConnect 1.5 Conclusion
[A Time-Mode Neural Network Architecture]
Incremental learning has been a long standing problem in machine learning [Incremental Event
Detection via Knowledge Consolidation Networks]
-Fully correlated same power (are same).
-uncorrelated signal add in power and fully correlated signals add in amplitude.
• kernel Principal Component Analysis - kPCA
FRACTIONAL ORDER CONTROLLERS AND APPLICATIONS TO REAL LIFE SYSTEMS
(Abandoned Thesis)Thesis for: PhD (submitted) AbandonedAdvisor: Prof. Dr M.S . Bhatia
- FinFET and multi-gate transistors have super-swing (sub-threshold slope) and low junction
leakage.
-characterize random signal: 1.statistics, pdf probability density function (mean, rms, signal power,
p-p value). 2. Time domain: how signal statistics change with time (how fast is changed)?
Autocorrelation function 3. Frequency domain: Fourier of autocorrelation function: power spectral
density (PSD). PSD provide same information as autocorrelation but in different domain. [Ali
Sheikholeslami, ISSCC video youtube]
-Oscillator Neural Networks (ONNs)
-

5. Root Mean Squared Error (RMSE)= ︎sqart((1/n)∑(yest − ytrue)2)
Root Mean Squared Error between the actual and estimated artifacts.
A variety of time-frequency transformations are available to capture temporal and spectral aspects
of the data simultaneously (e.g., Short-Time Fourier Transform (STFT) and Wavelet
Transformations (Discrete Wavelet Transform (DWT), and Continuous Wavelet Transform (CWT)
[39]). Fourier Transformations can model changes in the spectral characteristics but are incapable of
detecting the moment when these changes occur. The Short-Time Fourier Transform (STFT)
segments the data into multiple windows and applies the Fast-Fourier Transform in each of them,
the Stationary Wavelet Transform (SWT), otherwise known as Maximal Overlap Discrete Wavelet
Trans- form (MODWT) [41], to transform the ECG and motion reference data into the time -
frequency space. In contrast to the regular DWT, the output of each level of SWT contains the same
number of samples as the input data enabling us to construct a tensor with a consistent number of
samples for each wavelet decomposition stage. As a mother wavelet, we selected the Haar wavelet
[42]. [Application of Tensor Decomposition in Removing Motion Artifacts from the Measurements
of a Wireless Electrocardiogram]
Andrew Ng co-founder of Coursera
It is an American massive open online course provider founded in 2012 by Stanford University's
computer science professors Andrew Ng and Daphne Koller that offers massive open online
courses, specializations, degrees, professional and mastertrack courses. [Wikipedia]

6. The expression to identify the evaluation metrics are given in equations: (MLC = Multi-Label
Classification)
Hamming_Loss= 1/N sum from i=1 to i=N 1/L |MLC(xi,Yi)|
Accuracy = 1/N sum from i=1 to i=N (|MLC(xi)^Yi|/|MLC(xi)vYi|); ^ is intersection and v is union
Precision = 1/N sum from i=1 to i=N (|MLC(xi)^Yi)|/|MLC(xi)|)
Recall = 1/N sum from i=1 to i=N (|MLC(xi)^Yi)|/|Yi|)
F1-measure = 1/N sum from i=1 to i=N (|2xMLC(xi)^Yi)|/(|MLC(xi)|+|Yi|))
-Hamming loss gives the percentage of wrong labels to the total number of labels. Lower the
hamming loss, better is the performance of the method used. For an ideal classifier, hamming loss is
0.
-Accuracy of the multi-label classifier is defined as the proportion of the predicted correct labels to
the total number of labels for that instance. Overall accuracy is the average across all instances.
-Precision is the proportion of the predicted correct labels to the total number of actual labels
averaged over all instances. In other words, it is the ratio of true positives to the sum of true
positives and false positives averaged over all instances.
-Recall is the proportion of the predicted correct labels to the total number of predicted labels
averaged over all instances. In other words, it is the ratio of true positives to the sum of true
positives and false negatives averaged over all instances.
-F1 measure is given by the harmonic mean of Precision and Recall.
-Log loss, aka logistic loss or cross-entropy loss. Logarithmic Loss, or simply Log Loss, is a
classification loss function often used as an evaluation metric in Kaggle competitions. Since success
in these competitions hinges on effectively minimizing the Log Loss, it makes sense to have some
understanding of how this metric is calculated and how it should be interpreted.
Logloss = -log(1 / N)

7. evaluate the performance of the model, accuracy, which was calculated as the
percentage of correctly classified samples over all data, was utilized to compute
the score of the entire classification, and it was used in the analysis of
experimental data. In addition, considering the prevalent imbalance of data
distribution in the experimental data, the macro-average F-measure (Macro_F)
was also employed to describe the classification effects. Macro_F is more
sensitive to the classification quality, and it is defined as follows [50]:
is the precision, and N is the number of clusters. TP denotes true positives, FP
denotes false positives, and FN denotes false negatives. [An Accurate and Robust
Method for Spike Sorting Based on Convolutional Neural Networks]
-HIGH-SPEED MATERIALS FOR PCBS [https://cdn2.hubspot.net/hubfs/3869113/
High%20Speed%20Materials%20for%20PCBs%20-%20Final.pdf]
-Moore’s law, April 1965.
-Presidential Early Career Award for Scientists and Engineers.
B. A. Minch, “Analysis, synthesis, and implementation of networks of multiple-input translinear
elements,” Ph.D. dissertation, Calif. Inst. Technol., Pasadena, 1997.
E.Rodriguez-Villegas,“Low voltage and low power analog and digital design with the floating gate
MOS transistor (FGMOS),” Ph.D. dissertation, Univ. Seville, Seville, Spain, 2002.
-First computer machines were mechanical, then tubes, transistors, BJT, NMOS, CMOS,
- ASIC Physical Design Post-Layout Verification: (Verify with Calibre) http://
www.eng.auburn.edu/~nelson/courses/elec5250_6250/slides/ASIC-Verification-Calibre.pdf
- ELEC 5250/6250/6256 - Computer-Aided Design of Digital Circuits http://
www.eng.auburn.edu/~nelson/courses/elec5250_6250/
- Victor P. Nelson: https://www.eng.auburn.edu/~nelsovp/
- What is peer review? Peer review is designed to assess the validity, quality and often the
originality of articles for publication. Its ultimate purpose is to maintain the integrity of science
by filtering out invalid or poor quality articles. From a publisher’s perspective, peer review
functions as a filter for content, directing better quality articles to better quality journals and so
creating journal brands. Running articles through the process of peer review adds value to them.

8. For this reason publishers need to make sure that peer review is robust. https://
authorservices.wiley.com/Reviewers/journal-reviewers/what-is-peer-review/index.html
- Root locus theory: can be used to check pole-zero cancellation, how pole and zero move when
changing the gain.
- SOLOMON.SYSTECH.COM https://www.yumpu.com/user/solomon.systech.com
- PSPICE TSMC180nm.lib file RWN 04/18/2010 Newcomb: https://user.eng.umd.edu/
~newcomb/courses/spring2010/303/tsmc180nmcmos.lib
-
- ECE429 Lab2 - Tutorial : Inverter Schematic and Simulation, This tutorial introduces you to the
Cadence Virtuoso custom IC design platform. This platform serves as a central point for design
entry and provides various interfaces to other EDA tools. In this tutorial, we will first draw the
schematic of an inverter using Virtuoso Schematic Editor and then simulate it using Synopsys
HSPICE. http://www.ece.iit.edu/~vlsida/ECE429_tutorials/ECE429%20Lab%202%20-
%20Tutorial%20I_%20Inverter%20Schematic%20and%20Simulation.html
- Aperiodic signal is a periodic signal with very large period. Thus take integral in Fourier series as
from +/- infinity. [Ali Hajamiri]
- Fourier transform is special case of Laplace Transform when it is evaluated on jw axis. Fourier
transform inverse itself [Ali Hajamiri].
- Inverse Laplace Transform by Partial Fraction Expansion.
- However, due to the size limit of complementary metal–oxide–semiconductor (CMOS)
transistors, von Neumann-based computing systems are facing multiple challenges (such as
memory walls). As the number of transistors required by the neural network increases, the
development of neural networks based on the von Neumann computer is limited by volume and
energy consumption. As the fourth basic circuit element, memristor shines in the field of
neuromorphic computing. The new computer architecture based on memristor is widely
considered as a substitute for the von Neumann architecture and has great potential to deal with
the neural network and big data era challenge. [The Future of Memristors: Materials Engineering
and Neural Networks]
- R Pubsure uses cutting-edge machine learning trained on millions of published papers and
editorial corrections performed by industry-leading editors. Since the acquisition of UNSILO by
CACTUS Communications (R Pubsure's parent company) we've combined forces to strengthen
our manuscript evaluation engine. As a result, we are already seeing faster evaluations, superior
language suggestions and more accurate detection of references, tables and figures, etc. There's
more to come here, so stay tuned. https://pubsure.researcher.life
-
- Conflicts of interest Reviewers should decline to review a submission when they: Have a recent
publication or current submission with any author. Share or have recently shared an affiliation
with any author. Collaborate or have recently collaborated with any author. Have a close personal
connection to any author. Have a financial interest in the subject of the work. Feel unable to be
objective [https://www.hindawi.com/publish-research/reviewers/].
-
- LTspice for radio amateurs: https://robs-blog.net/2017/02/10/lt-spice-for-radio-amateurs-part-1/

9. -The LTSpice IV simulator : manual, methods and applications / [author Gilles Brocard. – Imprint.
– W a l d e n b u r g , 2 0 1 3 h t t p s : / / w w w . b i b l o s . p k . e d u . p l / S T /
2017/02/100000304469/100000304469_Brocard_TheLtspiceIvSimulator.pdf
- 0.13um IBM CMOS technology, Cadence Virtuoso, FPAA, in spanish: https://riudg.udg.mx/
bitstream/20.500.12104/79912/1/MCUCEI01065FT.pdf
- Principal Components Analysis (PCA) https://www.egr.msu.edu/annweb/pca.html
- Cryogenic CMOS interfaces for large-scale quantum computers: from system & device models
to circuits: Abstract: Quantum computers operate by processing information stored in quantum
bits (qubits), which must typically operate at cryogenic temperature. A practical quantum
computer will comprise thousands of qubits, thus requiring an electronic interface also operating
at cryogenic temperature to ensure integration and scalability of the whole system. Focusing on
the use of standard CMOS technology, we will explore the challenges in building such interface,
comprising modeling of the quantum/classical interface, devices modeling for cryogenic CMOS
and the design of high-performance cryogenic CMOS circuits. By demonstrating the cryogenic
operation of complex CMOS analog and digital systems, we will show that cryogenic CMOS is a
viable technology to enable large-scale quantum computing. Bio: Fabio Sebastiano holds degrees
in Electrical Engineering from University of Pisa, Italy (BSc, 2003; MSc, 2005) from Sant’Anna
school of Advanced Studies, Pisa, Italy (MSc, 2006) and from Delft University of Technology,
The Netherlands (PhD, 2011). From 2006 to 2013, he was with NXP Semiconductors Research
in Eindhoven, The Netherlands. In 2013, he joined Delft University of Technology, where he is
currently an Assistant Professor. He has authored or co-authored one book, ten patents, and over
60 technical publications. His main research interests are cryogenic electronics for quantum
applications, sensor read-outs and frequency references. Dr. Sebastiano was the co-recipient of
the best student paper award at ISCAS in 2008, the best paper award at IWASI in 2017 and the
best IP award at DATE in 2018. He is a senior member of IEEE, a TPC member for RFIC and a
Distinguished Lecturer of the IEEE Solid-State Circuit Society.
https://www.youtube.com/watch?v=C1US7IPcN_0&t=854s
- artefact suppression is achieved by applying the pole shift technique of a tuneable pseudo-
resistor structure in combination with a digital adjustment of the threshold voltage. [Artefact-
Suppressing Analog Spike Detection Circuit for Firing-Rate Measurements in Closed-Loop
Retinal Neurostimulators]
- Wavelets for EEG Analysis [https://www.intechopen.com/online-first/wavelets-for-eeg-analysis]
- We believe that the realization of AOC memristors is an impor- tant milestone toward real
optoelectronic NC that possesses the advantages of both photonics and electronics. For
traditional electrical memristors, a high voltage or current is generally required to tune their
memconductance. Such strong electrical stimuli may result in 1) high power consumption, 2) a
large amount of Joule heat, 3) microstructural change accelerated by the Joule heat, and 4) high
crosstalk in memristor crossbars. These issues can be addressed with our AOC mem- ristor
given the very low light power densities (≈20 μW cm−2) required to operate it. On the other
hand, optoelectronic computing using our AOC memristor is more practically feasible than
purely optical computing[18–20] owing to the simple structure and easy fabrication of this
device. Future research might explore neuronal functions (e.g., integrate and fire) using our AOC
memristor to enable optoelectronic SNNs. [All-Optically Controlled Memristor for
Optoelectronic Neuromorphic Computing]
- Cadence Tutorial for Cadence version 6.1: http://www-classes.usc.edu/engr/ee-s/477p/
cadencetutorial.pdf

10. - EE 477L MOS VLSI Circuit Design Professor Alice C. Parker: http://www-classes.usc.edu/engr/
ee-s/477p/
- Sanjit Mitra: https://minghsiehece.usc.edu/directory/faculty/profile/?lname=Mitra&fname=Sanjit
- The Designer’s Guide to Spice and Spectre: https://www.springer.com/gp/book/9780792395713
- https://www.quora.com/unanswered/What-is-the-best-way-to-learn-Cadence-Virtuoso
h t t p s : / / b o o k s . g o o g l e . a e / b o o k s ?
id=6GfjBwAAQBAJ&pg=PA130&lpg=PA130&dq=kenneth+kundert+transient+analysis+theory&s
ource=bl&ots=663KniRqpm&sig=K44ihHxLg2Nns2VnfdkjZMqdMG4&hl=en&sa=X&redir_esc=
y#v=onepage&q=kenneth%20kundert%20transient%20analysis%20theory&f=false
- Fitzpatrick, Dennis. Analog design and simulation using OrCAD Capture and PSpice. Newnes,
2017. https://www.sciencedirect.com/book/9780081025055/analog-design-and-simulation-using-
orcad-capture-and-pspice
- Stanford CNFET Model: https://nano.stanford.edu/stanford-cnfet-model
- Bruun E., Noise properties of CMOS current conveyors, in 1996 IEEE International Symposium
on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, Atlanta, GA,
USA, 1996, pp. 1276–1291.
- Bruun, E. (1998). Worst case estimate of mismatch induced distortion in complementary CMOS
current mirrors. Electronics Letters.
- IEEE Medal of Honor Goes to Transistor Pioneer Chenming Hu The Life Fellow brought
transistors into the third dimension. How the Father of FinFETs Helped Save Moore's Law -
IEEE …Hu has been called the Father of the 3D Transistor due to his development of the Fin
Field Effect Transistor in 1999. Intel, the first company to implement FinFETs in its products,
called the invention the most radical shift in semiconductor technology in more than 50 years.
[Design of Energy-Efficient Electrocorticography Recording System for Intractable Epilepsy in Implantable
Environments]