This document describes a hardware implementation of a genetic algorithm based digital color image watermarking system. The system embeds a watermark image into the luminance channel (Y channel) of a host color image after converting the image from RGB to YUV color space. A genetic algorithm is used to determine optimal intensity values in the host image for embedding the watermark image bits invisibly. The proposed design is implemented as a custom integrated circuit for real-time watermarking of images as they are captured by a digital camera. Synthesis results show that the design can operate at 5ns clock speed and consumes a maximum power of 73.84mW when implemented on an Altera Cyclone II FPGA.