A lecture to motivate the students towards the core domain VLSI Design , especially Verification ..

1. WHY SYSTEM VERILOG?

2. INTRODUCTION
• Most of the fresh engineering graduates who wish
to enter the core domain of VLSI design always
have a doubt, “Why System Verilog”?
• Because many trainers might have taught them
that either VHDL or Verilog are enough for VLSI
Design.
Yes , no doubt they are..
• Especially language like Verilog , which is similar
to C in many respect appears to be more promising
also.

3. Contd..
• So, before discussing why System Verilog,let us
first explore what is actually this SV(System
Verilog) ?
• This SV is not only a HDL but includes all of the
features of the hardware verification language
(HVL).Hence it is also known as HDVL.Hardawre
Design and Verification Language.
• Also many designers believe that System Verilog is
the first truly industry-standard language to cover
design, assertions,transaction level modeling and
coverage driven constrained random verification.

4. contd
• Also, the System Verilog has almost similar
structure and syntax of Verilog with many extra
features. i.e SV is a super set of Verilog
• So, learning SV is not that difficult and writing a
test bench in SV is not that complex.
• To understand the syntax and structure and
constructs available in SV let us consider a simple
design example of an 8-bit full adder.

5. 8-Bit Full Adder
• For the 8-bit full adder A[7:0] ,B[7:0] and Cin are
inputs & Sum[7:0] , Cout are outputs . The block
diagram of the FA is shown below.

6. System Verilog Code For FA
• module my_FA( Sum, Cout,A,B,Cin);
input logic[7:0]A;
input logic[7:0]B;
input logic Cin;
output logic [7:0]Sum;
output logic Cout ;
logic [8:0] result;
assign result = A+B+Cin;

7. contd
23 June 2020 7yayavaram@yahoo.com
• assign Sum = result[7:0];
assign Cout = result[8];
endmodule
• If you oserve the SV code it is very much similar to
Verilog .
• Except that a new data variable logic is defined ,to
avoid the confusion between reg and wire which are
normally used in Verilog HDL.

8. Why System Verilog?
23 June 2020 8yayavaram@yahoo.com
• It’s a proven fact that SV is the industry accepted
Hardware Verification Language(HVL).
• If you consider the VHDL or Verilog there are some
inadequacies. Because their support for high level
data types , object oriented programming,assertions,
functional coverage and declarative constraints is
very poor.
• So, the code size in SV is relatively compact when
compared to so called the conventional HDLs.

9. contd
23 June 2020 9yayavaram@yahoo.com
• The feature Direct Programming interface allows, C
functions to be called directly from System Verilog
(and vice versa) without using the PLl .
(Programming Language Interface).
• Many Extensions to Always blocks for modelling
combinational, latched or clocked processes are
provided which were not available in either in
VHDL or in Verilog.

10. contd
23 June 2020 10yayavaram@yahoo.com
• So, the designer can’t use a separate language for
verification if he opts either Verilog or VHDL as
there are so many integration problems.
• Also, technically speaking all VHDL capabilities are
directly available in SV.
• Again the SV unifies all the points mentioned above
under a consistent syntax ,coherent semantics with
minimal race conditions and with global
optimization opportunities.

11. 23 June 2020 11yayavaram@yahoo.com
THANQ FOR WATCHINIG
GOOD LUCK !!