Personal Information
Unternehmen/Arbeitsplatz
Bengaluru Area, India, Karnataka India
Beruf
Technical Program Committee Member DVCon USA 2018 at DVCon USA 2018
Branche
Electronics / Computer Hardware
Webseite
www.cvcblr.com/blog
Info
A dynamic technical evangelist in the domain of VLSI design, based in Bangalore – India. My areas of interest are the advanced verification solutions and methodologies such as SystemVerilog, OVM, VMM, Assertion-Based Verification, formal verification etc.
As CTO @CVC (www.cvcblr.com) my job is to stream line all the technical deliverables, meeting customer expectations and defining roadmap for near future. I provide support to leading edge semiconductor design companies on their verification methodologies and challenges.
I have the right mix of both Design house and EDA industry and hence can appreciate the strengths and weaknesses of both.
In my previous employment with various des...
Tags
systemverilog
asic
vlsi
verilog
eda
cvc vmm systemverilog verilog debug verdi novas
ovm
vmm
Mehr anzeigen
Präsentationen
(3)Dokumente
(1)Personal Information
Unternehmen/Arbeitsplatz
Bengaluru Area, India, Karnataka India
Beruf
Technical Program Committee Member DVCon USA 2018 at DVCon USA 2018
Branche
Electronics / Computer Hardware
Webseite
www.cvcblr.com/blog
Info
A dynamic technical evangelist in the domain of VLSI design, based in Bangalore – India. My areas of interest are the advanced verification solutions and methodologies such as SystemVerilog, OVM, VMM, Assertion-Based Verification, formal verification etc.
As CTO @CVC (www.cvcblr.com) my job is to stream line all the technical deliverables, meeting customer expectations and defining roadmap for near future. I provide support to leading edge semiconductor design companies on their verification methodologies and challenges.
I have the right mix of both Design house and EDA industry and hence can appreciate the strengths and weaknesses of both.
In my previous employment with various des...
Tags
systemverilog
asic
vlsi
verilog
eda
cvc vmm systemverilog verilog debug verdi novas
ovm
vmm
Mehr anzeigen