8051

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Presentation on
8051 and Addressing
Modes
By :
Faizan Ali Khan
Mail @
faizankhan031@gmail.com

MuP and MuC
Microcontroller
 It itself is a small computer
 It has a CPU, RAM,ROM and other
peripherals embedded on a single
chip
 It has I/O ports and Serial Com port
 Has separate m/ry to store program
and data
 Designed to perform specific tasks.
Ex – mouse, mobile….
 Has its own inbuilt memory
 Lower clock frequency and low
performance simple CPU arch

Microprocessor
•
•

Its just a CPU of a computer
It just has a CPU

•

None. Requires extra devices.(8155
for I/O, 8250 for Serial Com port)
Same memory
Unspecific tasks.
Ex – gaming, websites….
Doesn’t have
higher clock frequency and a high
performance pipelined parallel CPU
arch

•
•

•
•


Harvard and VON Neumann
Harvard architecture

Von Neumann architecture

•

•

Has shared s/g s and memory

•

Not possible

•

Program can be easily modified by
itself since it is stored in read-write
memory
Slower

•

•
•

•
•

program
memory

Has physically separate memory
and s/g s for code and data memory
Program memory and data memory
can be accessed simultaneously
It is impossible for program
contents to be modified by the
program itself
Faster , as Program memory and
data memory are accessed
simultaneously
Pipelining is possible
Processor can complete an
instruction in one cycle
processor

Data
memory

•

•
•

Not possible
Processor requires 2 clock cycles to
complete an instruction

processor

Program memory
And
Data memory


8051 Internal Block Diagram


Register Banks
Register Banks with Addresses

Selecting the Register Banks


Stack
• The stack is a section of RAM used by the CPU to
store information temporarily. This information could
be data or an address. The CPU needs this storage
area since there are only a limited number of registers
• Stack is LIFO
• Register used to access the stack is called a Stack
Pointer (SP). Default value of a SP is 07H
• PUSH and POP


Special Function Registers


SFRs
• Accumulator, A – Used in logical and arithmetic
operations
• Register B – Used only in MUL and DIV
• Program Counter – It points to the address of the next
instruction to be executed.
• Stack Pointer - Used to access the stack
• Data Pointer – Address of higher bytes from external
RAM


Program Status Word


PCON
The Power Control SFR is used to control the 8051's
power control modes
SMOD is used to double the effective baud rate
of the 8051's serial port.


Timer Control (TCON)
Special Function
Register
.


BIT

SYMBOL

FUNCTION

7

TF1

Timer 1 Overflow flag. Set when timer rolls from all 1's to 0,i.e overflows. Cleared
when processor vectors to execute interrupt service routine located at program
address 001Bh.

6

TR1

Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by
program to off timer.

5

TF0

Timer 0 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor
vectors to execute interrupt service routine located at program address 000Bh.

4

TR0

Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by
program to halt timer.

3

IE1

External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received.
Cleared when processor vectors to interrupt service routine.

2

IT1

External interrupt 1 signal type control bit. Set to 1 by program to enable external
interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a
low-level signal on external interrupt 1 to generate an interrupt.

1

IE0

External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received.
Cleared when processor vectors to interrupt service routine.

0

IT0

External interrupt 0 signal type control bit. Set to 1 by program to enable external
interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a
low-level signal on external interrupt 0 to generate an interrupt.


Timer Mode Control
(TMOD) Special
Function Register
.


BIT

SYMBOL

FUNCTION

7

Gate

6

C/T

Set to 1 by program to act as a counter by counting pulses from external
input pins 3.5. Cleared to zero by program to act as a timer by counting
internal frequency.

5

M1

Timer/counter operating mode select bit 1. Set/cleared by program to
select mode.

4

M0

select mode.

3

GATE

2

C/T

Set to 1 by program to make timer 0 act as a counter by counting pulses
from external input pin 3.4. Cleared to zero by program to make timer act
as a timer by counting internal frequency.

1

M1

select mode.

0

M0

select mode.

To control start and stop of timer 1.
If GATE=0, SETB TR1 starts timer and CLR TR1 stops timer

To control start and stop of timer 0.
If GATE=0, SETB TR1 starts timer and CLR TR1 stops timer


SCON
Serial Control Register

.


SMO

.



SM1

SM2

REN

TB8

RB8

TI

SM0 SM1 Mode Baud Rate
----------------------0
0
0
f osc/12
0
1
1
variable
1
0
2
f osc/32 or f osc/64

 SM2 Multiprocessor Mode Control Bit
1 = Multi-processor mode
0 = Normal mode


REN Receiver Enable Bit

1 = Receive Enable
0 = Receive Disabled
 TB8 Transmit Bit 8
Enabled only for modes 2 and 3. Made 0 as its not used
 RB8 Receive Bit 8
Used in modes 2 and 3. it gets a copy of Stop Bit when an 8 bit data is received


RI, TI Serial Interrupts

RI is set to indicate receipt of a serial word and TI is set to indicate completion of a serial transmission and
ready to transfer another byte.


RI

Interrupt Enable
Register
.


Interrupt Enable Register
EA

----

ET2

ES

ET1

EX1

ET0

EX0

• EA - disable all the interrupts. EA=0, no interrupt is acknowledged.
EA=1, interrupt source is enabled or disabled
• ----- for future use
• ET2 – enables or disables timer 2 overflow interrupt
• ES - enables or disables the serial port interrupt
• ET1 - enables or disables timer 1 overflow interrupt
• EX1 - enables or disables external interrupt 1
• ET0 - enables or disables timer 0 overflow interrupt
• EX0 - enables or disables external interrupt 0


Interrupt Priority
Register
.


Interrupt Priority Register
.

----

•
•
•
•
•
•
•

----

PT2

PS

PT1

PX1

PT0

PX0

---- reserved
PT2 – timer2 interrupt priority bit
PS – serial port interrupt priority bit
PX1 – external interrupt 1 priority bit
PX0 – external interrupt 0 priority bit

Addressing
Modes


Addressing modes
• The 8051 instructions use eight addressing modes.
These are:
1.Register
2. Direct
3. Indirect
4. Immediate
5. Relative
6. Absolute
7. Long
8. Indexed

Register Addressing
Register Addressing
• In this mode the data, which the instruction operates on, is in one of eight
registers labeled R0 to R7 (Rn, in general). These registers are to be found
in one of four register banks, only one of which can be active at any one
time. The active bank may be selected by using bit 3 and bit 4 of the PSW
(rs0 & rs1). On power-up or reset, the default register bank is bank 0.
• For example, to logically OR the contents of accumulator A with that of
register R3, the following instruction is used:
ORL A, R3
• and the op-code is 01001011B. The upper five bits, 01001, indicate the
instruction, and the lower three bits, 011, the register.


Direct Addressing
•

Instructions using direct addressing consists of two bytes: op-code and address.

•

Such instructions can access any on-chip variable or hardware register. Note that the
most significant bit of the direct address determines which area in the on-chip is to
be accessed. An address between 00H and 7FH accesses a location in the low-order
on-chip RAM.

•

Any address with bit 7 = 1 refers to one of the special function registers. It is not
necessary to remember the addresses of these special function registers. The
assembler usually understands and converts the mnemonic of a special function
register, e.g. P2 for Port 2, into the appropriate address. An example of a direct
addressing instruction is

•

MOV P1, A
which transfer the content of the accumulator to Port 1. The direct address of Port 1
(90H) is determined by the assembler and inserted as byte 2 of the instruction. The
source of the data, the accumulator, is specified implicitly in the op-code.

Indirect Addressing

• In this mode of addressing the instruction performs an
operation on the data whose address is contained in
register R0 or R1. Instructions using indirect addressing
are single byte instructions. In 8051 assembly language
the symbol @ before R0 or R1 denotes indirect
addressing. An example of an indirect addressing
instruction is
SUBB A, @R0
• This instruction performs the operation:
(A)  (A) – (C) – ((R0)).

Immediate Addressing
• In an instruction that uses immediate addressing, the operand
of the instruction is given as the byte that follows the op-code.
The operand may be a numeric constant, a symbolic
variable, or an arithmetic expression using
constants, symbols, and operators.
• In assembly language we use the symbol # before an operand
to denote immediate addressing. An example of an instruction
using immediate addressing is
ANL A, #77
which performs the operation: (A)  (A) · #77.


Relative Addressing
•

•

•

Sometimes this is also called program counter relative addressing. This addressing
mode is used only with certain jump instructions. A relative address (or offset) is an
8-bit signed value, which is added to the program counter to form the address of the
next instruction executed.
The range for such a jump instruction is –128 to +127 locations. Although the range
is rather limited, relative addressing does offers the advantage of providing
position-independent code (since absolute addresses are not used). For example, the
instruction
JZ rel
performs the following operations:
(PC) ¬ (PC) + 2
IF (A) = 0
THEN (PC) ¬ (PC) + rel
ELSE continue
The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice.


Absolute Addressing
• There are only two instructions that use this addressing:
ACALL (absolute call) and AJMP (absolute jump).
• These instructions perform branching within the current 2K
page of program memory. The branch address is obtained by
successively concatenating the five high-order bits of the
program counter, bits 5 – 7 of the op-code, and the second byte
of the instruction.

• The diagram illustrate how this is done:


Absolute Addressing


Long Addressing
• Only two instructions use this addressing mode. These
instructions are LCALL addr16 and LJMP addr16.
• Both of these are three byte instructions with the op-code
being the first byte and the following two bytes are the address
high-byte and address low-byte respectively.
• These instructions enable the program to branch to anywhere
within the full 64 K-bytes of program memory address space.


Indexed Addressing
• In this mode the 16-bit address in a base register is added to a positive
offset to form an effective address for the jump indirect instruction JMP
@A+DPTR, and the two move code byte instructions MOVC
A,@A+DPTR and MOVC A,@A+PC.
• The base register in the jump instruction is the data pointer and the
positive offset is held in the accumulator. For the move instructions the
base register can either be the data pointer or the program counter, and
again the positive offset is in the accumulator. The operations of these three
instructions are as follows:
JMP @A+DPTR (PC) (A) +(DPTR)
MOVC A,@A+DPTR (A)  ((A) + (DPTR))
MOVC A,@A+PC (PC)  (PC) + 1
(A)  ((A) + (PC))


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