7. FPGA Core Fabric Cyclone IV FPGAs—Logic Element LUT In1 In2 In3 In4 Carry In0 Carry In1 Carry Out0 Carry Out1 LUT chain Register chain General routing Local routing General routing Register chain Clock REG
8. Cyclone IV FPGA’s Embedded Memory Cyclone IV Device M9K Block Data Widths: Feature Cyclone IV Benefit Block size 9 Kbits Memory with parity bits Dual-port read during write behavior New data or old data Flexibility and ease of use Parity bit Yes Usability for high-reliability apps Clock enables 4 Increased flexibility and reduced power Read and write enables 4 Increased flexibility and reduced power Routing Dedicated Higher performance since routing isn’t shared with any other on-chip resource Mode Data Width Configurations Single Port or Simple Dual Port ×1, ×2, ×4, ×8/9, ×16/18, and ×32/36 True Dual Port ×1, ×2, ×4, ×8/9, and ×16/18
11. Supported I/O Standards Type I/O Standard Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X Differential I/O SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
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20. Programmable Logic is Found Everywhere! Cellular Basestations Wireless LAN Switches Routers Optical Metro Access Broadband Audio/video Video display Studio Satellite Broadcasting Medical Test equipment Manufacturing Card readers Control systems ATM Navigation Entertainment Secure comm. Radar Guidance and control Wireless Networking Wireline Entertainment Broadcast Automotive Instrumentation Military Security & Energy Management Servers Mainframe RAID SAN Copiers Printers MFP Computers Storage Office Automation Consumer Automotive Test, Measurement, & Medical Communications Broadcast Military & Industrial Computer & Storage
Cyclone IV FPGA Device Family By Altera Corporation
Welcome to the training module on the Cyclone IV FPGA device family. This presentation highlights the key features of device. We will discuss the features and variants, core architecture, I/Os, clock management, external memory interface, high speed transceivers and the hard IP for PCI express.
Altera’s Cyclone IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs. Now with a transceiver variant, the Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs.
Providing power and cost savings without sacrificing performance, along with a low-cost integrated transceiver option, the Cyclone IV devices are ideal for low-cost, small-form-factor applications in the wireless, wire-line, broadcast, industrial, consumer, and communications industries.
The key points about the Cyclone IV GX devices include high functionality, lower system cost and the optimization for lower power. The high functionality: as evidence by the ample on-chip resources, large amount of logic, embedded memory & multipliers as well as the new 3 gigabit per second transceivers. We have the smallest density FPGA with transceivers so we can offer a lower price point than our competitors. We have an integrated hard IP block implementation for PCI-Express functionality. We optimized the XCVR I/O and associated clocking resources for low cost. These devices only need two power supplies. In subsequent slides, we’ll discuss why this is so important…and finally all the devices come in low cost wirebond packages. The Cyclone IV devices are also optimized for lower power. The 60nm process is very mature and thus lower cost compared to other newer fab processes. It is also optimized for lower power. We estimate that the device dissipates less than 1.5 watts of total power.
This Page shows the block diagram of Cyclone IV device. It has PCI Express hard IP blocks along with High Speed transceivers which are embedded in Core fabric. Clock management is handled by GPLL block. MPLL block is another circuitry which is used to clock High speed transceivers.
Cyclone IV devices leverage the same core fabric as the very successful Cyclone series devices. The fabric consists of LEs, made of 4-input look up tables or LUTs, memory blocks, and multipliers. Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM memory. The M9K blocks can be configured as single port, simple dual port, or true dual port RAM, as well as FIFO buffers or ROM.
The embedded memory structure consists of columns of M9K memory blocks(9,216 bits per block including parity) that you can configure to provide various memory functions, such as RAM, shift registers, ROM, and FIFO buffers. There are two clock-enable control signals for each port (port A and port B)
Each embedded multiplier consists of a Multiplier stage, Input and output registers, Input and output interfaces. The multiplier stage of an embedded multiplier block supports 9 × 9 or 18 × 18 multipliers as well as other multipliers between these configurations. Depending on the data width or operational mode of the multiplier, a single embedded multiplier can perform one or two multiplications in parallel.
Cyclone-IV i/o architecture consist of: Selectable I/O standards per each I/O bank. Programmable drive strength, slew rate, and on-chip termination. Finally, it also selectable on each individual I/O options: open drain output, bus-hold, pull-up resistor, PCI-clamp diode.
Cyclone IV devices support LVDS, BLVDS, reduced swing differential signalling (RSDS), mini-LVDS, and point-to-point differential signalling (PPDS). The LVDS I/O standards also support the transceiver reference clocks on top of the existing general purpose I/O clock input features.
Cyclone IV GX devices support two types of PLLs: Multi-purpose PLLs (MPLLs) and General-purpose PLLs (GPLLs): ■ MPLLs are used for clocking the transceiver blocks. They can also be used for general-purpose clocking when not used for transceiver clocking. ■ GPLLs can be used for general-purpose applications in the fabric and periphery, such as external memory interfaces. Some of the GPLLs can support the transceiver clocking.
In Cyclone IV devices, dedicated clock input pins, PLL counter outputs, dual-purpose clock I/O inputs, and internal logic can all feed the clock control block for each GCLK. Dedicated clock pins can directly feed the global clock multiplexer or the PLLs.
Cyclone IV devices can easily interface with a broad range of external memory devices, including DDR2 SDRAM,DDR SDRAM, and QDR II SRAM. External memory devices are an important system component of a wide range of image processing, storage, communications, and general embedded applications.
Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that can operate independently. These blocks support multiple industry-standard communication protocols, as well as Basic mode, which can be used to implement your own proprietary protocols. Each transceiver channel has its own pre-emphasis and equalization circuitry, which can be set at compile time to optimize signal integrity and reduce bit error rates. Transceiver blocks also support dynamic reconfiguration, allowing you to change data rates and protocols on-the-fly.
The transceiver channels are primarily driven by clocks from the MPLLs within the same transceiver block. Cyclone IV GX transceivers support flexible clocking architecture that allows implementation of multiple protocols, while fully utilizing all available transceiver resources. For example, you can use one of the MPLL to drive the Tx and the Rx channels at the same rates, while the remaining MPLL can be used as a GPLL.
Cyclone IV GX transceivers are designed to support the serial protocols listed as shown in this page.
In the block diagram, you can see the transceivers which can also be used for non PCI Express application. The interface to the hard IP block supports a PIPE 2.0 compliant interface. The hard IP PCI Express block offers support for end-port and root-port applications.
This page gives some of the key features of Hard IP which consist of End-point, Root-port dual-mode core, it supports Integrated transaction layer (TL), data link layer (DLL), physical interface/media access control (PHY/MAC), and transceivers.
Cyclone-IV has its applications in several fields including consumer, automotive, Test and Measurement, Communication Broadcast, military and industrial.
This slide shows a typical application of Cyclone-4 being used for a Broadcast Video Capture card. The device provides several advantages over the competitor solutions including: The flexibility to convert to and from any standard, lower cost through FPGA integration & simplified PCB, as well as simplified power management. The other benefit of replacing it ’ s external transceivers is the reduction in power consumption by as much as 30%. This savings is realized through integrated transceivers and removal of parallel I/O that typically interface from FPGAs to external transceivers.
This slide is in continuation to previous one which explains about the Next-generation challenges: Price/cost pressure, Advancing video standards like 4K2K, 3D, 8 bit to 10/12 bit color, 120 Hz to 240 Hz refresh rates and Responds to new requirements faster. With Cyclone IV GX: Lower costs are achieved through the replacement of 36 LVDS transmission pairs with only 4 transceiver channels, Reduced cables & connectors and a simplified board design. FPGA processing handles new video standards, thus enhancing image and signal quality. The device’s flexibility supports evolving requirements and changing algorithms thus allowing you to achieve quicker revenue.
Thank you for taking the time to view this presentation on Cyclone IV. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Altera site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility. You may visit Element 14 e-community to post your questions.