Processor architecture design using 3 d integration technologies
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3D Integration Technologies, End of Moore's law, stacking approach, monolithic approach
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Processor architecture design using 3 d integration technologies
- 1. PROCESSOR ARCHITECTURE DESIGN USING 3D INTEGRATION TECHNOLOGIES YUAN XIE PENNSYLVANIA STATE UNIVERSITY Presented by AVINASH REDDY PENUGONDA 674394454UIC 1
- 2. Contents Title Overview Background & Motivation Introduction to 3D Integration Technology Types of 3D Integration technologies & techniques Monolithic Through Silicon Via (TSV) Design approaches of 3D Processor Architecture Advantages & Challenges of 3D stacking technology Conclusion Future Work References UIC 2
- 3. Overview Why 3D Architecture? What challenges does 2D architecture face? Different 3D Architecture Design Approaches Advantages of using a 3D design Challenges of using of 3D design UIC 3
- 4. Background & Motivation: Currently we are using 14nm FinFet Technology and 10nm is expected in 2017 We are almost at the end of Moore’s Law, what’s next big thing?? UIC 4
- 5. Challenges in Current 2D Design Performance Power Consumption UIC 5 Interconnect delay is increasing and we need to address that!! Interconnect power consumption is also increasing!! Images source: www.eetimes.com
- 6. Challenges in 2D design Use of Multi-Core & SMT Architectures has Memory Bandwidth problem Can we further reduce the form factor of the chip? UIC 6
- 7. Introduction to 3D Integration Technologies 3D Integration Technologies Monolithic Approach Sequential device process First build multiple active device layers on a single wafer and then build interconnects among them Use vertical connections of 50nm in size Stacking Approach Separate processing of each layer and integrate them using bonding technology More Practical Examples: Wire bonded, MicroBump, Contactless and TSV TSV offers greatest vertical interconnect densityUIC 7 3D IC Stacking
- 8. Introduction to 3D Integration Techniques Face-to-Face bonding Two wafers stacked so top metal layers are connected Device Layer connection: Microbump I/O connections: TSV Face-to-Back bonding Top metal layer of one die is bonded with the substrate of the other die. Device Layers connection: TSV I/O connections: TSV UIC 8 Illustration of F2F and F2B 3D bonding
- 9. Through Silicon Via (TSV) 3D stacking process steps TSV formation For layer and I/O connection. TSV size range: 0.2um to 10um Wafer thinning To reduce the impact of TSV’s Thinner the wafer smaller the TSV is Wafer Thickness range: 10um to 100um Aligned wafer/die bonding: Wafer to Wafer bonding / Die to Wafer bonding TSV size, length, pitch density and bonding techniques are important consideration for 3D microprocessor design UIC 9
- 10. Design Approaches of 3D Processor Architecture Wire length reduction Global Interconnect delay does not scale down well with technology 3D Integration reduce global interconnects, so critical path reduced and so delay reduced Wire length reduced by factor of square root of number of layers used. Advantages: Improved performance and reduced power consumption. Power Reduction As Interconnect length reduces, power consumption also reduces. 7% to 46% power reduction using 3D arithmetic circuits. For Intel Pentium 4, power reduction by 15% due to reduction in wire length. UIC 10
- 11. Design Approaches of 3D Processor Architecture Latency Improvement As interconnect length and critical path length reduces, latency is improved. Tool used: 3D Cacti tool 3D Cache design: Divide the bank into multiple layers and reduce global interconnects, so fast cache access time Latency reduction is around 25% using two layer 3D cache. Intel Pentium 4 processor: Showed 15% performance improvement on 2 layer 3D integration due to restructuring of heavy pipelined wires. Downsides: Increases design complexity latency improvement varies on partitioning strategies and 3D process technology. UIC 11
- 12. Design Approaches of 3D Processor Architecture Memory Bandwidth Improvement Many core architectures, SMT deteriorated the Memory Wall problem 3D integration can mitigate the memory wall problem. How?? Idea: stack memory on top of CMP, so that memory bandwidth is improved. Intel Core2 Duo processor 2 cores stacked with 32MB DRAM cache Reduced the access time by 13% on average with negligible temperature increase. Pico Server Project DRAM main memory on top of CMP, so Cache not required. Replace Cache area with more simple cores to improve performance Up to 14% performance improvement and 55% power reduction. As the number of cores increase, 3D memory stacking becomes more important as it gives more memory bandwidth for all cores UIC 12
- 13. Design Approaches of 3D Processor Architecture Heterogeneous Integration Stacking of different technologies with greater flexibility Non-volatile Memory Stacking Stack non-volatile memory on top of processors Advantages: Non-volatile, low access power, zero standby power Challenges: Fabrication, complex Optical Device Layer Stacking Integrate Optical Die with Processor to improve Off-chip Communication with I/O devices/ memory Corona Architecture, HP Labs with nano- photonic communication has 20 terabit/sUIC 13 An illustration of 3D heterogeneous architecture with non-volatile memory stacking and optical die stacking
- 14. Design Approaches of 3D Processor Architecture Cost-effective Architecture Increased integration density results in large die size, so low yield To increase yield, partition a large 2D processor into multiple smaller dies and stack them together So, depending on 2D processor size, use 3D stacking as cost effective solution 3D Network on Chip (NoC) Architecture General Purpose On-Chip interconnection network architecture to connect processor cores Cores communicate using packed-switched protocol Many design challenges needs to be addressed to combine 3D IC with NoC to form a 3D NOC design. UIC 14
- 15. Advantages of 3D Integration Improved Performance Reduced Power Consumption Reduced form factor Improved Memory Bandwidth Cost-effective Architecture UIC 15
- 16. Challenges of 3D Architecture Design Thermal management: Due to increased power density Design Complexity 3D IC Manufacturing Challenges Design tools and methodologies: EDA tools to design new architectures 3D testing issues: Lack of DFT techniques UIC 16
- 17. Conclusion: 3D Integration is the one of the next big things in Semi- Conductor Industry TSV is considered a more practical design approach It has all the benefits (Performance, Power, Area) which are now difficult to reap with scaling down process technologies UIC 17
- 18. Future work Thermal issues need to be addressed EDA tools need to be developed Testing techniques need to be developed and many more!! UIC 18Image source: 3D IC Challenges by Wally Rhines, CEO, Mentor Graphics
- 19. References Process Architecture Design Using 3D Integration Technologies by Yan Xie http://electronicsforu.com/newelectronics/circuitarchives/view_article.asp? sno=1173&id=11332&article_type=8&b_type=new www.eetimes.com www.extremetech.com UIC 19