1. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012 819
Compact Modeling of Perpendicular-Anisotropy
CoFeB/MgO Magnetic Tunnel Junctions
Yue Zhang, Weisheng Zhao, Member, IEEE, Yahya Lakys, Jacques-Olivier Klein, Member, IEEE,
Joo-Von Kim, Member, IEEE, Dafiné Ravelosona, and Claude Chappert, Member, IEEE
Abstract—Magnetic tunnel junctions (MTJs) composed of fer-
romagnetic layers with perpendicular magnetic anisotropy (PMA)
are of great interest for achieving high-density nonvolatile memory
and logic chips owing to its scalability potential together with
high thermal stability. Recent progress has demonstrated a ca-
pacity for high-speed performance and low power consumption
through current-induced magnetization switching. In this paper,
we present a compact model of the CoFeB/MgO PMA MTJ, a
system exhibiting the best tunnel magnetoresistance ratio and
switching performance. It integrates the physical models of static,
dynamic, and stochastic behaviors; many experimental parame-
ters are directly included to improve the agreement of simula-
tion with experimental measurements. Mixed simulation based on
the 65-nm technology node of a magnetic flip-flop validates its
relevance and efficiency for MTJ/CMOS memory and logic chip
design.
Index Terms—Compact modeling, magnetic tunnel junction
(MTJ), perpendicular magnetic anisotropy (PMA), spin transfer
torque (STT).
I. INTRODUCTION
SHRINKING of the complementary metal–oxide–
semiconductor (CMOS) fabrication node below 90 nm
leads to high static power in memory and logic chips due
to increasing leakage currents [1]. Emerging nonvolatile
technologies are of great interest to overcome this issue, and
spintronic devices, such as magnetic tunnel junction (MTJ)-
based nanopillars, are becoming one of the more promising
candidates for the next generation of nonvolatile memory
devices and logic chips, due to their potential for high access
speed, easy integration with CMOS processes, and technology
maturity [2]–[4]. An MTJ nanopillar is mainly composed
of three thin films, namely, a thin oxide barrier and two
ferromagnetic (FM) layers [see Fig. 1(a)]. As a result of the
tunnel magnetoresistance (TMR) effect [5], the nanopillar
resistance, i.e., RP or RAP, depends on the relative orientation,
i.e., parallel (P) or antiparallel (AP), of the magnetization of
the two FM layers. In standard applications, the magnetization
Manuscript received July 20, 2011; revised November 14, 2011; accepted
November 28, 2011. Date of publication January 6, 2012; date of current
version February 23, 2012. This work was supported in part by the French
NANOINNOV Program through Contract SPIN and in part by the European
FP7 Program through Contract MAGWIRE (257707). The review of this paper
was arranged by Editor J. C. S. Woo.
The authors are with the Institut d’Electronique Fondamentale, CNRS
UMR 8622, University of Paris-Sud 11, 91405 Orsay, France (e-mail:
weisheng.zhao@u-psud.fr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2011.2178416
Fig. 1. (a) Vertical structure of an MTJ nanopillar composed of CoFeB/
MgO/CoFeB thin films. (b) STT switching mechanism: the MTJ state changes
from P to AP as the positive direction current IP→AP > IC0; on the contrary,
its state will return as the negative direction current IAP→P > IC0.
of one FM layer is pinned, whereas the other is free to
take the two orientations corresponding to resistances RP
and RAP [4]. By using crystalline MgO barriers, the TMR
ratio = (RAP − RP )/RP of MTJ nanopillars can reach more
than 600% at room temperature [6], [7]. This allows the state
of MTJs to be easily detected by CMOS sense amplifiers [8].
Much of academic and industrial research efforts are
presently focused on developing efficient strategies for switch-
ing magnetization in MTJs [9]–[14]. One promising method
relies on using spin transfer torques (STTs) in MTJs based
on CoFeB/MgO, which involve low threshold currents IC0
and well-understood mechanisms for switching [11], [12].
In addition, only a bidirectional current is needed for MTJ
switching [see Fig. 1(b)]. This greatly simplifies the CMOS
switching circuits and therefore allows for higher density than
other approaches. However, some unexpected effects have been
discovered using this approach in small MTJs (e.g., for lateral
sizes of 40 nm), such as erroneous state switching with reading
currents and short retention times [13]. These problems are
mainly related to the use of in-plane magnetic anisotropies,
which do not lead to a sufficiently high-energy barrier E to
ensure thermal stability [14], as described by
E =
μ0MS × V × HK
2
(1)
where Hk is the anisotropy field, μ0 is permeability in free
space, Ms is the saturation magnetization, and V is the volume
of the free layer. This issue greatly limits the potential for
further miniaturization of MTJs, and other storage principles
have been investigated to overcome these hurdles [15]–[17].
0018-9383/$31.00 © 2012 IEEE

2. 820 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012
One possible solution involves the use of perpendicular
magnetic anisotropy (PMA) in CoFeB/MgO structures [15]–
[17], because it allows high-energy barriers to be attained for
small size structures < 40 nm while maintaining the possibility
for fast-speed operation, high TMR ratios, and low threshold
currents. The possibility to obtain perpendicular anisotropy in
CoFeB-based systems was first demonstrated for a TbCoFe/
CoFeB/MgO/CoFeB/TbCoFe nanopillar, but this structure ex-
hibited a low TMR ratio [15]. Recent progress in materials engi-
neering involving perpendicular CoFeB/MgO/CoFeB systems
has led to TMR ratios of up to 120% [16], with even lower
IC0 and faster switching speeds than in-plane anisotropy MTJs
[17]. Another advantage of PMA systems is that it can store the
data with circular elements, which are less immune to issues re-
lated to reproducibility associated with the elliptical structures
required for in-plane-based systems. Other methods have been
also investigated to improve the thermal stability and help MTJ
size scaling. For instance, based on the exchange bias storage
principle, a thermally assisted STT was demonstrated in an
MTJ with two anti-FM layers [18], [19]. While such structures
provide the best thermal stability, the additional heating and
cooling operations greatly increase the switching latency up to
20 ns, which is too long for gigahertz high-speed applications.
We believe that the combination of the PMA and the STT for
the MTJ will provide the best strategy for constructing new
generation of memory and logic chips.
In this paper, we present the first compact model of the
CoFeB/MgO/CoFeB PMA MTJ switched by STTs that inte-
grates the tunnel resistance effect and physical models related
to the static, dynamic, and stochastic aspects of the STT. This
model will be useful for IC design of hybrid MTJ/CMOS
systems [20]–[22] by allowing for direct analysis of the area
and energy performance and facilitating the optimization for
different applications [23]–[26]. This model is programmed
with the Verilog-A language [27], which is compatible with
standard CMOS computer-aided design tools (e.g., Cadence
platform) [28] and provides an easy parameter interface. In
order to help the reader to set the parameters with a configura-
tion corresponding to experimental results, we give their default
values in Table I. The parameters are dependent on the material
composition and structures of the MTJ nanopillar. For the same
magnetic process and material composition, only the variables
can be modified to optimize the circuit performance addressing
different applications. The simulation of a writing circuit and a
nonvolatile magnetic flip-flop (MFF) [29] has been performed
to validate this compact model.
The rest of this paper is organized as follows: In the next
section, we describe the physical models of PMA MTJ and
STT switching. In Sections III and IV, we demonstrate the
mixed simulations of this model with the CMOS 65-nm design
kit [30]. A discussion and concluding remarks are provided in
Section V.
II. PHYSICAL MODEL OF THE STT PMA MTJ
In order to optimize memory and logic circuit design, the
capacity to extract performance criteria, such as speed, area,
reliability, and power, from hybrid MTJ/CMOS simulations is
TABLE I
PARAMETERS AND VARIABLES PRESENT IN THE FITTING FUNCTIONS
important. The physical models presenting the static, dynamic,
and stochastic behaviors of the STT PMA MTJ are required
to be electrically integrated in the compact model. First, the
physical model gives the resistances of the MTJ depending
on its magnetic configuration (P or AP) and its bias voltage;
second, it defines the current thresholds required to switch
between both configurations; and, finally, it takes into account
the switching delays, including stochastic fluctuations. Note
that the compilation speed of this model should be fast enough
to ensure the transient simulation of very large scale integra-
tion circuits; consequently, some physical models such as the
Landau–Lifshitz–Gilbert equation for the precessional motion
of magnetization in the free layer [31] were discarded.
A. MgO Barrier Tunnel Resistance Model
The physical model of the tunnel junction conductance was
introduced in 1970 [32]. The resistance value mainly depends
on the oxide barrier height and the interfacial effect between the
oxide barrier and the FM layers.
A simplified equation obtained from this model is inte-
grated into the compact model to calculate the resistance of
the CoFeB/MgO/CoFeB MTJ [19], as shown in the following
equation:
RP =
tox
F × ϕ1/2
× Area
× exp(1.025 × tox × ϕ1/2
) (2)
where RP is the resistance of the MTJ in the parallel state, ϕ =
0.4 is the potential barrier height of crystalline MgO [7], tox
is the thickness of the oxide barrier, and Area is the MTJ area
(see Table I). F is a factor calculated from the resistance–area
product (R · A) value of the MTJ, which depends on the mate-
rial composition of the three thin layers. For this model, R · A
is defined as parameter = 10 Ω · μm2
, which gives F = 332.2
with (2).

3. ZHANG et al.: COMPACT MODELING OF PERPENDICULAR-ANISOTROPY CoFeB/MgO MTJs 821
B. Bias-Voltage-Dependent TMR Model
The TMR effect is a key factor for the sensing mechanism
of spin memory and logic circuits. For instance, the error rate
caused by the mismatch variation of CMOS transistors will be
greatly increased as the TMR ratio is reduced [8]. Thereby, a
high TMR ratio is strongly expected to ensure reliable sensing,
which is particularly important for logic chips where there are
no error-correction circuits [33]. However, it was found that
the TMR ratio decreases with reading bias voltage Vbias [7]. In
order to describe this behavior, the following equation extracted
from the theory shown in [34] is included:
TMRreal =
TMR(0)
1 +
V 2
bias
V 2
h
(3)
where TMRreal is the real value of the TMR ratio during
simulation, TMR(0) is the TMR ratio with 0-V bias voltage,
and Vh is the bias voltage as TMRreal = 0.5 × TMR(0). For
this model, the default value of TMR(0) is set to 120% [16],
and Vh = 0.5 V. Based on (2) and (3), the resistance of the MTJ
in the antiparallel state, i.e., RAP, can be defined as
RAP = RP × (1 + TMRreal). (4)
C. Static Model of STT Switching
The STT switching statics in the PMA MTJ is mainly based
on the calculation of threshold or critical current Ic0, which can
be expressed by [16]
Ic0 = α
γe
μBg
(μ0MS)HKV = 2α
γe
μBg
E (5)
where E is the barrier energy [see also (1)], α is the magnetic
damping constant, γ is the gyromagnetic ratio, e is the elemen-
tary charge, μB is the Bohr magneton, V is the volume of the
free layer, and kB is the Boltzmann’s constant. Their default
values are shown in Table I. Equation (5) shows that Ic0 is
proportional to the perpendicular anisotropy field Hk, whereas
the calculation of Ic0 in the in-plane anisotropy MTJ is more
complex as it mainly depends on the demagnetization field Ms
[11], [12]. This explains the Ic0 reduction for the PMA MTJ.
Note that the spin accumulation effects are neglected in this
compact model, and spin polarization efficiency factor g is
obtained with the following equation [35]. It provides the best
agreement with the experimental results [16]. Thus
g = gsv ± gtunnel (6)
where the sign depends on the free-layer alignment. gsv and
gtunnel are the spin polarization efficiency values in a spin valve
and tunnel junction nanopillars, respectively. They are both
predicted by Slonczewski, i.e.,
gsv = −4 + P− 1
2 + P
1
2
3 (3 + cos θ)
4
−1
(7)
gtunnel =
P
2(1 + P2 cos θ)
(8)
Fig. 2. Comparison of the STT dynamic model with the measured data. The
diameter of the MTJ is set to 105 nm to meet the experimental setup.
where P is the spin polarization percentage of the tunnel
current, and θ is the angle between the magnetization of the
free and reference layers [11], [36].
D. Switching Dynamic and Stochastic Models
The switching dynamics of the STT in the PMA MTJ
is presented in [17], and (9) shows the dependence of the
switching current Iwrite value with the duration. The increase
of Iwrite and the decrease of Ic0 both contribute to scaling
down the switching latency, which also suggests the methods to
optimize the tradeoff between the area and speed performance
of spin chips. In Section V, we will demonstrate an example of
circuit optimization based on this compact model. The average
switching time is given by
1
τ
=
⎡
⎣ 2
C + ln π2ξ
4
⎤
⎦ μBPref
em(1 + Pref Pfree)
(Iwrite − Ic0)
(9)
where C ≈ 0.577 is the Euler’s constant; ξ = E/kBT is the
activation energy in units of kBT; Pref and Pfree are the
tunneling spin polarizations of the reference and free layers (we
assume that Pref = Pfree = P for this compact model); and m
is the magnetic moment of the free layer.
The initial temperature T variation is one of the major causes
of stochastic STT switching, and it also has an important impact
on data retention according to the Néel–Brown model [37]. In
order to take into account this temperature dependence effect, T
is a value randomly drawn from a uniform distribution between
−25 ◦
C and 75 ◦
C, which is a standard requirement of digital
ICs [27]. This allows the thermal fluctuation to be studied with
this model.
E. Fitting the Models With Experimental Results
In order to achieve good agreement with experimental para-
meters and high simulation accuracy, all the integrated physics
models have been verified using MATLAB [38] with the exper-
imental measurements shown in [15]–[17]. For instance, Fig. 2

4. 822 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012
Fig. 3. (a) Model symbol under the Spectre simulator. (b) DC simulation of
the STT PMA MTJ (the red and black curves describe the state switching from
AP to P and from P to AP, respectively).
shows the good agreement of the STT PMA dynamic model
with the experimental data extracted from [17]. For each fit,
only the diameter of the assumed circular MTJ is varied to
meet different experimental setups (e.g., 40 nm in [16] and
105 nm in [17]). For the hybrid MTJ/CMOS simulation, these
two technologies should be based on the same node; thereby,
the default diameter value of the MTJ is set to 65 nm (see
Table I).
III. ELECTRICAL COMPACT MODEL AND SIMULATIONS
A. Compact Model of the PMA MTJ and DC Simulation
Based on the aforementioned physical models, we pro-
grammed the compact model with Verilog-A and developed the
symbols under the Spectre simulator (Cadence Platform) [28]
[see Fig. 3(a)].
DC simulation, as shown in Fig. 3(b), was first performed
to verify the static behavior model functionality. The diameter
of the MTJ is set to 40 nm to meet the experimental setup
[16]. In this simulation, the critical current switch magneti-
zation from the P state to the AP state is ∼72 μA, whereas
the reverse switch critical current is ∼28 μA. These results
show the good agreement between static behavior physical
models and measured data and confirm the strong switching
asymmetry between the two states shown in the experimental
measurements of CoFeB/MgO PMA MTJs [16]. It is due to
the different spin polarization efficiency factors g in the P and
AP states [see (6)–(8)]. We can also describe the asymmetric
voltage dependence for the two MTJ states, which is caused by
the reduction of the TMR ratio under a bias voltage [see (3)]
[6] [7].
B. Transient Simulation
Transient simulation, as shown in Fig. 4, was then performed
to verify the agreement of the dynamic behavior between
physical models and experimental measurements. We find that
the switching delay is inversely proportional to the writing
current, as described in (9). The static breakdown voltage of
this MTJ is set to 1.5 V, which leads to a maximum current of
633.75 μA that can be generated with the default configuration
(see Table I). In this case, the switching duration can be down
Fig. 4. Transient simulation of the PMA MTJ demonstrates the integration of
the dynamic model and helps one to study the tradeoff between die area and
switching speed.
Fig. 5. Statistical simulation of the PMA MTJ. Each time, four runs are
performed with the same parameters, and the stochastic switching effect due
to the thermal fluctuation can be obtained.
to ∼0.5 ns, which potentially allows for an ∼2-GHz operating
frequency. This paper confirms the potential application of the
PMA MTJ as a base for logic and memory chips. For logic
computing, high currents can be sent to ensure fast speed, but
for memory applications, small currents are used to provide
high densities.
Statistical simulation, as shown in Fig. 5, was at last per-
formed to verify the stochastic behavior of the STT in the PMA
MTJ. As aforementioned, the initial temperature is generated
at random in the range from −25 ◦
C to 75 ◦
C. Four runs are
performed each time with the same parameters. We clearly find
the stochastic effect due to the thermal fluctuation with low
switching currents, for instance, 100 μA, as shown in Fig. 5.
However, this effect can be greatly minimized by increasing
the current value, which confirms that high currents not only
increase the speed but also improve the reliability, which is one
of the most important requirements for logic chips where error-
correction circuits cannot be used to ensure high speeds.
IV. HYBRID CIRCUIT SIMULATION WITH
THE COMPACT MODEL
Beyond the single-model simulation shown in the previous
section, hybrid MTJ/CMOS circuits have been also simulated
to validate the compact model. By using our compact model

5. ZHANG et al.: COMPACT MODELING OF PERPENDICULAR-ANISOTROPY CoFeB/MgO MTJs 823
Fig. 6. Full writing schematic for the STT writing approach, which is com-
posed of two modified inverters and logic control circuits.
and CMOS design kit, the power, speed, and area performance
of the hybrid circuits can be analyzed to obtain the best design
for specific applications. Here, two examples will be presented.
The first example concerns a simple writing circuit, which
dominates the power and area of the hybrid circuits [39]. The
second involves an STT PMA MTJ-based nonvolatile MFF
[29], which is the key element to provide zero standby power
for logic circuits and instant-on capability.
A. STT PMA MTJ Writing Circuit
Two nMOS (MN0–1) and two pMOS (MP0–1) transistors
have been designed as the main circuit to generate the bidirec-
tional current to switch a couple of MTJs in the complementary
state (see Fig. 6). Two transistors are always left open and the
others closed. Through two NOR and three NOT logic gates,
the “Input” and “EN” signals control the current direction and
activation, respectively.
In order to generate the maximum current flowing through
the couple of MTJs, both transistors (one pMOS and one
nMOS) should operate in their linear region above threshold
voltage VTH [40]. In this case, VDS 2(VGS − VTH) for the
nMOS transistor and VDS 2(VGS − VTH) for the pMOS
transistor. Their resistances Rop and Ron can be approximately
expressed by (10) and (11), and the generated current can be
obtained through (12). The aforementioned equations are given
as follows:
Ron =
1
μnCox
W
L (VGS − VTH)
(10)
Rop =
1
μpCox
W
L (VSG − |VTH|)
(11)
Iwrite =
Vdda
Rp + Rap + Ron + Rop
(12)
where μn is the electron mobility, μp is the hole mobility, Cox
is the gate oxide capacitance per unit area, W is the channel
width, L is the channel length, VGS is the gate–source voltage,
and VTH is the threshold voltage of the MOS transistor.
From (10)–(12), we find that the most efficient method to
improve the current value is by increasing W, but this leads
to significant area overhead. Fig. 7 shows a study of area,
speed, and energy performance for this circuit. Here, only the
area of four transistors (MN0–1 and MP0–1) has been taken
Fig. 7. High dependence of (solid line) circuit switching speed and (dotted
line) energy dissipation versus die area with four transistors (MN0–1 and
MP0–1) shown in Fig. 6.
Fig. 8. Full schematic of the nonvolatile MFF based on STT PMA MTJs.
into account as that of the logic control circuit is the same
for different simulation. Strong dependence between area and
speed is shown in Fig. 7, as the area is smaller than 0.2 μm2
.
The speed improvement becomes less significant for larger
areas and saturates at ∼1.1 GHz, which is different from the
2-GHz value obtained with a single-model simulation. There
are two reasons for this: First, Vdda is set to 2 V as 2.2 V is the
breakdown limit for 65-nm technology [30]; second, there are a
couple of MTJs. Thus, the bias voltage for each one cannot be
larger than 1 V.
The energy of each switching operation has been calculated
with (13) based on the simulation results. We also find a
threshold point, i.e., ∼ 0.1 μm2
, below which the energy is
nearly the same for whatever the size. The energy will be
rapidly increased with a smaller area due to the extremely long
switching duration as current Iwrite approaches threshold Ic0
[see also (9)], i.e.,
Eoperation = Vdda × Iwrite × Duration. (13)
The region around crossing point A of the two curves can
be localized. It can be considered as a good tradeoff among
the area (∼ 0.096 μm2
or 30 F2
), power (∼1 pJ), and speed
(∼500 MHz) performance of this switching circuit and be

6. 824 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012
Fig. 9. Simulation of the MFF (see also Figs. 6 and 8). (a) FF logic behaviors
can be correctly produced, and the nonvolatile state can be retrieved after only
one clock signal. (b) Comparison of two simulations with different delays
between the rising edge of “CLK” and “Input” signals. To ensure the correct
operation of the MFF, the delay of “CLK” after the “Input” signal should be
longer than ∼1.7 ns.
suitable to build up both logic and memory chips. This simu-
lation can also help to analyze the circuits with special require-
ments, such as high operating frequency (e.g., 800 MHz).
B. STT PMA MTJ Nonvolatile MFF
The master–slave flip-flop (FF) is one of the most important
elements in logic circuits, which stores and synchronizes in-
termediate computing data [37]. Nonvolatile MFFs have been
intensely studied since 2006 and are considered as another
important application of MTJ nanopillars [29], [41]. Fig. 8
shows the schematic of this MFF, where MN0, MN1, MN4, and
MP0–MP3 transistors constitute a precharge sense amplifier
[8], [29]. Combining with the writing circuit shown in Fig. 6,
the master register of an FF can be built up to store the
intermediate data in a nonvolatile state and the falling edge of
“CLK” drives the switching and reading of the MTJ.
The logic behavior of the MFF has been simulated, as shown
in Fig. 9(a). The “Input” signal is correctly reproduced at the
output under the synchronization of the “CLK” signal as the
enable signal “EN” is activated (see also Fig. 6). Due to the
nonvolatility of the MTJ, the previous saved state “0” or “1”
before power off can be retrieved after one cycle of “CLK.”
This advantageous performance allows the system embedded
with the MFF to be completely shut down during the “idle”
state and powered on instantly.
Different from the conventional FF [42], there is an im-
portant delay between the input and output signals, which
would limit the operating frequency. In order to investigate this
extra latency, Fig. 9(b) shows a comparison of two simulation
cases with different delays between the rising edge of “Input”
and “CLK.” Erroneous CLK (“CLK-E”) and correct CLK
(“CLK-C”) start ∼1.6 and ∼1.7 ns after the input signal,
respectively. We can find that “Output-C” driven by “CLK-C”
correctly reproduces the input signal; on the contrary,
“Output-E” driven by “CLK-E” presents numerous errors.
Based on these simulation results, we find that the MFF requires
minimum Dtotal =∼ 1.8 ns between the input and output sig-
nals, which can be also calculated by (14). The maximum
operating frequency is potentially limited to ∼500 MHz to
ensure the correct logic operations. As the logic setup delay
Dsetup (∼100 ps) and sensing delay Dread (∼100 ps) are much
lower than Dwrite, efforts should be focused on the methods to
reduce Dwrite to relax this limitation of the MFF. As shown in
Fig. 7, an operating frequency of ∼1 GHz can be achieved for
this MFF but at the cost of a larger silicon area, i.e.,
Dtotal = Dwrite + Dsetup + Dread. (14)
V. CONCLUSION AND DISCUSSION
We have presented the first compact model of CoFeB/MgO/
CoFeB PMA MTJs switched by STTs. It can be very useful
for spin-based logic and memory design, which are emerging
in many areas such as aerospace and automotive applications.
A number of physical models and realistic material parame-
ters have been integrated into the model to achieve excellent
agreement with experimental measurements. Furthermore, im-
plementation using Verilog-A allows this model to be easily
extended to other PMA MTJ structures. Single-cell simulations
were first performed to validate its static, dynamic, stochastic
behavior. Based on the 65-nm node, hybrid MTJ/CMOS cir-
cuits were simulated to demonstrate its usefulness for circuit
performance analysis and optimization. This model can be also
extended to simulate some complex spintronic systems such
as racetrack memory devices [43]–[45], where PMA MTJs
constitute the read and write heads.
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Yue Zhang was born in China in 1986. He received
the B.S. degree in optoelectronics from Huazhong
University of Science and Technology, Wuhan,
China, in 2009 and the M.S. degree in electronic
systems for integrated sensors from the University of
Paris-Sud 11, Orsay, France, in 2011.
He is currently with the Institut d’Electronique
Fondamentale, University of Paris-Sud 11, work-
ing on a research project on electrical modeling of
nanospintronic components and evaluation of new
integrated architectures of integrated circuits.

8. 826 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 3, MARCH 2012
Weisheng Zhao (M’06) received the M.Sc. degree
in electrical engineering from École Nationale
Supérieure d’Électronique, d’Électrotechnique,
d’Informatique, d’Hydraulique et des Télé-
communications (ENSEEIHT), Toulouse, France,
in 2004 and the Ph.D. degree in physics from the
University of Paris-Sud 11, Orsay, France, in 2007.
From 2004 to 2008, he investigated spintronic-
device-based logic circuits and designed a prototype
for hybrid spintronic/CMOS (90 nm) chip in coop-
eration with STMicroelectronics and French Atomic
Agency (CEA). From 2008 to 2009, he was with the embedded computing
laboratory at CEA, and his work included the functional model development
and neuromorphic computing architecture design based on nanodevices. In
2009, he joined the CNRS as a Tenured Research Scientist, and his interest
includes the hybrid integration of nanodevices with CMOS circuit and new
nonvolatile memory (40 nm and below) such as MRAM IC design. He has
authored more than 40 scientific papers. He is the holder of four international
patents.
Yahya Lakys received the B.S. degree from the
Lebanese University, Beirut, Lebanon, in 2003, the
M.S. degree from the University of Rennes, Rennes,
France, in 2004, and the Ph.D. degree from the
University of Bordeaux, Bordeaux, France, in 2009.
He is currently a Postdoctoral Researcher with
the Institut d’Electronique Fondamentale, University
of Paris-Sud 11, Orsay, France. He is interested
in the design of integrated circuits based on new
“spintronics” nanocomponents and semiconductor.
He proposed new designs of building blocks for
reconfigurable logic circuits and nonvolatile magnetic RAM.
Jacques-Olivier Klein (M’90) was born in France
in 1967. He received the Ph.D. degree and the Habil-
itation in electronic engineering from the University
of Paris-Sud 11, Orsay, France, in 1995 and 2009,
respectively.
He is currently a Professor with the Institut
d’Electronique Fondamentale, University of Paris-
Sud 11, where he leads the nanocomputing group
that focuses on architecture of circuits and systems
based on emerging components in the field of nano-
magnetism and bioinspired nanonoelectronics. He
teaches embedded system design in the Institut Universitaire de Technologie
de Cachan. He is the author of 70 technical papers, including seven invited
communications.
Prof. Klein served on the program committee of conferences such as Design
& Technology of Integrated Systems in nanoscale era (DTIS) and Great
Lakes Symposium on VLSI (GLSVLSI). He served as a Reviewer for the
International Journal of Reconfigurable Computing, IEEE TRANSACTIONS
ON MAGNETICS, Solid State Electronics, and conferences like International
Symposium on Circuits and Systems (ISCAS). He coordinated the project
ANR-PANINI fund by the French Research Agency. He leads, with C. Maneux
(IMS), the topic “Emerging Technologies” of the research group dedicated to
system-on-chip and system-in-package (CNRS GDR SoC-SiP).
Joo-Von Kim (M’06) received the B.Sc.(Hons.)
degree in physics and the Ph.D. degree from the
University of Western Australia, Perth, Australia, in
1998 and 2003, respectively.
He is currently a CNRS Research Associate with
the Institut d’Electronique Fondamentale, University
of Paris-Sud 11, Orsay, France, where he pursues his
research interests in theoretical magnetism and spin-
dependent transport. He has coauthored more than 50
research papers. He is the holder of three patents.
Dafiné Ravelosona received the Ph.D. degree in
solid-state physics from the National Centre for Mi-
croelectronics (CNM), Madrid, Spain, in 1995.
He was a Postdoctoral Fellow with CNM. In 1998,
he became a permanent research member of CNRS
at the University of Paris-Sud 11, Orsay, France.
He is an experimentalist physicist and is currently
the Head of the “Nanospintronics” Group, Institut
d’Electronique Fondamentale, University of Paris-
Sud 11. From 2004 to 2005, he was an Invited
Scientist at the Research Center of Hitachi Global
Storage Technology, San José, CA. He has more than 15 years of experience
on magnetic thin-film growth, ion irradiation of magnetic films, nanodevice
development, magnetotransport phenomena, and nanomagnetism. His work has
mainly focused on transport phenomena in nanostructures with perpendicular
anisotropy for applications to logic and solid-state memory devices. Since
2005, he has participated to the demonstration of several breakthroughs in the
field of magnetization switching under spin-polarized current in films with
perpendicular anisotropy. He is currently the Coordinator of a collaborative
FP7 STREP European project in charge of developing a domain-wall-based
memory prototype integrated into CMOS technology. He also coordinates a
USA–France “Materials World Network” project on spintronic devices.
Dr. Ravelosona the recipient of the 2010 Innovation Prize at the University
of Paris-Sud 11.
Claude Chappert (M’09) received the “Docteur
d’Etat” Diploma from the University of Paris-Sud
11, Orsay, France, in 1985.
He is currently a Research Director at CNRS, with
over 30 years of experience in research on magnetic
ultrathin films and nanostructures and their applica-
tions to ultrahigh density recording. He spent one
year as a Visiting Scientist with the IBM Almaden
Research Center, San José, CA. He then started
a research group on “Nanospintronics” within the
Institut d’Electronique Fondamentale, University of
Paris-Sud 11 and CNRS (www.ief.u-psud.fr). From 2005 to 2011, he has
been in charge of the Spin Electronics Division, “Centre de Competences
en Nanosciences,” Ile-de-France. In January 2010, he has taken the position
of Director of the Institut d’Electronique Fondamentale. He has coauthored
more than 250 papers. He is the holder of six patents. His major interests
have been on perpendicular interface anisotropy materials, oscillating interlayer
interaction, magnetization reversal in ultrathin films and dot arrays, ion irradia-
tion patterning of magnetic materials, and now spin-transfer-induced gigahertz
magnetization dynamics of MRAM cells and magnetic logic circuits.
Dr. Chappert was the recipient of the Silver Medal of CNRS in 2000 for his
research achievements.