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VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

•
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A
Amal Khailtash

Describes the VHDL arithmetic packages and functions available. It also shows the new VHDL-200x packages and functions.

TechnologieDesign
1 von 47
The power of partnership. The triumph of technology. VHDL Packages Coding Styles for Arithmetic Operations VHDL-200x Additions
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Introduction ,[object Object],[object Object],[object Object],[object Object]
VHDL Libraries and Packages ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
STD.Standard ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
STD.Textio ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.std_logic_1164 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.numeric_bit ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.numeric_std ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.math_real (not synthesizable*) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.math_complex (not synthesizable) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE(synopsys).std_logic_arith ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE(synopsys).std_logic_signed ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE(synopsys).std_logic_unsigned ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE(synopsys).std_logic_textio ,[object Object],[object Object],[object Object]
The two camps (IEEE vs Synopsys) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The two camps (cont.) ,[object Object],[object Object],[object Object],[object Object]
The two camps (cont.) ,[object Object],[object Object],[object Object]
Either Camp ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],integer bit_vector std_logic_vector 22 s 713 ms 31 s 369 ms 32 s 756 ms
Coding Arithmetic Operations in VHDL
Arithmetic Operations ,[object Object]
Type Conversions/Resize
Additions/Subtraction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Additions/Subtraction (cont.) ,[object Object],signal a : signed(15 downto 0) signal b : signed(15 downto 0) signal c : signed(16 downto 0) p_Add_With_Carry: process( clock ) begin if rising_edge(clock) then c <= resize(a, c'length) + resize(b, c'length); end if; end process p_Add_With_Carry; signal a : signed(15 downto 0) signal b : signed(15 downto 0) signal c : signed(16 downto 0) p_Add_With_Carry: process( clock ) begin if rising_edge(clock) then c <= conv_signed(a, c'length) + conv_signed(b, c'length); end if; end process p_Add_With_Carry; numeric_std std_logic_arith c a b
Multiplication ,[object Object],[object Object],[object Object],[object Object],[object Object]
Multiplication (cont.) ,[object Object],constant DEPTH : positive := 3; signal a : signed(15 downto 0) signal b : signed(10 downto 0) signal c : signed(a'length+b'length-1 downto 0); type Pipe_Type is array(0 to DEPTH-1) of signed(c'range); signal pipe : Pipe_Type; p_Mult_pipe: process( clock ) begin if rising_edge(clock) then pipe <= signed(a * b) & pipe(0 to pipe'length-2); end if; end process p_Mult_pipe; c <= pipe(pipe'length-1); c a b
Divide (Remainder/Modulus) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Square Root ,[object Object],[object Object],[object Object],[object Object]
Trigonometric Functions ,[object Object],[object Object],[object Object],[object Object]
VHDL-200x Additions
http://www.eda.org/vhdl-200x/vhdl-200x-ft
STD.Standard (additions) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
STD.Textio (additions) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.std_logic_1164 (additions) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.numeric_bit_unsigned (new) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.numeric_std (additions) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.numeric_std_unsigned (new) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.fixed_pkg (new) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.float_pkg (new) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
IEEE.float_alg_pkg (new) ,[object Object],[object Object],[object Object]
Cores, cores, cores...
Reusable/Generic Code ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reusable/Generic Code (cont) ,[object Object],[object Object],[object Object],[object Object],[object Object],Package config_pkg is type TARGET_TYPE is (FPGA, ASIC); type VENDOR_TYPE is (XILINX, IBM, LSI, ...); type XILINX_PARTS is (Virtex2, Virtex4, ...); type IBM_PROCESSES is (G4, G5, ...); type LSI_PROCESSES is (Flex, Gflex, ...); End Package config_pkg; Package hill_config_pkg is -- Chip specific parameters constant DEVICE_ID : ... = ...; constant HAS_CLOCK_ERROR : boolean := TRUE; constant VITERBI_TRACE_BACK : positive := ...; constant HAS_FLASH : boolean := TRUE; constant FLASH_DATA_SIZE : positive := 16; End Package hill_config_pkg;
Reusable/Generic Code (cont) ,[object Object],[object Object],[object Object],[object Object],[object Object],a <= b * c; d <= a + d; g_XILINX_V2: if ( TARGET=XILINX_V2 ) generate u_div: generic_divider generic map (...) port map (...); end generate; g_IBM_G5: if ( TARGET=IBM_G5 ) generate u_div: DW_DIV port map (....); end generate;
Reusable/Generic Code (cont) ,[object Object],[object Object],[object Object],Entity memory is generic (TARGET : TARGET_TYPE ); ... begin g_Xilinx_V2: if ( TARGET=X_V2 ) generate u_mem : block_memory_RW generic map (...) port map (...); end generate; g_LSI_GFlex: if ( TARGET=LSI_GFlex ) generate u_mem : m1r2d_xyz port map (...); end generate; End Entity memory;
Conclusion
Conclusion ,[object Object],[object Object],[object Object],[object Object]

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