The document describes two FPGA projects using HDL: 1. Salt and pepper noise removal from images using a median filter optimized for FPGA hardware. The filter reduces comparison times by 40% over traditional algorithms. 2. Generation of pulse-width modulation (PWM) signals using a counter and comparator on an FPGA. A 25% duty cycle PWM signal is successfully generated to control devices. The document provides details on the hardware design, VHDL code modules, and testing of both projects. Real-time filtering of 1Kx1K images and MATLAB simulation of PWM generation are demonstrated. Guidelines for efficient HDL coding suited for FPGA implementation are also listed.

1. 1
FPGA APPLICATIONS USING HDL
Report by,
Sankarshan D PES1201700495
Santhosh S PES1201700501
Nikhilesh M PES1201700538
Under the guidance of,
Dr. Venugopal N EEE Department
Prof. Sumanth ECE Department

2. 2
Introduction
Hardwaredescription language
(HDL) is a specialized computer
language used to program
electronic and digital logic circuits.
The structure, operation and design
of the circuits are programmable
using HDL. HDL includes a textual
description consisting of operators,
expressions, statements, inputs and
outputs. Instead of generating a
computer executable file, the HDL
compilers provide a gate map. The
gate map obtained is then
downloaded to the programming
device to check the operations of
the desired circuit. The language
helps to describeany digital circuit
in the formof structural,
behaviouraland gate level and it is
found to be an excellent
programming languagefor FPGAs
and CPLDs.
Structurallevel logic is used when
knowledgeregarding the equations
is present. Behavioral level logic is
used when knowledgeregarding the
process is known. Gate level logic is
used when the circuit is available.
Differencebetween FPGA and
microcontrollers
Microcontrollers
Custom built minicomputers in an
IC. Consumeless power. Can’t be re
programmed. Built for specific
functionality Cheap and less flexible.
FPGA
Comprised of logic blocks that can
be rewired. They consumemore
power and can be reprogrammed.
They are costly but more flexible.
Very VHDL projectshould comprise
of two basic modules,
1) Design module
2) Test bench
Design module comprises of the
entity and the architecture of the
entity. The entity declares the ports
and the architecture determines the
function of the ports and the
module.
Test bench module includes the
module to be tested, there are no
input or output ports for test bench
Functional
Specification
HDL
Synthesis Place & Route
Download&
Verifythe circuit

3. 3
entity, reduces the functional
verification of design module.
Approach
 Initialize all input
 Set the clk signal
 Send test vectors
 Specify when to end the
simulation
Project 1.
Salt & Pepper noise removal
using Sort optimization
algorithm of median filtering
based on FPGA – IEEE PAPER.
(Lu, Dai, Jiang, & Li, 2010)
In the name, salt refers to the white
noises and pepper refers to the
black noises. In a grey scale image,
each pixel comprises of 8 bits,
whereis 0 black and 256 is white.
Consider the following diagram
below
10 256 10
15 0 15
10 10 10
The figure represents a small 3x3
pixel where256,0 arethe noises. By
considering the median in each row
we can remove256, 0 back to their
rightful values ( 10 and 15
respectfully ).
We shall be doing it for a large scale
of 256x256 pixel image.
Designing an optimized median
sort filter.
The traditional sorting algorithm of
median
filtering is optimized according to
the hardwarestructure
features of FPGA. FPGA is used to
acquire the data
parallelly for comparing the data of
the samecolumn in the
median filtering window. Comparing
results shared by
adjacent filter window are saved
temporarily to match the
new round of median filtering by
using FPGA internal
resources. This method can reduce
the comparing times
from current 21 down to 13, and
improvethe algorithm
efficiency nearly 40%.The
experimental results provethat
the optimized algorithm can filter a
1K×1K gray-levelimage
in about 20ms, which ensurethe
proposed algorithm can be
applied in the real-time image
median filtering system.
Test
Bench
Design
Module

4. 4
The workflow of the median
filtering module is that: firstly, three
lines of data are wrote into the
internal FIFO of FPGA, and when the
third FIFO turn into half full state,
the median filtering system begin to
work. The data in the 3 FIFO willbe
sent to the ordering comparator
ordinally for data ordering, and the
results will be send to next different
comparators. Beforethe second
comparing, the data need 2 circle
delay to distinguish the circle order
of input data by two D flip-flops.
The second comparing results will
be sent tothe final median
comparator to get the final result.
Designing ordering comparator
The figure above shows the
ordering comparator. WhereD
refers to the D flipflop and PE refers
to a normal comparator. A B C are
the inputs. After the firstclock
cycle, the 3 inputs enter the
ordering comparator. Inputs A and
B are compared in the firstPE
comparator which we have called
U1 in the file. C is fed to a D flip flop
which we refer to U2. After the first
clock cycle we get MAX (s1) , MIN(
s2 ) and C respectively. Next the 3
outputs go through the D ( U3) F/F
(MAX goes through this), MIN& C
go through PE ( U4 ). The outputs
,MAX (s4) , MAX(s5) and MIN(s6)
are obtained at the 2nd
clock cycle.
Similarly after the 3rd
clock cycle we
get outputs MAX MID and MINfrom
PE ( U5 ) and D F/F (U6).
To design this ordering comparator
we need to design 2 files first, 1 D
F/F and 1 PE comparator and then
finally port map these two multiple
time with the help of signals.
Figure 1Hardware structure of median filtering after arranging in ascending order

5. 5
Designing D F/F
Design Module
Inputs ared, clk, reset.
Output is q.
Test bench
Designing PE comparator
Design Module
Test bench

6. 6
Simulation
Port mapping D F/F and PE
comparator
Design Module
Test bench

7. 7
Simulation
Designing MIN comparator module
This module requires, PE min
comparator ( U1,U3 ) and D F/F
(U2). The output will be obtained
after 3 clock cycles.
Designing PE min module
Test Bench
Simulation

8. 8
Portmapping for Min comparator
module
Design Module
Test Bench
Simulation
Designing Medcomparator module
This module requires PE comparator
(U1 & U4 ) , D F/F ( U2 , U3) and PE
Min comparator (U5). The output is
obtained after 4 clock cycles.
Since all the modules have been
previously designed, wecan directly
go for port mapping.
Portmapping the modules
Test bench

9. 9
Simulation
Designing Max comparator
module
The above figure represents max
comparator. The max comparator
comprises of 3 inputs and 1 output.
Internally 1 D F/F ( U1) , 2 PE max
comparators ( U2,U3). Theoutput
max number is obtained after 3
clock cycles.
Designing PE Max comparator
Design Module
Test bench
Simulation
Designing the final port map for
the filter
Refer to figure 1.
Design Module

10. 10
Test bench
Simulation
Designing Input mechanism
Each pixel from the image is taken
in from the data in port. FIFO is a
253 bit register. 3 outputs are taken
from this input mechanism and sent
to the filter. That is D3, D2 and Data
out. The D F/F can be considered as
3x3 pixel matrix. Which is whatwe
require as discussed earlier.
Design Module for moving window.
Designing port map for the
whole project
Now a portmap for the whole
projectmust be designed wherethe
moving window ( U1) and the
Median Filter ( U2 ) are linked by
signals S1,S2,S3 ( o/p of U1 and i/p
to U2)

11. 11
Design module for portmapping
System generator interfacing
with Matlab
Now an interface mustbe made to
link the HDL code with the input
and to obtain the o/p. We mustalso
dump the code onto the FPGA.
The general steps are
Step 1: Open Systemgenerator and
configurematlab 2012 with it.
Step2: Open systemgenerator file,
Matlab will open
Step3: Click on simulink icon, then
click on Xilinx library and drag
systemgenerator icon followed by
blackboxonto simulink workspace
Step4: Xilinx will open now, Add
subfiles of Xilinx project
Step5: Edit Workspaceas per
requirement
Step6: Make connections from
FPGA to laptop and simulate

12. 12
Matlab File
Input
Output
Itcan be observed that the salt and
pepper noises are removed from
the input image. Hence the image
filtering has been successfully
implemented.

13. 13
Project 2
PWM Generator
A Pulse Width Modulation (PWM)
Signal is a method for generating an
analog signalusing a digital source.
A PWMsignal consists of two main
components that define its
behavior: a duty cycle and a
frequency. The duty cycle describes
the amountof time the signalis in a
high (on) state as a percentage of
the total time of it takes to
complete one cycle. The frequency
determines how fast the PWM
completes a cycle (i.e. 1000 Hz
would be 1000 cycles per second),
and therefore how fastit switches
between high and low states. By
cycling a digital signaloff and on at
a fast enough rate, and with a
certain duty cycle, the output will
appear to behave like a constant
voltage analog signal when
providing power to devices.
PWMsignals are used for a wide
variety of control applications. Their
main use is for controlling DC
motors but it can also be used to
control valves, pumps, hydraulics,
and other mechanical parts. The
frequency that the PWMsignal
needs to be set at will be dependent
on the application and the response
time of the systemthat is being
powered. Below are a few
applications and sometypical
minimum PWM frequencies
required:
 Heating elements or systems
with slow responsetimes: 10-
100 Hz or higher
 DC electric motors: 5-10 kHz
or higher
 Power supplies or audio
amplifiers: 20-200 kHz or
higher

14. 14
Generating PWM
0 1 2 3 4 5 6 7
PWM’s can be generated with the
help of clock signals.For every
positiveedge of the clock signal
with the help of a counter, we
can begin the counting.
To control the duty cycle we’ll
need a comparatorwhose output
values are either one and 0. For a
25 percent duty cycle we can set
the output to be 1 from 0 count
to count 2 and 0 from 2 to 7. This
is the way we can generate PWM
waves.
Hardware Structure
For PWM generation we need one
counter (U1) that is related to clock
and one comparator ( U2 ) that is
linked to the counter through a
signal S1.
Designing the counter
Design Module
Test bench
Counter
Comparator
CLK Reset
Duty Cycle
Count PWM

15. 15
Simulation
From the abovefigure we can see
that for every clock cycle the
counter counts,after the counter
reaches ”111” the counter goes
back to 0.
Designing comparator
The role of the comparator here is
to dictate the duty cycle. Based on
the input given by the user, the
comparator takes in this value and
compares the counter output.
Based on this comparison the
counter gives output of either one
or zero, hence generating PWM’s.
Designmodule
The comparator has one output i.e.
the PWMand 2 inputs reset and
counter output.

16. 16
Test bench
Simulation
Creating port map & final
module
The port map comprises of
one counter(U1),one
comparator(U2),clk, reset
and pwm output.
Design module
Test bench

17. 17
Simulation
MATLAB MODEL

18. 18
Output
25 percent duty cycle pwm has
been generated by giving data in
as 2.

19. 19
RTL Rules for coding
RTL rule no 1 : always give priority for
reset pin.
RTL rule no 2: always use active high reset
pin. – In order to avoid an extra inverter.
RTL rule no 3 : Use only priority variables
in the sensitivity list, avoid inputs.
RTL rule no 4 : Always use if else
statement that creates mux on hardware.
RTL rule no 5: For many conditions and
many outcomes avoid if else if and use
case statement.
RTL rule no 6 : Variable’s are cache
memory and don’t create connections
use := while assigning , but signals create a
dedicated wires in the hardware.
Difference in if statements
Simple if : Creates an inverter.
If + else statement : Creates a
mux.
If + elsif : Creates encoder.