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Ripes tracking computer architecture throught visual and interactive simulators

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RISC-V International
RISC-V International

Ripes is a visual processor simulator and assembly editor for RISC-V that was created to teach computer architecture concepts. It allows interactive simulation and visualization of different processor models, including single-cycle, pipelined, and models with caching. Ripes uses the Visual Simulation of Register Transfer Logic (VSRTL) framework, which generates circuit visualizations from processor descriptions. This allows Ripes to simulate various RISC-V processors and visualize their data paths during execution. Ripes has been expanded over time to support cache simulation and integration with C toolchains.

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Information Classification: General December 8-10 | Virtual Event
Information Classification: General December 8-10 | Virtual Event Ripes Teaching Computer Architecture Through Visual and Interactive Simulators #RISCVSUMMIT Morten Borup Petersen
Information Classification: General About me ● 2015 - 2019 : B.Sc. EE @ DTU - Technical University of Denmark ● Spring 2019 : Intern embedded software engineer @ ARM Cambridge ● 2019 - now : M.Sc. CS @ EPFL - École polytechnique fédérale de Lausanne Agenda ● Educational simulators and motivation for Ripes ● Demo 1: Ripes overview, usage & processor models ● Ripes - What’s inside? VSRTL ● Demo 2: C Integration & cache simulation
Information Classification: General Undergraduate course coverage: 1. ISAs & assembly level programming 2. Microarchitecture ● Single-cycle, pipelined ● Hazards, forwarding ● Memory system Teaching computer architecture Why not have a single application to experiment with all of the core concepts while unifying simulator capabilities? Simulator capabilities*: ● Online (Venus, Vulcan, ...) ⇨ Zero setup ● Functional (Spike, QEMU, ...) ⇨ Efficiently execute binaries ● Visual (WebRISC-V, ...) ⇨ Investigate datapath during execution
Information Classification: General In books...
Information Classification: General What makes a good educational simulator? 1. Little/no setup 2. Eliminate sources of frustration 3. Make it visual 4. Make it capable The simulator should make you want to explore RISC-V! Simulator requirements First point of contact - make it enjoyable!
Information Classification: General Ripes “A visual processor simulator and assembly editor for the RISC-V ISA” ISA & Implementations ● Simulates various in-order architectures ● Implements the RV32(I/M) instruction set Editor & Interaction ● Integrated assembly editor ● Interactive memory viewer ● Animated datapath High(er) level concepts ● Cache simulation ● C toolchain integration
Information Classification: General Ripes has been used at ... And others...
Information Classification: General Ripes - Timeline 2017 2018 2019 2020 Initial commit (ISA simulator) 5-stage pipeline visualization, built-in assembler & editor VSRTL initial commit (circuit visualization framework) Simulator & visualization overhaul (VSRTL) ⇨ multiple processor models Cache simulation, C toolchain integration 2021
Information Classification: General Ripes - Editor Simulator controls Stage contents Source code Disassembled executable
Information Classification: General Ripes - Processor Animated datapath Register view Instruction view
Information Classification: General Ripes - Processor
Information Classification: General Ripes - Memory Scrollable memory view Cache geometry configuration Cache policy configuration Cache access statistics Cache animation
Information Classification: General Demo 1: Ripes overview, usage & processor models
Information Classification: General Ripes v1.0: Some lessons learned 1. Circuit description: Need a correct and versatile simulation framework ● Allows for design modification ● Multiple processor designs 2. Graphics: Circuit visualization should be generated from circuit description ● Allows for interaction with circuit (highlighting wires, show/hide components etc.) 3. Simulation: Need ability to step back and forward in time ● Allows for investigating interesting pipeline situations What’s Inside? Conclusion: 1. Needed a framework to provide all of the above 2. Notably, these requirements may be fully decoupled from the notion of “simulating a processor”
Information Classification: General Visual Simulation of Register Transfer Logic A framework for describing cycle-accurate simulators which provides an automatically generated visualization of the simulated circuit What’s Inside? - VSRTL
Information Classification: General VSRTL Graphics VSRTL Components VSRTL Core What’s inside? - VSRTL VSRTL Architecture Circuit description ● (Simple) HDL embedded in C++ ● Simulator, circuit primitives (ports, entities, wires, …) ● VSRTL Standard library: logic gates, registers, multiplexers, … ● Component widgets ● Reflect simulator state changes ● Visualization “place and route” Ripes processor models
Information Classification: General VSRTL Graphics VSRTL Components VSRTL Core What’s inside? - VSRTL VSRTL Architecture … *: VSRTL Core was/is an interesting exercise but we should be able to visualize circuits generated through commonly used HDLs Future: ● Add FIRRTL parser/simulator backend ⇨ Chisel will have a simulator with visualization VSRTL Graphics decoupled from VSRTL Core ● Why? No one needs another HDL* ● VSRTL Graphics expects some simulator backend adhering to its interface
Information Classification: General ● Ships with 4 processor models - Single cycle - 5 stage - 5 stage w/o hazard detection - 5 stage w/o forwarding or hazard detection ● Different views for each processor model ● Interactive ● Reversible simulation Ripes v2 VSRTL Integration
Information Classification: General ● Ships with 4 processor models ● Different views for each processor model - Standard - Extended + control, forwarding, hazard units + port widths ● Interactive ● Reversible simulation Ripes v2 VSRTL Integration
Information Classification: General ● Ships with 4 processor models ● Different views for each processor model ● Interactive - Port values (w/ radix selection) - Wire highlighting ● Reversible simulation Ripes v2 VSRTL Integration
Information Classification: General Demo 2: C Integration & cache simulation
Information Classification: General Going further... Low-hanging fruit Beyond the basics VSRTL Branch prediction I/O Out-of-order Processors ALU ALU FPU LSU IM Sched RF ?
Information Classification: General December 8-10 | Virtual Event Ripes on GitHub: github.com/mortbopet/Ripes morten_bp@live.dk linkedin.com/in/mortbopet/
Information Classification: General December 8-10 | Virtual Event Thank you for joining us. Contribute to the RISC-V conversation on social! #RISCVSUMMIT @risc_v

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Ripes tracking computer architecture throught visual and interactive simulators

  • 2. Information Classification: General December 8-10 | Virtual Event Ripes Teaching Computer Architecture Through Visual and Interactive Simulators #RISCVSUMMIT Morten Borup Petersen
  • 3. Information Classification: General About me ● 2015 - 2019 : B.Sc. EE @ DTU - Technical University of Denmark ● Spring 2019 : Intern embedded software engineer @ ARM Cambridge ● 2019 - now : M.Sc. CS @ EPFL - École polytechnique fédérale de Lausanne Agenda ● Educational simulators and motivation for Ripes ● Demo 1: Ripes overview, usage & processor models ● Ripes - What’s inside? VSRTL ● Demo 2: C Integration & cache simulation
  • 4. Information Classification: General Undergraduate course coverage: 1. ISAs & assembly level programming 2. Microarchitecture ● Single-cycle, pipelined ● Hazards, forwarding ● Memory system Teaching computer architecture Why not have a single application to experiment with all of the core concepts while unifying simulator capabilities? Simulator capabilities*: ● Online (Venus, Vulcan, ...) ⇨ Zero setup ● Functional (Spike, QEMU, ...) ⇨ Efficiently execute binaries ● Visual (WebRISC-V, ...) ⇨ Investigate datapath during execution
  • 6. Information Classification: General What makes a good educational simulator? 1. Little/no setup 2. Eliminate sources of frustration 3. Make it visual 4. Make it capable The simulator should make you want to explore RISC-V! Simulator requirements First point of contact - make it enjoyable!
  • 7. Information Classification: General Ripes “A visual processor simulator and assembly editor for the RISC-V ISA” ISA & Implementations ● Simulates various in-order architectures ● Implements the RV32(I/M) instruction set Editor & Interaction ● Integrated assembly editor ● Interactive memory viewer ● Animated datapath High(er) level concepts ● Cache simulation ● C toolchain integration
  • 8. Information Classification: General Ripes has been used at ... And others...
  • 9. Information Classification: General Ripes - Timeline 2017 2018 2019 2020 Initial commit (ISA simulator) 5-stage pipeline visualization, built-in assembler & editor VSRTL initial commit (circuit visualization framework) Simulator & visualization overhaul (VSRTL) ⇨ multiple processor models Cache simulation, C toolchain integration 2021
  • 10. Information Classification: General Ripes - Editor Simulator controls Stage contents Source code Disassembled executable
  • 11. Information Classification: General Ripes - Processor Animated datapath Register view Instruction view
  • 13. Information Classification: General Ripes - Memory Scrollable memory view Cache geometry configuration Cache policy configuration Cache access statistics Cache animation
  • 14. Information Classification: General Demo 1: Ripes overview, usage & processor models
  • 15. Information Classification: General Ripes v1.0: Some lessons learned 1. Circuit description: Need a correct and versatile simulation framework ● Allows for design modification ● Multiple processor designs 2. Graphics: Circuit visualization should be generated from circuit description ● Allows for interaction with circuit (highlighting wires, show/hide components etc.) 3. Simulation: Need ability to step back and forward in time ● Allows for investigating interesting pipeline situations What’s Inside? Conclusion: 1. Needed a framework to provide all of the above 2. Notably, these requirements may be fully decoupled from the notion of “simulating a processor”
  • 16. Information Classification: General Visual Simulation of Register Transfer Logic A framework for describing cycle-accurate simulators which provides an automatically generated visualization of the simulated circuit What’s Inside? - VSRTL
  • 17. Information Classification: General VSRTL Graphics VSRTL Components VSRTL Core What’s inside? - VSRTL VSRTL Architecture Circuit description ● (Simple) HDL embedded in C++ ● Simulator, circuit primitives (ports, entities, wires, …) ● VSRTL Standard library: logic gates, registers, multiplexers, … ● Component widgets ● Reflect simulator state changes ● Visualization “place and route” Ripes processor models
  • 18. Information Classification: General VSRTL Graphics VSRTL Components VSRTL Core What’s inside? - VSRTL VSRTL Architecture … *: VSRTL Core was/is an interesting exercise but we should be able to visualize circuits generated through commonly used HDLs Future: ● Add FIRRTL parser/simulator backend ⇨ Chisel will have a simulator with visualization VSRTL Graphics decoupled from VSRTL Core ● Why? No one needs another HDL* ● VSRTL Graphics expects some simulator backend adhering to its interface
  • 19. Information Classification: General ● Ships with 4 processor models - Single cycle - 5 stage - 5 stage w/o hazard detection - 5 stage w/o forwarding or hazard detection ● Different views for each processor model ● Interactive ● Reversible simulation Ripes v2 VSRTL Integration
  • 20. Information Classification: General ● Ships with 4 processor models ● Different views for each processor model - Standard - Extended + control, forwarding, hazard units + port widths ● Interactive ● Reversible simulation Ripes v2 VSRTL Integration
  • 21. Information Classification: General ● Ships with 4 processor models ● Different views for each processor model ● Interactive - Port values (w/ radix selection) - Wire highlighting ● Reversible simulation Ripes v2 VSRTL Integration
  • 22. Information Classification: General Demo 2: C Integration & cache simulation
  • 23. Information Classification: General Going further... Low-hanging fruit Beyond the basics VSRTL Branch prediction I/O Out-of-order Processors ALU ALU FPU LSU IM Sched RF ?
  • 24. Information Classification: General December 8-10 | Virtual Event Ripes on GitHub: github.com/mortbopet/Ripes morten_bp@live.dk linkedin.com/in/mortbopet/
  • 25. Information Classification: General December 8-10 | Virtual Event Thank you for joining us. Contribute to the RISC-V conversation on social! #RISCVSUMMIT @risc_v