Sequential circuits

UNIT III
Sequential Circuits
By Dr. Dhobale J V
Associate Professor
School of Engineering & Technology
RNB Global University, Bikaner
RNB Global University, Bikaner. 1Course Code - 19004000

Objectives
 Various types of flip-flops and their
conversions.
 Registers, Timing issues, Counters-
Synchronous, Asynchronous.
 Finite state machines.
 Design of Synchronous sequential circuits.
 Design of Asynchronous circuits, cycles,
races and hazards.
2RNB Global University, Bikaner.Course Code - 19004000

Flip-flops
 Computers and calculators use Flip-flop for
their memory. A combination of number of flip
flops will produce some amount of memory.
 Flip flop is formed using logic gates, which are
in turn made of transistors.
 Flip flop are basic building blocks in the
memory of electronic devices.
 Each flip flop can store one bit of data.
 These are also called as sequential logic
circuits.

Flip-flops
 Flip – flops have two stable states and hence
they are bistable multivibrators.
 The two stable states are High (logic 1) and
Low (logic 0).
 The term flip – flop is used as they can switch
between the states under the influence of a
control signal (clock or enable) i.e. they can
‘flip’ to one state and ‘flop’ back to other state.
 Flip – flops are a binary storage device
because they can store binary data (0 or 1).

Flip-flops
 Flip – flops are edge sensitive or edge
triggered devices i.e. they are sensitive to the
transition rather than the duration or width of
the clock signal.
 They are also known as signal change
sensitive devices which mean that the change
in the level of clock signal will bring change in
output of the flip flop.
 Flip flops are also used to control the digital
circuit’s functionality. They can change the
operation of a digital circuit depending on the
state. 5RNB Global University, Bikaner.Course Code - 19004000

Flip-flops

Flip-flops
 Where we use flip flops?
 Registers: As the flip flops have two stable
states, we use them in memory elements like
registers, for data storage. Generally we use
registers in electronic devices like computers.
 Counters: The groups of interconnected flip
flops are uses as counters, to count the
increment or decrement of an event
occurrence.

Flip-flops
 Where we use flip flops?
 Frequency division: Flip flops are used as
frequency division circuits, which divide the
input frequency to exactly to its half.
Frequency division circuits are used to
regularize the frequency of electronic circuits.
 Data transfer: We use shift registers (A
special-type of registers) to transfer the data
from one flip flop to another, which are
connected in a specific order.

Flip-flops
 SR flip-flop: Besides the CLOCK input, an SR
flip-flop has two inputs, labeled SET and
RESET.
 If the SET input is HIGH when the clock is
triggered, the Q output goes HIGH. If the
RESET input is HIGH when the clock is
triggered, the Q output goes LOW.

Flip-flops
 SR flip-flop:
 Note that in an SR flip-flop, the SET and
RESET inputs shouldn’t both be HIGH when
the clock is triggered.
 This is considered an invalid input condition,
and the resulting output isn’t predictable if this
condition occurs.

Flip-flops
 SR flip-flop:

Flip-flops
 D flip-flop:

Flip-flops
 D flip-flop:
 D flip flop is actually a slight modification of the
clocked SR flip-flop.
 From the figure you can see that the D input is
connected to the S input and the complement
of the D input is connected to the R input.
 The D input is passed on to the flip flop when
the value of CP is ‘1’. When CP is HIGH, the
flip flop moves to the SET state. If it is ‘0’, the
flip flop switches to the CLEAR state.

Flip-flops
 J-K flip-flop:

Flip-flops
 J-K flip-flop:
 A J-K flip flop can also be defined as a
modification of the S-R flip flop. The only
difference is that the intermediate state is
more refined and precise than that of a S-R
flip flop.
 The behavior of inputs J and K is same as the
S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for
CLEAR.

Flip-flops
 J-K flip-flop:
 When both the inputs J and K have a HIGH
state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to
Q=0 and for a value of Q = 0, it switches to
Q=1.
 The circuit includes two 3-input AND gates.
The output Q of the flip flop is returned back
as a feedback to the input of the AND along
with other inputs like K and clock pulse [CP].

Flip-flops
 J-K flip-flop:
 So, if the value of CP is ‘1’, the flip flop gets a
CLEAR signal and with the condition that the
value of Q was earlier 1.
 Similarly output Q’ of the flip flop is given as a
feedback to the input of the AND along with
other inputs like J and clock pulse [CP].
 So the output becomes SET when the value of
CP is 1 only if the value of Q’ was earlier 1.

Flip-flops
 J-K flip-flop:
 The output may be repeated in transitions
once they have been complimented for J=K=1
because of the feedback connection in the JK
flip-flop.
 This can be avoided by setting a time duration
lesser than the propagation delay through the
flip-flop. The restriction on the pulse width can
be eliminated with a master-slave or edge-
triggered construction.

Flip-flops
 T flip-flop:
 This is a much simpler version of the J-K flip
flop. Both the J and K inputs are connected
together and thus are also called a single input
J-K flip flop.
 When clock pulse is given to the flip flop, the
output begins to toggle. Here also the
restriction on the pulse width can be
eliminated with a master-slave or edge-
triggered construction.

Flip-flops
 T flip-flop:

Flip-flops - Conversions
 As flip-flops are bistable devices, these
sequential circuits are sometimes called
“latches” because their outputs are locked or
latched onto their input state until there is
another change to its input condition.
 The interconnection of digital logic gates to
produce a memory device leads to
applications such as switch debounce circuits,
shift registers and counters, etc.

 For the conversion of one flip flop to another,
a combinational circuit has to be designed
first.
 If a JK Flip Flop is required, the inputs are
given to the combinational circuit and the
output of the combinational circuit is
connected to the inputs of the actual flip flop.
 Thus, the output of the actual flip flop is the
output of the required flip flop.

 SR Flip Flop to JK Flip Flop:
 J and K will be given as external inputs to S
and R.
 As shown in the logic diagram below, S and R
will be the outputs of the combinational circuit.
 The truth tables for the flip flop conversion are
given below.
 The present state is represented by Qp and
Qp+1 is the next state to be obtained when the
J and K inputs are applied.

 For two inputs J and K, there will be eight
possible combinations.
 For each combination of J, K and Qp, the
corresponding Qp+1 states are found.
 Qp+1 simply suggests the future values to be
obtained by the JK flip flop after the value of
Qp.

 JK Flip Flop to SR Flip Flop:
 This will be the reverse process of the above
explained conversion.
 S and R will be the external inputs to J and K.
 As shown in the logic diagram below, J and K
will be the outputs of the combinational circuit.
 Thus, the values of J and K have to be
obtained in terms of S, R and Qp. The logic
diagram is shown below.

 A conversion table is to be written using S, R,
Qp, Qp+1, J and K.
 For two inputs, S and R, eight combinations
are made.
 For each combination, the corresponding
Qp+1 outputs are found

 SR Flip Flop to D Flip Flop:
 As shown in the figure, S and R are the actual
inputs of the flip flop and D is the external
input of the flip flop.
 The four combinations, the logic diagram,
conversion table, and the K-map for S and R
in terms of D and Qp are shown below.

 SR Flip Flop to D Flip Flop:

 D Flip Flop to SR Flip Flop:
 D is the actual input of the flip flop and S and
R are the external inputs.
 Eight possible combinations are achieved from
the external inputs S, R and Qp. But, since the
combination of S=1 and R=1 are invalid, the
values of Qp+1 and D are considered as “don’t
cares”.
 The logic diagram showing the conversion
from D to SR, and the K-map for D in terms of
S, R and Qp are shown below.

 D Flip Flop to SR Flip Flop:

 JK Flip Flop to T Flip Flop:
 J and K are the actual inputs of the flip flop
and T is taken as the external input for
conversion.
 Four combinations are produced with T and
Qp. J and K are expressed in terms of T and
Qp.
 The conversion table, K-maps, and the logic
diagram are given below.

 JK Flip Flop to T Flip Flop:

 JK Flip Flop to D Flip Flop:
 D is the external input and J and K are the
actual inputs of the flip flop. D and Qp make
four combinations. J and K are expressed in
terms of D and Qp.
 The four combination conversion table, the K-
maps for J and K in terms of D and Qp, and
the logic diagram showing the conversion from
JK to D are given below.

 JK Flip Flop to D Flip Flop:

 D Flip Flop to JK Flip Flop:
 In this conversion, D is the actual input to the
flip flop and J and K are the external inputs. J,
K and Qp make eight possible combinations,
as shown in the conversion table below. D is
expressed in terms of J, K and Qp.
 The conversion table, the K-map for D in terms
of J, K and Qp and the logic diagram showing
the conversion from D to JK are given in the
figure below.

 D Flip Flop to JK Flip Flop:

Registers
 A register is made out of multiple flip-flops
connected to each other used to store multiple
bits of data. If we have ‘n’ flip-flops, we can
store ‘n’ bits of data.

Registers
 The binary data in a register can be moved
within the register from one flip-flop to another.
The registers that allow such data transfers
are called as shift registers. There are four
mode of operations of a shift register.
1. Serial Input Serial Output
2. Serial Input Parallel Output
3. Parallel Input Serial Output
4. Parallel Input Parallel Output

Registers
1. Serial Input Serial Output:
 Let all the flip-flop be initially in the reset
condition i.e. Q3 = Q2= Q1 = Q0 = 0.
 If an entry of a four bit binary number 1 1 1 1 is
made into the register, this number should be
applied to Din bit with the LSB bit applied first.
 The D input of FF-3 i.e. D3 is connected to
serial data input Din. Output of FF-3 i.e. Q3 is
connected to the input of the next flip-flop i.e.
D2 and so on.

Registers
1. Serial Input Serial Output:

Registers
1. Serial Input Serial Output: Waveform

Registers

Registers
 Serial In Parallel Out (SIPO): For this kind of
register, data bits are entered serially in the
same manner as discussed in the last section.
 The difference is the way in which the data bits
are taken out of the register.
 Once the data are stored, each bit appears on
its respective output line, and all bits are
available simultaneously.

Registers
 Serial In Parallel Out (SIPO):
 In the table below, we can see how the four-bit
binary number 1001 is shifted to the Q outputs
of the register.

Registers
 Serial In Parallel Out (SIPO):

Registers
 Parallel In Serial Out (PISO): A four-bit parallel
in - serial out shift register is shown below.
 The circuit uses D flip-flops and NAND gates
for entering data (ie writing) to the register.

Registers
 Parallel In Serial Out (PISO):
 D0, D1, D2 and D3 are the parallel inputs,
where D0 is the most significant bit and D3 is
the least significant bit.

Registers
 Parallel In Serial Out (PISO): To write data in,
the mode control line is taken to LOW and the
data is clocked in.
 The data can be shifted when the mode
control line is HIGH as SHIFT is active high.
 The register performs right shift operation on
the application of a clock pulse, as shown in
the table below.

Registers
 Parallel In Serial Out (PISO):

Registers
 Parallel In Serial Out (PISO): To write data in,
the mode control line is taken to LOW and the
data is clocked in.
 The data can be shifted when the mode
control line is HIGH as SHIFT is active high.
 The register performs right shift operation on
the application of a clock pulse, as shown in
the table below.

Registers
 Parallel In Parallel Out (PIPO): For parallel in -
parallel out shift registers, all data bits appear
on the parallel outputs immediately following
the simultaneous entry of the data bits.
 The following circuit is a four-bit parallel in -
parallel out shift register constructed by D flip-
flops.

Registers
 Parallel In Parallel Out (PIPO):
 The D's are the parallel inputs and the Q's are
the parallel outputs.

Registers
 Parallel In Parallel Out (PIPO):
 Once the register is clocked, all the data at the
D inputs appear at the corresponding Q
outputs simultaneously.

Registers
 Bidirectional Shift Register: The registers
discussed so far involved only right shift
operations.
 Each right shift operation has the effect of
successively dividing the binary number by
two.
 If the operation is reversed (left shift), this has
the effect of multiplying the number by two.

Registers
 Bidirectional Shift Register: With suitable
gating arrangement a serial shift register can
perform both operations.
 A bidirectional, or reversible, shift register is
one in which the data can be shift either left or
right.
 A four-bit bidirectional shift register using D
flip-flops is shown below.

Registers
 Bidirectional Shift Register: .

Registers
 Bidirectional Shift Register: Here a set of
NAND gates are configured as OR gates to
select data inputs from the right or left
adjacent bistables, as selected by the
LEFT/RIGHT control line.

Counters
 Counter is a sequential circuit.
 A digital circuit which is used for a counting
pulses is known counter.
 Counter is the widest application of flip-flops.
It is a group of flip-flops with a clock signal
applied.
 Counters are of two types:
1. Asynchronous.
2. Synchronous counters.

Counters
 In an asynchronous counter, an
external event is used to directly SET or
CLEAR a flip-flop when it occurs.
 In a synchronous counter however,
the external event is used to produce a
pulse that is synchronised with the
internal clock.

Counters
1. Asynchronous : The logic diagram of a 2-bit
ripple up counter is shown in figure.
 The toggle (T) flip-flop are being used. But
we can use the JK flip-flop also with J and K
connected permanently to logic 1.
 External clock is applied to the clock input of
flip-flop A and QA output is applied to the
clock input of the next flip-flop i.e. FF-B.

Counters
1. Asynchronous : .

Counters
1. Asynchronous :

Counters
1. Asynchronous : Operations
Condition Operation
Initially let both the FFs
be in the reset state
QBQA = 00 initially
After 1st negative clock
edge
As soon as the first negative clock
edge is applied, FF-A will toggle and
QA will be equal to 1.
QA is connected to clock input of FF-B.
Since QA has changed from 0 to 1, it is
treated as the positive clock edge by
FF-B. There is no change in
QB because FF-B is a negative edge
triggered FF.
QBQA = 01 after the first clock pulse.

Counters
1. Asynchronous :
Condition Operation
After 2nd negative clock
edge
On the arrival of second negative clock
edge, FF-A toggles again and QA = 0.
The change in QA acts as a negative
clock edge for FF-B. So it will also
toggle, and QB will be 1.
QBQA = 10 after the second clock
pulse.

Counters
1. Asynchronous :
Condition Operation
After 3rd negative clock
edge
On the arrival of 3rd negative clock
edge, FF-A toggles again and
QA become 1 from 0.
Since this is a positive going change,
FF-B does not respond to it and
remains inactive. So QB does not
change and continues to be equal to 1.
QBQA = 11 after the third clock pulse.

Counters
1. Asynchronous :
Condition Operation
After 4th negative clock
edge
On the arrival of 4th negative clock
QA becomes 1 from 0.
This negative change in QA acts as
clock pulse for FF-B. Hence it toggles
to change QBfrom 1 to 0.
QBQA = 00 after the fourth clock pulse.

Counters
2. Synchronous Counter: If the "clock" pulses
are applied to all the flip-flops in a counter
simultaneously, then such a counter is called
as synchronous counter.
 2-bit Synchronous up counter
 The JA and KA inputs of FF-A are tied to logic
1. So FF-A will work as a toggle flip-flop. The
JB and KB inputs are connected to QA.

Counters
2. Synchronous Counter:

Counters
2. Synchronous Counter: Operations
Condition Operation
Initially let both the FFs
be in the reset state
QBQA = 00 initially.
After 1st negative clock
edge
As soon as the first negative clock
edge is applied, FF-A will toggle and
QA will change from 0 to 1.
But at the instant of application of
negative clock edge, QA , JB = KB = 0.
Hence FF-B will not change its state.
So QB will remain 0.
QBQA = 01 after the first clock pulse.

Counters
Condition Operation
After 2nd negative clock
edge
On the arrival of second negative clock
QA changes from 1 to 0.
But at this instant QAwas 1. So JB =
KB= 1 and FF-B will toggle. Hence
QB changes from 0 to 1.
QBQA = 10 after the second clock
pulse.

Counters
Condition Operation
After 3rd negative clock
edge
On application of the third falling clock
edge, FF-A will toggle from 0 to 1 but
there is no change of state for FF-B.
QBQA = 11 after the third clock pulse.
After 4th negative clock
edge
On application of the next clock pulse,
QAwill change from 1 to 0 as QB will
also change from 1 to 0.
QBQA = 00 after the fourth clock pulse.

Counters
 Classification of Counter: Depending on the
way in which the counting progresses, the
synchronous or asynchronous counters are
classified as follows −
1. Up counters
2. Down counters
3. Up/Down counters

Counters
 Classification of Counter: A ripple counter is
an asynchronous counter where only the
first flip-flop is clocked by an external clock. All
subsequent flip-flops are clocked by the output
of the preceding flip-flop.
 Asynchronous counters are also
called ripple-counters because of the way the
clock pulse ripples it way through the flip-flops.

Counters
 Up/Down counters: Up counter and down
counter is combined together to obtain an
UP/DOWN counter.
 A mode control (M) input is also provided to
select either up or down mode.
 A combinational circuit is required to be
designed and used between each pair of flip-
flop in order to achieve the up/down
operation.
 Type of up/down counters
 UP/DOWN ripple counters
 UP/DOWN synchronous counter 79RNB Global University, Bikaner.Course Code - 19004000

Counters
 UP/DOWN Ripple Counters: In the
UP/DOWN ripple counter all the FFs operate
in the toggle mode.
 So either T flip-flops or JK flip-flops are to be
used. The LSB flip-flop receives clock
directly. But the clock to every other FF is
obtained from (Q = Q bar) output of the
previous FF.

Counters
 UP/DOWN Ripple Counters:
 UP counting mode (M=0) − The Q output of
the preceding FF is connected to the clock of
the next stage if up counting is to be achieved.
For this mode, the mode select input M is at
logic 0 (M=0).
 DOWN counting mode (M=1) − If M = 1, then
the Q bar output of the preceding FF is
connected to the next FF. This will operate the
counter in the counting mode.

Counters

Counters
 Modulus Counter (MOD-N Counter): The 2-bit
ripple counter is called as MOD-4 counter and 3-bit
ripple counter is called as MOD-8 counter.
 MOD counters are defined based on the number of
states that the counter will sequence through before
returning back to its original value.
 For example, a 2-bit counter that counts from 002 to
112 in binary, that is 0 to 3 in decimal, has a modulus
value of 4 ( 00 → 01 → 10 → 11 , return back to 00 )
so would therefore be called a modulo-4, or mod-4,
counter.
 So in general, an n-bit ripple counter is called as
modulo-N counter.
Where, MOD number = 2n.

Counters
 Modulus Counter (MOD-N Counter): .

Counters
 Modulus Counter (MOD-N Counter): It is also
called as Johnson Counter.

Counters
 Ring Counter: A ring counter is a Shift
Register (a cascade connection of flip-flops)
with the output of the last flip flop connected to
the input of the first.
 It is initialised such that only one of the flip flop
output is 1 while the remander is 0. ... It can be
implemented using D-type flip-flops (or JK-
type flip-flops).

Counters
 Ring Counter:

Finite State Machines
 There are many ways of modeling the
behavior of systems, and the use of state
machines is one of the oldest and best known.
 State machines allow us to think about the
“state” of a system at a particular point in time
and characterize the behavior of the system
based on that state.
 The use of this modeling technique is not
limited to the development of software
systems.

 In fact, the idea of state-based behavior can
be traced back to the earliest considerations of
physical matter.
 For example, H2O can exist in 3 different
states easily observable in nature: solid (ice),
liquid (water), and gaseous (steam, fog,
clouds).
 In each of these states, the behavior of H2O is
different. The means of forcing transitions
between the 3 states is also well-defined.

 Many other natural and artificial systems may
also be modeled by defining
1. The possible states the system can occupy,
2. The behavior in each of those states, and
3. How the system transitions between the
states, including which states are “connected”
and which are not.

 We can use a similar technique to model and
design software systems by identifying what
states the system can be in, what inputs or
events trigger state transitions, and how the
system will behave in each state.

 An FSM, in its most general form, is a set of
flipflops that hold only the current state, and a
block of combinational logic that determines
the the next state given the current state and
some inputs.
 The output is determined by what the current
state is.
 Take a look at the following diagram.

 This is what an FSM looks like in hardware. The only
storage it has is for the current state. Since the main
block of logic is combinational, there can't be any flip-
flops inside of it. Remember, combinational
logic will produce the same outputs given the same
set of inputs at any time. 94RNB Global University, Bikaner.Course Code - 19004000

 The first thing to do when designing an FSM is
to figure out what states you will need.
 Since we are going to use the FSM to control
a robot, we need to think about the behavior
we want.
 First, the robot has two contact switches
mounted on the front of it as shown below.

 These are wired up so that when they are not
being pressed, the signal line is connected to
ground, but when pressed, it get connected
to +5V.
 By using these switches, the robot can realize
when it runs into something. For some basic
object avoidance, we will make the robot
back up when it hits something then turn right
if the left switch was pressed or turn left if the
right switch was pressed.

 When the robot hasn't hit anything it will just
drive forward.
 This leads us to five states.
1. FORWARD
2. BACKUP_RIGHT
3. TURN_RIGHT
4. BACKUP_LEFT
5. TURN_LEFT

 Notice that there are two versions of
the BACKUP state, BACKUP_RIGHT and BA
CKUP_LEFT. This is because we need to
encode in the states which one will turn right
after it backs up and which will turn left. If we
didn't have separate states, we would have to
read the state of the switch after it backed up
and at that point the switch would not be
pressed anymore.

 State Transitions:

Design of Sequential Circuits
 Design problem normally starts with a word
description of input output relation and ends
with a circuit diagram having sequential and
combinatorial logic elements.
 Sequential logic circuit design refers to
synchronous clock-triggered circuit because of
its design and implementation advantages.

 Steps involved in design of sequential
circuit:
1. Input output relation.
2. State transition diagram or Algorithmic State
Machine (ASM)chart.
3. State synthesis table –
1. Flip Flop based implementation - excitation tables are
used to generate design equations through Karnaugh Map.
2. Read Only Memory (ROM) based implementation -
excitation tables are not required but flip-flops are used as
delay elements

 Steps involved in design of sequential
circuit:
4. Circuit diagram is developed from these
design equations.

 State machine design: There are two
different approaches of state machine design
called Moore model and Mealy model.
 In Moore model circuit outputs, also called
primary outputs are generated solely from
secondary outputs or memory values.

 State machine design: In Mealy model circuit
inputs, also known as primary inputs combine
with memory elements to generate circuit
output.

 CONVERSION FROM ONE MODEL TO
OTHER:
 Conversion from one model to other can be
done through state diagram representation.
 Depending on application requirements we
choose one of these two models or a mixed
model where a part of the circuit follows Mealy
model and the other Moore model.

 Sequential Circuit Design Steps: The design
of sequential circuit starts with verbal
specifications of the problem.

 Sequential Circuit Design Steps:
 The next step is to derive the state table of the
sequential circuit. A state table represents the
verbal specifications in a tabular form.
 In certain cases state table can be derived
directly from verbal description of the problem.
 In other cases, it is easier to first obtain a state
diagram from the verbal description and then
obtain the state table from the state diagram.

 A state diagram is a graphical representation
of the sequential circuit.
 In the next step, we proceed by simplifying the
state table by minimizing the number of states
and obtain a reduced state table.
 The states in the reduced state table are then
assigned binary-codes. The resulting table is
called output and state transition table.

 From the state transition table and using flip-
flop’s excitation tables, flip-flops input
equations are derived. Furthermore, the output
equations can readily be derived as well.
 Finally, the logic diagram of the sequential
circuit is constructed.
 An example will be used to illustrate all these
concepts.

Design of Sequential Circuits - Example
 Sequence Recognizer:
 A sequence recognizer is to be designed to
detect an input sequence of ‘1011’. The
sequence recognizer outputs a ‘1’ on the
detection of this input sequence. The
sequential circuit is to be designed using JK
and D type flip-flops.
 A sample input/output trace for the sequence
detector is shown in Table below.

 We will begin solving the problem by first
forming a state diagram from the verbal
description.
 A state diagram consists of circles (which
represent the states) and directed arcs that
connect the circles and represent the
transitions between states. 114RNB Global University, Bikaner.Course Code - 19004000

 In a state diagram:
1. The number of circles is equal to the number
of states. Every state is given a label (or a
binary encoding) written inside the
corresponding circle.
2. The number of arcs leaving any circle is 2n,
where n is the number of inputs of the
sequential circuit.

 Before we begin our design, the following
should be noted
1. We do not have an idea about how many
states the machine will have.
2. The states are used to “remember”
something about the history of past inputs.
For the sequence 1011, in order to be able to
produce the output value 1 when the final 1 in
the sequence is received, the circuit must be
in a state that “remembers” that the previous
three inputs were 101. 116RNB Global University, Bikaner.Course Code - 19004000

 Before we begin our design, the following
should be noted.
3. There can be more than one possible state
machine with the same behavior.

 Deriving the State Diagram :
 Let us begin with an initial state (since a state
machine must have at least one state) and
denote it with ‘S0’ as shown in Figure below :

 Two arcs leave state ‘S0’ depending on the input
(being a 0 or a 1). If the input is a 0, then we return
back to the same state. If the input is a 1, then we
have to remember it (recall that we are trying to detect
a sequence of 1011). We remember that the last input
was a one by changing the state of the machine to a
new state, say ‘S1’. This is illustrated in Figure below :

 ‘S1’ represents a state when the last single bit
of the sequence was one. Outputs for both
transitions are zero, since we have not
detected what we are looking for.

 Again in state ‘S1’, we have two outgoing arcs.
If the input is a 1, then we return to the same
state and if the input is a 0, then we have to
remember it (second number in the
sequence). We can do so by transiting to a
new state, say ‘S2’. This is illustrated in Figure
below:

 Note that if the input applied is ‘1’, the next
state is still ‘S1’ and not the initial state ‘S0’.
This is because we take this input 1 as the first
digit of new sequence. The output still remains
0 as we have not detected the sequence.

 State ‘S2’ represents detection of ‘10’ as the last two
bits of the sequence. If now the input is a ‘1’, we have
detected the third bit in our sequence and need to
remember it. We remember it by transiting to a new
state, say ‘S3’ as shown in Figure below. If the input is
‘0’ in state ‘S2’ then it breaks the sequence and we
need to start all over again. This is achieved by
transiting to initial state ‘S0’. The outputs are still 0.

 In state ‘S3’, we have detected input sequence ‘101’.
Another input 1 completes our detection sequence as
shown in Figure 2 below. This is signaled by an output
1. However we transit to state ‘S1’ instead of ‘S0’
since this input 1 can be counted as first 1 of a new
sequence. Application of input 0 to state ‘S3’ means
an input sequence of 1010. This implies the last two
bits in the sequence were 10 and we transit to a state
that remembers this input sequence, i.e. state ‘S2’.
Output remains as zero.

 Deriving the State Table:
 A state table represents time sequence of
inputs, outputs, and states in a tabular form.
The state table for the previous state diagram
is shown in Table below.

 The state table can also be represented in an
alternate form as shown in Table:

 Here the present state and inputs are
tabulated as inputs to the combinational
circuit. For every combination of present state
and input, next state column is filled from the
state table.
 The number of flip-flops required is equal to
[log2(number of states)].
 Thus, the state machine given in the figure will
require two flip-flops [log2(4)]=2. We assign
letters A and B to them

 State Assignment :
 The states in the constructed state diagram
have been assigned symbolic names rather
than binary codes.
 It is necessary to replace these symbolic
names with binary codes in order to proceed
with the design.
 In general, if there are m states, then the
codes must contain n bits, where 2n ≥ m, and
each state must be assigned a unique code.

 There can be many possible assignments for
our state machine. One possible assignment is
show in Table below:

 The assignment of state codes to states
results in state transition table as shown -

 It is important to mention here that the binary
code of the present state at a given time t
represents the values stored in the flip-flops;
and the next-state represents the values of the
flip-flops one clock period later, at time t+1.

 General Structure of Sequence Recognizer:
 The specifications required using JK and D
type flip-flops.
 Referring to the general structure of sequential
circuit shown in Figure below, our synthesized
circuit will look like that as shown in the figure.
Observe the feedback paths.

 The state transition table as shown can now
be expanded to construct the excitation table
for the circuit.
 Since we are designing the sequential circuit
using JK and D type flip-flops, we need to
correlate the required transitions in state
transition table with the excitation tables of JK
and D type-flip-flops.

 The functionality of the required combinational
logic is encapsulated in the excitation table.
Thus, the excitation table is next simplified
using map or other simplification methods to
yield Boolean expressions for inputs of the
used flip-flops as well as the circuit outputs.

 Deriving the Excitation Table:
 Excitation table for D flip-flop-

 Excitation table for J-K flip-flop-

 The excitation table (See Table below)
describes the behavior of the combinational
portion of sequential circuit.

 For deriving the actual circuitry for the
combinational circuit, we need to simplify the
excitation table in a similar way we used to
simplify truth tables for purely combinational
circuits.
 Whereas in combinational circuits, our concern
were only circuit outputs; in sequential circuits,
the combinational circuitry is also feeding the
flip-flops inputs. Thus, we need to simplify the
excitation table for both outputs as well as flip-
flops inputs. 139RNB Global University, Bikaner.Course Code - 19004000

 We can simplify flip-flop inputs and output
using K-maps as shown in Figure

 Finally the logic diagram of the sequential
circuit can be made as shown in Figure

Design Asynchronous Circuits
 Used when speed of operation is important.
 Response quickly without waiting for a clock pulse.
 „Used in small independent systems. „
 Only a few components are required .„
 Used when the input signals may change
independently of internal clock .„
 Asynchronous in nature.„
 Used in the communication between two units
that have their own independent clocks. „
 Must be done in an asynchronous fashion.

 Definition of Asynchronous Circuits:
 Inputs / Outputs.
 Delay elements: „
 Only a short term memory. „
 May not really exist due to original gate delay.
 Secondary variable: „
 Current state (small y).
 Excitation variable: „
 Next state (big Y). „
 Have some delay in response to input changes.

 Operation Mode:
 Steady-state condition: „
 Current states and next states are the same. „
 Difference between Y and y will cause a transition. „
 Fundamental mode: „
 No simultaneous changes of two or more
variables. „
 The time between two input changes must be
longer than the time it takes the circuit to a stable
state. „
 The input signals change one at a time and only
when the circuit is in a stable condition. 144RNB Global University, Bikaner.Course Code - 19004000

 A race condition or race hazard is the
behavior of an electronic, software, or other
system where the output is dependent on the
sequence or timing of other uncontrollable
events.
 A race condition is said to be exist in
asynchronous sequential circuit when two or
more binary state variables change value in
response to change in an input variable.

 When the S and R inputs of an SR flipflop is
at logical 1 and then the input is changed to
any other condition, then the output becomes
unpredictable and this is called the race
around condition.

Reviews
 Various types of flip-flops and their
conversions.
 Registers, Timing issues, Counters-
Synchronous, Asynchronous.
 Finite state machines.
 Design of Synchronous sequential circuits.
 Design of Asynchronous circuits, cycles,
races and hazards.

Thank You!
RNB Global University, Bikaner. 148Course Code - 19004000

Sequential circuits

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