2. • Teaching Scheme
– Lectures: 3 Hrs/week
– Practical: 2 Hrs/Week
• Examination Scheme
– Paper: 100 Marks
– Practical: 50 Marks
– Oral: 25 Marks
3. Unit-I
VHDL Modeling and Design Flow
Introduction to VLSI: complete VLSI design flow
(with reference to an EDA tool). Sequential, Data
flow, and Structural Modeling. Functions.
Procedures, attributes. Test benches,
Synthesizable, and non synthesizable
statements; packages and configurations
Modeling in VHDL with examples of circuits such
as counters, shift registers, bidirectional bus, etc.
4. Unit 2
FSM And Sequential Logic Principles
Sequential Circuits, Meta-stability
Synchronization, Design of Finite State
Machines, and State minimization, FSM
CASE STUDIES - Traffic Light control. Lift
Control and UART STA and DTA
5. Unit 3
Programmable Logic Devices
Introduction to the CPLDs, Study of
architecture of CPLD. and Study of the
Architecture of FPGA
6. Unit 4
System On Chip
One, two phase clock, Clock distribution. Power
distribution. Power optimization, SRC and DRC,
Design validation, Global routing, Switch box
routing. Off chip connections, I/O Architectures,
Wire parasitics, EMI immune design. Study of
memory-Basics of memory includes types of
memory cells and memory architectures. Types of
memory, based on architecture specific and
application specific viz. SRAM, DRAM, SDRAM,
FLASH, FIFO.
7. Unit 5
CMOS VLSI
CMOS parasitics, equivalent circuit, body
effect, Technology Scaling, A. parameter.
Detail study of Inverter Characteristics,
power dissipation, power delay product,
CMOS combinational logic design and
W/L calculations. Transmission gates,
Introduction to CMOS layout.
8. Unit 6
Testability
Need of Design for testability, Introduction to
Fault Coverage, Testability. Design- for-
Testability, Controllability and Observability,
Stuck-at Fault Model. Stuck-Open and
Stuck-Short faults. Boundary Scan check.
JTAG technology; TAP Controller and TAP
Controller State Diagram. Scan path. Full
and Partial scan. BIST
9. Text Books
1. John F. Wakerly, "Digital Design, Principles
and Practices", Prentice Hall Publication
2. Neil H. E Weste and Kamran Eshraghian,
"Principles of CMOS VLSI Design".
3. Wayne Wolf, "Modern VLSI Design"
4. Sudhkar Yalamachalli, "Introductory VHDL from
simulation to Synthesis"
10. Reference Books
1. Perry "VHDL"
2. Charles Roth, "Digital System Design using VHDL". McGraw hill.
3. Xilinx Data Manual "The Programmable Logic Data Book".
4. Stephen Brown and Zvonko Vranesic, "Fundamentals of Digital
Logic with VHDL Design", Second Edition, McGraw-Hill, 2005.
5. Michael John Sebastian Smith, "Application-Specific Integrated
Circuits", Addison Wesley.
6. Wayne Wolf, "FPGA-Based System Design", Prentice Hall,
7. Miron Abramovici, "Digital Systems Testing and Testable Design",
Jaico Publishing.
8. Sung-Mo (Steve) kang, Yusuf Leblebici, " CMOS Digital
Integrated Circuit", Tata McGraw-Hill Publication.
11. LIST OF EXPERIMENTS
Any 8 assignments out of the following:
Simulation, Synthesis, and Implementation of:
1. 8: 1 Multiplexer, 2:4 Decoder, Comparator and Adder.
2. Flip Flop, Shift Register and Counter
3. Lift Controller /Traffic Light Controller/ UART. Anyone of the
three.
4. Parity generator and Checker.
5. Implementation of RAM/FIFO.
6. Ramp waveform generator using DAC
7. Bi-directional buffer
8. Temperature sensing using ADC, Displaying on 7-Segment
display and threshold setting using keyboard
9. Implementation of 4-bit RISC processor
16. Microelectronics
Is the art, science and technology of
designing and fabricating integrated circuits
with small-dimension electronic devices
Areas of Microelectronics are :
• VLSI Design
• VLSI CAD Tools
• Technology & Fabrication
• Physics
• Modeling and Simulation
• Characterization
• Testing
Nearly all the advances in the modern day electronic systems
and devices are a direct outcome of VLSI technology
17. Some keywords!
• Very-large-scale-integration (VLSI) is defined as a
technology that allows the construction and
interconnection of large numbers (millions) of transistors
on a single integrated circuit.
• Integrated circuit is a collection of one or more gates
fabricated on a single silicon chip.
• Wafer is a thin slice of semiconductor material on which
semiconductor devices are made. Also called a slice or
substrate.
• Chip is a small piece of semiconductor material upon
which miniaturized electronic circuits can be built.
• Die is an individual circuit or subsystem that is one of
several identical chips that are produced after dicing up
a wafer.
If you use these key-words often, people will
think that you are an expert VLSI engineer!!!
18. • The origin of this terminology can be traced as the logical extension
to the integration techniques namely the Small Scale Integration, SSI
(the ICs which functioned as logic gates, flip-flops), the Medium
Scale Integration, MSI (multiplexers, decoders)., the Large Scale
Integration LSI (early microprocessors, small memories, PAL, GAL
Technology
Number of
gates/transistors*
per chip
Examples Year
SSI 1 to 20
74XX series,
4xxx series
60’s
MSI 100 to 1000
74XXX series,
45XX series
70’s
LSI
1000 to 10,000/100 to
100,000*
8085, 80’s
VLSI
10,000 to
100,000/1,000,000
*
CPLD, FPGA,
advanced
μC, SoC
90’s
Dividing line between LSI and VLSI is somewhat fuzzy hence
number of transistors provides a good criterion
19. The advances in the integration techniques can be attributed
directly to :
•Advances in photolithography techniques
•New designs of semiconductor devices
•Newer methods of metallization
The development of integration technology has followed the
famous Moore’s Law. It was stated by Gordon Moore, co-founder of
Intel, in the year 1965, that “the number of transistors per chip
would grow exponentially (double every 18 months)”. In fact the
doubling period has shortened to a mere 12 months!
21. The number of transistors/gates that can fit in to the
semiconductor die dictates the complexity of the
functionality that the device can perform. The important
factors that fuel the research in VLSI technology can be
summarized as below:
• Increased functionality
• Higher reliability
• Small footprint
• Very low power consumption
• Increased speed of operation
• Re-programmability( except ASIC devices)
• Mass production
• Low cost
22. VLSI is thus a technology that can be
harnessed for various applications covering
analog, digital and mixed signal electronics.
The current trend is to reduce the entire
system design to a single chip solution
called as system on chip (SoC)
23. Building blocks of VLSI system on chip
Digital
MCU/MPU
Memory
MEMS
CCD sensors
microtransformers
microresonators
RF/Analog
Frequency generation
mixers
filters
VCO
LNA
RF power amplifiers
Opamps
Mixed-Signal DSP
Audio ,Video
circuits
MPEG engine
Power Management
converter
regulator
on-chip power supply
Applications
multimedia
computing
communications
biomedical
...
24. VLSI Design Process
VLSI technology thus provides a platform for developing
systems for various applications
The integrated circuits so developed can be further classified as :
25. ASIC
• An Application Specific Integrated Circuit
(ASIC) is a semiconductor device designed
especially for a particular customer (versus a
Standard Product, which is designed for general
use by any customer)
• The three major categories of ASIC Technology
are :
– Gate Array-Based
– Standard Cell-Based
– Full custom
26. Gate Arrays
• There are two types of gate arrays:
– a channeled gate array
– channel-less gate array
• A channeled gate-array is manufactured with single
or double rows of basic cells across the silicon
• A basic cell consists of a number of transistors
• The channels between the rows of cells are used for
interconnecting the basic cells during the final
customization process
• A channel-less gate array is manufactured with a
“sea” of basic cells across the silicon and there are
no dedicated channels for interconnection
• Gate arrays contain from a few thousand equivalent
gates to hundreds of thousand of equivalent gates
• Due to the limited routing space on channeled gate
arrays, typically only 70% to 90% of the total number
of available gates can be used
27. • The library of cells provided by a gate array
vendor will contain:
– primitive logic gates
– registers,
– hard-macros
– soft-macros
Hard-macros and soft-macros are usually of MSI and
LSI complexity, such as multiplexers, comparators
and counters.
Hard macros are defined by the manufacturer in terms
of cell primitives
Soft-macros are characterized by the designer, for
example, specifying the width of a particular counter
28. Standard Cell
• Standard cell devices do not have the concept of a basic
cell and no components are prefabricated on the silicon
chip
• The manufacturer creates custom masks for every stage
of the device’s process which leads to a more efficient
utilization of silicon as compared to gate arrays
• Manufacturers supply hard-macro and soft-macro
libraries containing elements of LSI and VLSI complexity,
such as controllers, ALUs and microprocessors.
• Additionally, soft-macro libraries contain RAM functions
that cannot be implemented efficiently in gate array
devices; ROM functions are more efficiently
implemented in cell primitives
29. The Characteristics of ASICs
The remarks that follow further discuss some
trade-offs of ASICs with respect to the
following categories:
• Complexity
• Silicon Efficiency
• Design Risks
• Prototype Turnaround
• NRE
• CAD / CAE Support
• Performance
30. Complexity
• Complexity here means the number of transistors (or the amount of
logic and/or memory) per given amount of area, plus the associated
interconnect capability
• Current Array-Based and Cell-Based chips accommodate as many
as 20,000,000 usable logic gates on a single die
• Array-Based designs -especially in a Channel-Free Array
technology - are capable of realizing functions that represent actual
system building blocks and incorporate system memory functions on
the same die
• The Array-Based memories do tend to be about 5 times less dense
than Cell-Based memories because they are constructed out of the
gates on the master slice. And full custom memories would provide
much higher densities than do Array-Based memories
• But in fact many designers who are using the Array-Based
technologies to get fast turn around tend to be using very small
“scratch pad” or “cache” types of memories which fit very well into
the ASIC concept
31. Silicon Efficiency
• Array-Based technologies focus on fast
implementation of logic integration onto a single
chip, rather than on absolute highest density.
• Cell-Based designs allow you to get more logic
onto a chip in a given area.
• Cell-Based designs feature transistors and
routing tracks whose gradations of size are finer
than those in Array-Based products. Thus Cell-
Based designs use silicon more efficiently than
Array-Based designs
32. NRE
• NRE (“Non-Recurring Engineering”) charges are
the costs associated with developing an ASIC
• NRE is based on a number of factors like:
– the complexity of the design,
– the technology chosen (# of masks required)
– the amount of work to be done by the customer and
by the silicon vendor
– the need for special cells or procedures
– the type of package required
– the schedule the number of layers of metal
– …
33. • The more work the silicon vendor does and the
more special the requirements, the higher will be
the NRE . The more work the customer does,
the lower the NRE !
• Array-Based designs require the fewest number
of design-specific masks and therefore offer the
lowest NRE to prototypes.
• Cell- Based designs require all masks to be
generated for the chosen process and therefore
the NRE charge will be higher for a Cell-Based
design than for an Array-Based design
34. Design Risks
• The penalty for discovering a design error
is higher for a Cell-Based ASIC than for an
Array-Based ASIC
• Mistakes after prototype fabrication in
Array-Based designs usually only require
that the metal mask layers be redone. On
the other hand, design changes for a Cell-
Based design may require that all masks
be redone !
35. Prototype Turnaround Time
(TAT)
• Designs that require a complete mask set (Cell-
Based) will always require more time to
manufacture than designs which use a basic set
of diffusion masks and only require
customization at the metal layers (Array-Based)
• This difference in time could be anywhere from
one week to 4 weeks depending on how fast the
silicon vendor can get masks from the mask
shop and depending on how long the FAB cycle
is for a given process
36. CAD / CAE Support
The use of EDA tools ensure:
• Clean documentation
• Reusable data
• Functional verification
• Easy modification
• Automated rule check
• Back-annotation (synchronization between
schematic and layout)
• Bill of material
37. Performance
• The two most critical parameters that have been used to
measure the worth of new technologies have been
speed and power
• High power circuits are normally fast, but the increased
power requires larger power supplies and tends to heat
up the junctions on silicon chips which slows the
devices.
• In today's most dominant ASIC technology - CMOS -
high power can cause accelerated junction temperatures
which can slow down speed
• One way to reduce the power and still maintain speed is
to develop circuits such as differential pairs that do not
switch from voltage rail to voltage rail
39. INITIAL DESIGN REVIEW
DESIGN ENTRY
SIMULATION & POWER
ANALYSIS
LOGIC & TEST
SYNTHESIS
CLOCK PLANNING/
CLOCK TREE SYNTHESIS
FLOORPLANNING
GATE-LEVEL
SIMULATION
FORMAL
VERIFICATION
TEST STRUCTURE
VERIFICATION
POWER
ESTIMATION
STATIC TIMING
ANALYSIS
PRE-LAYOUT
TECHNOLOGY
CHECKS
RELEASE TO LAYOUT
TIMING DRIVEN
LAYOUT/OPTIMIZATION
STATIC TIMING
ANALYSIS
POST LAYOUT
TECHNOLOGY CHECKS
AUTOMATIC TEST-PATTERN
GENERATION
RELEASE TO
MANUFACTURING
TIMING
ASSERTIO
NS
DESIGN LANDMARKS
FRONT-END TOOLS
TEST& VERIFICATION
TOOLS
LAYOUT & PHYSICAL
VERIFICATION TOOLS
ASIC Design
Flow (detailed)
40. Programmable logic device
(PLD)
• It is an integrated circuit able to implement
combinational and/or sequential digital functions
defined by the designer and programmed into
this circuit
• There are a wide variety of ICs that can have
their logic function “programmed” into them after
they are manufactured. Most of these devices
use technology that also allows the function to
be reprogrammed
41. • Historically, programmable logic arrays (PLAs) were the
first programmable logic devices
• PLAs contained a two-level structure of AND and OR
gates with user-programmable connections
• Using this structure, a designer could accommodate any
logic function up to a certain level of complexity using the
well-known theory of logic synthesis and minimization
• PLA structure was enhanced and PLA costs were
reduced with the introduction of programmable array
logic (PAL) devices
• Today, such devices are generically called
programmable logic devices (PLDs), and are the “MSI”
of the programmable logic industry
• The ever-increasing capacity of integrated circuits
created an opportunity for IC manufacturers to design
larger PLDs for larger digital-design applications
• However, the basic two-level AND-OR structure of PLDs
could not be scaled to larger sizes. Instead, IC
manufacturers devised complex PLD (CPLD)
architectures to achieve the required scale
42. • A typical CPLD is merely a collection of multiple PLDs
and an interconnection structure, all on the same chip. In
addition to the individual PLDs, the on-chip
interconnection structure is also programmable,
providing a rich variety of design possibilities
• CPLDs can be scaled to larger sizes by increasing the
number of individual PLDs and the richness of the
interconnection structure on the CPLD chip
• At about the same time that CPLDs were being invented,
other IC manufacturers took a different approach to
scaling the size of programmable logic chips.
• Compared to a CPLD, a field-programmable gate arrays
(FPGA) contains a much larger number of smaller
individual logic blocks, and provides a large, distributed
interconnection structure that dominates the entire chip
44. Top-Down design methodology
• Means describing a complete system at an
abstract level using hardware description
language(HDL) and the use of EDA tools
like partitioners and synthesizers
• More time is spent on designing HDL
models, considering different architectures
and considering system test & testability
issues. Practically no time is spent on
designing at gate level
To consider a concept without
thinking of a specific example;
consider abstractly or theoretically.
ABSTRACT
45. Levels of behavioural abstractionINCREASINGBEHAVIOURALABSTRACTION
INCREASINGDETAILEDREALIZATION&COMPLEXITY
TRANSISTOR / SWITCH
GATE
RTL / DATAFLOW
ALGORITHM
SYSTEM
CONCEPT
The process of
formulating
general
concepts by
abstracting
common
properties of
instances
46. • System Level: All the specifications (input and output) are
described at this level. This level completely ignores the
hardware structure. However HDLs are not useful at this stage.
It simply treats the design like a black box.
• Algorithmic (also called behavioural) level: This is the highest
level of abstraction provided by most HDLs. A module can be
implemented in terms of the desired deign algorithm without the
concern of the hardware implementation details. Design at this
level is very similar to a conventional high level language
programming like C.
• RTL (Register Transfer Level) (also called dataflow): At this level
the module is designed by specifying the data flow between the
registers. The designer is aware of how data flows between
hardware registers and how the data is processed in the design.
• Gate Level: The module is implemented in terms of logic gates
and interconnections between these gates. Design at this level
is similar to describing a design in terms of gate-level logic
diagram.
• Transistor (also called Switch) Level: This is the lowest level of
abstraction. A module can be implemented in terms of switches,
storage nodes, and the interconnections between them. Design
at this level requires knowledge of switch-level implementation
details.
48. PLD based design flow
•A decision has to be arrived at regarding the
selection of the type of a PLD since we have two
options the CPLD and the FPGA
•The selected device is then called the target
device
• Specifications
• Design Entry
• Compilation
• Functional Simulation/Verification
• Synthesis
• Post-synthesis simulation
• Implementation
• Timing Simulation
• Hardware Implementation
Steps involved:
49. SPECIFICATIONS
(STEP 1)
CREATE A DIGITAL DESIGN
BY
VHDL CODE
SCHEMATIC ENTRY
STATE DIAGRAM
(STEP 2)
COMPILATION
(STEP 3)
FUNCTIONAL SIMULATION
(STEP 4)
(SPECIFY TARGET DEVICE)
SYNTHESIS
(STEP 5)
SIMULATION
(POST SYNTHESIS)
(STEP 6)
IMPLEMENTATION
PLACE & ROUTE
Active-HDL
Xilinx ISE
Libero IDE
FPGA Advantage
Lattice ISP LEVER
Active-HDL
Modelsim
Xilinx XST
Synplify
Leonardo Spectrum
Active-HDL
Modelsim
(RTL Level)
Netlist
(Gate Level)
Optimized Netlist
(Gate Level)
(STEP 7)
SIMULATION
(TIMING ASPECTS)
Palace
Active-HDL
Modelsim
Xilinx IMPACT
Actel Flash Pro
(STEP 8)
HARDWARE
IMPLEMENTATION
HDL based design flow
50. Idea
Design Entry
(Schematic)
VHDL Template
Model
Generator
Target
Device
Library
Synthesis
(Synthesizer Tool)
Design Entry
(Text Editor)
Netlist
(EDIF,XNF,DSL...)
Functional Simulation
(VHDL Simulator)
Algorithmic Simulation
(VHDL)
Test Vectors
(Input Stimuli & Output
Expected)
Post- Simulation
(VHDL Simulator)
Structural VHDL
(VITAL primitives)
Timing Analysis
VITAL
Primitive
Library
SDF
(Delay Information)
Program Data
(Fuse Map: JED, HEX...)
Device Programming
JTAG-ISP
Chip
Placement & Routing
(Device Vendor's Tool)
Back-annotation
TO PLACE & ROUTE
NETLIST
Detailed HDL based design flow
51. • It may again include the input, output and ambient specifications
• Target device may be finalized
• Choice of target device as CPLD or FPGA depends on various factors
• Specific type of device may be selected by comparing the specifications
provided by the manufacturer in the datasheet and the actual design
requirements
6
3
31
5
5
15
11
24
Xilinx
Actel
Cypress
Altera
Lattice
AMD
AT&T
Others
• XILINX
• LATTICE
• LUCENT
• ALTERA
• ACTEL
• CYPRESS
• AT&T
• AMD
Specifications
52. Design Entry
• This is essentially the design entry point in an EDA tool
• It can be done by the following means:
• Block Diagram/Schematic capture
• State Diagram entry
• HDL code entry
53. Block Diagram/Schematic capture
• A schematic circuit is literally “drawn” in an appropriate graphical
editor
• The EDA tool associated with this task is called Schematic Capture
Tool
• An electrical rule check (ERC) is usually run
• The main job of the ERC tool is to check for incorrect electrical
connections for example if a VCC pin of an IC is accidentally shorted
to ground, then the ERC tool will point out such a discrepancy
• For this tool to be effective the IC pins have to be earlier declared as
power, ground, input, output, bidirectional etc.
• After removing the ERC errors a netlist is generated by the editor
• A netlist is a text file showing the nets i.e. a set of components
connected together
• It is also possible to generate VHDL netlist
55. State Diagram entry
• Many designs are most effectively described
/designed by state diagram approach.
• Effective for sequential designs
• The EDA tools provide a graphical interface so
that the designer can directly make an entry of
the state diagram and generate the netlist.
• This method is preferred since it is a fast way of
creating the design
57. HDL code entry
• A designer can enter his /her design using a hardware description
language (HDL)
• The HDLs prominent in the industry are “VHDL” and “Verilog”
• There is another language that is recently making ground called as
“System C”
• Being similar to C language gives it an advantage to be more user
friendly and comfortable to designers familiar with C
• Using the code entry method is the most preferred one since it
offers:
– Design flexibility
– Code re-use
– Easy modification
– Tighter control over resources
• A netlist is again created by compiling the HDL code
59. Compilation
• At this stage the design is said to be at the Register
Transfer Level (RTL)
• All the data manipulation is done here at the register of
the host CPU or we can say that the design is not in
terms of the logic gates but “internal” to the environment
• After successful compilation of the design using any one
of the three methods a netlist is generated which is
called the gate-level netlist
• The design now is translated in terms of the logic gates
and modular entities like multiplexers, decoders. Thus
we now have the design at Gate-level
60. Functional
Simulation/Verification
• There are two very different tasks in digital
system development
– Verification is the process of determining
whether a design meets the specification and
performance goals
– It concerns the correctness of the initial
design as well as the refinement processes
– Testing is the process of detecting the
physical defects of a die or a package that
occurred during manufacturing
61. Functional
Simulation/Verification
• A functional test is done by simulating the gate-level design using
logic simulators that may be available as a built-in feature of the
EDA tool. There are two ways of functional verification:
– Interactive mode
• In the interactive mode the designer can change the input signals and
observe the corresponding output behaviour of the design. This method is
becomes cumbersome for designs involving large number of inputs and
outputs.
– Batch mode
• Batch mode uses the concept of test-benches (also a piece of VHDL code)
that generates test patterns and checks the validity of the output. This mode
is attractive for larger designs.
• If any undesirable behaviour is observed, the designer can correct
the flaw by going back to the design entry level
• It is important here to note that none of the timing aspects have
been considered during this simulation. Functional verification can
thus be compared to the algorithm testing in conventional
programming languages
62. Synthesis
• Synthesis means to properly put together so as to make
the whole complex design
• At this stage it is necessary to specify the target device,
since the synthesis tool (again dedicated software)
requires knowing the resources available with the target
device
• Synthesis optimally maps the design functionality (at the
gate-level) in to the actual devices available with the
target device
• For example if the design uses a four- input AND gate
but since this is not available with the target device, the
synthesis tool can break down the four- input AND gate
into two two-input AND gates and map correspondingly
• Optimization is very important otherwise the design may
get “blown-up” and the target device may prove too small
for the design
• Synthesis tools have built-in proprietary algorithms for
optimization
63. Post-synthesis simulation
• After synthesis the design needs to be re-
checked to confirm its functionality
• Simulation at this level ensures that the
mapped design behaves correctly as
desired
• A possibility may exist wherein, the
synthesis tool may incorrectly recompose
the design while mapping
• Again timing parameters are ignored here
64. Implementation
• This is the process of physical placing of the design into
the target device.
• Though it is a physical placement, it still takes place in
the virtual environment provided by the EDA tool
• A physical map of the target device is loaded into the
environment and the components are virtually fitted into
the target device.
• Again this process may have two phases:
– Physical synthesis
• Physical synthesis means optimal relocation of the design into the
target device. Proprietary software tools are available for this task
and may be quite costly. This phase is however optional.
– Place and route
• Place and route is the phase where the tool completes the task of
virtually placing the components of the design in to the target device
and then wiring the individual modules to complete the design.
65. Timing Simulation
• One most important change the design undergoes is
after the implementation.
• The modules in the design now may be physically placed
apart from each other.
• This factor introduces the delay aspect in the signal
propagation.
• Many synchronous circuits will fail if the timing aspects
are ignored, even though they appear to be functionally
perfect!
• Hence a simulation is necessary again to test the timing
behaviour of the design.
• This provides the designer with a better view of the
design functionality.
• In fact the real-world behaviour of the device can be very
accurately studied by the simulation with timing aspects
66. Hardware Implementation
• The final step in design is to “download”
the functionality into the actual hardware
i.e. the target device
• The synthesis tool generates the output in
terms of “bit-stream” that is used to
configure the target device
• Vendor specific tools can be used for
downloading the bit-stream into the
physical device
67. HDL
• A hardware description language (HDL) is a software coding
language used to model the intended operation of a piece of
hardware
• There are two aspects to the description of hardware that an HDL
facilitates:
– true abstract behaviour modeling
– hardware structure modeling
• Abstract behaviour modeling
– A hardware description language is declarative in order to facilitate the
abstract description of hardware behaviour for specification purpose.
This behaviour is not influenced by structural or design aspects of the
hardware intent.
• Hardware structure modeling
– Hardware structure is capable of being modeled in a hardware
description language irrespective of the design’s behaviour.
68. VHDL
• What is VHDL?
– Digital system design using Hardware
Description Language is an established
methodology in EDA
– VHDL stands for
“VERY HIGH SPEED INTEGRATED CIRCUITS
HARDWARE DESCRIPTION LANUAGE”
EDA stands for “ELECTRONIC DESIGN AUTOMATION”
69. FEATURES
• VHDL is an amalgamation of following
languages
– Concurrent language
– Sequential Language
– Timing Specification
– Simulation Language
– Test Language
70. • VHDL has got powerful language
constructs
– {if…else}, {with…select} etc
• Design hierarchies to create modular
designs
• Supports Design Libraries
• Facilitates device independent design and
portability
71. Concurrent Language
• Concurrent statements execute at the same time
in parallel as in hardware
Z <= C + X ;
X <= A + B ;
+
+
A
B
C
X
Z
72. Sequential Language
• Sequential statements execute one at a
time in sequence
• As the case with any conventional
programming language the sequence of
statements is important
Z <= C + X ;
X <= A + B;
X <= A + B;
Z <= C + X ;≠
Sequential statements are required to design sequential circuits
73. Timing Specification
• Providing timing attributes in a sequential digital
design is of prime importance since the
operations are synchronized to a common clock
• Example:
process
begin
clk <= ‘0’ ;
wait for 20 ns ;
clk <= ‘1’ ;
wait for 12 ns ;
end process ;
0 20 32 52 64
ns
84
Timing can be specified in a process only
74. Simulation language
• For analyzing a digital design it is
important the design be simulated
• Simulation has different flavours
– Functional simulation
– Post-synthesis simulation
– Post- layout simulation
• Any HDL should thus be equipped with
simulation capability for verification and
troubleshooting purposes
75. Test Language
• Testbench
– It is a part of a VHDL module that generates a
set of test vectors (test inputs) and sends
them to the module being tested
– It collects the responses generated by the
module under test and compares them
against a specification of correct results
– Thus testbench is required to ensure that the
design is correct and that the module is
operating as desired
Equivalent to checking of logical errors in any conventional programming
language
76. Testbench use
Test
tst_a
tst_b
tst_c
MODULE UNDER TEST
ABC.vhdABC_testbench.vhd
Equivalent to mechanical test jigs used for testing functionality of mass
produced pcbs as in TV sets or motherboards
77. Design Hierarchy
• Hierarchy can be represented using VHDL
• Example
– A full adder which is the top level module being
composed of three lower level modules that are; half
adder and OR gate
HALF
ADDER
HALF
ADDER
OR
A
B
Cin
SUM
CARRY
Design hierarchy simplifies the design procedure and manageability in case
of complex designs
78. Design Libraries
• Design Unit
– It is any block of VHDL code or collection of VHDL
codes that may be independently analyzed and
inserted into a design library
• Design Library
– It is a storage facility in which analysed VHDL
descriptions are stored for repeated uses
1
3
2
54
Design
Library
Simulator
Analyze
DESIGN UNIT
79. Logic systems
• Need for multi-valued logic system
– Conventional logic systems have only three values
i.e. ‘0’, ‘1’, ‘Z’
• Example
– Consider the truth-table for AND gate
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
0 Z ?
HOW TO RESOLVE THIS CONDITION ?
80. • For this problem a 9-valued logic system
or package was developed that is called
“STD_LOGIC_1164” and it is accepted as
IEEE STD 1164-1993
• Multi-valued logic
– Unknown: value was known but not anymore
– Un-initialized: value was never known
– High impedance: net has no driver
– Drive strengths: handle different output
drivers
– Don’t care: value is immaterial
81. Levels of abstraction
• Different styles are adopted for writing VHDL
code
• Abstraction defines how much detail about the
design is specified in a particular description
• Four levels are:
– Layout level
– Logic level
– Register Transfer level
– Behavioral level LOGIC
LAYOUT
RTL
BEHAVIORAL
82. Layout Level
• This is the lowest level and describes the
CMOS layout level design on silicon
83. Logic Level
• Design has information about
– Function
– Architecture
– Technology
– Detailed timings
• Layout information and analog effects are
ignored
84. Register Transfer Level
• Using HDL every register in the design
and the logic in between is defined
• Design contains:
– Architecture information
– No details of technology
– No specification of absolute timing delays
85. Behavioral Level
• Describing function of a design using HDL
without specifying the architecture of
registers
• Contains timing information required to
represent a function
86. Basic building blocks of VHDL
code
• A VHDL design is composed of following
blocks:
– Library declarations
– Entity
– Architecture
– Configuration
92. Library
• It is a collection of compiled VHDL units
• It enables sharing of compiled designs and
hides the source code from the users
• Commonly used functions, procedures and
user data types can be compiled into a user
defined library for use with all designs
• Library should be declared before each
entity declaration even if it is in the same
VHDL file
93. Library
• To declare a library (i.e. to make it visible to the
design) two lines of code are needed , one
containing name of the library, the other a use
clause
• A library structure can be as follows:
FUNCTIONS
PROCEDURES
TYPES
CONSTANTS
COMPONENTS
LIBRARY
PACKAGE
94. Library syntax
LIBRARY library_name ;
USE library_name.package_name.package_parts ;
LIBRARY IEEE ; -- semicolon indicates
USE IEEE.std_logic_1164.all ; -- end of statement or
-- declaration
LIBRARY work ; -- double dash (--)
-- indicates a comment
USE work.all ;
Example
95. Library details
IEEE.MATH_COMPLEX.all This package defines a standard for designers
to use in describing VHDL models that make
use of common COMPLEX constants and
common COMPLEX mathematical functions and
operators.
IEEE.MATH_REAL.all This package defines a standard for designers
to use in describing VHDL models that make
use of common REAL constants and common
REAL elementary mathematical functions.
IEEE.NUMERIC_BIT.all This package defines numeric types and
arithmetic functions for use with synthesis tools.
Two numeric types are defined:
-- UNSIGNED: represents an UNSIGNED
number in vector form
-- SIGNED: represents a SIGNED number in
vector form
The base element type is type BIT.
96. Library details
IEEE.NUMERIC_STD.alll This package defines numeric types and
arithmetic functions for use with synthesis tools.
Two numeric types are defined:
-- UNSIGNED: represents UNSIGNED number in
vector form
-- SIGNED: represents a SIGNED number in
vector form
-- The base element type is type STD_LOGIC.
IEEE.STD_LOGIC_1164.all This package defines a standard for designers
to use in describing the interconnection data
types used in VHDL modeling.
Defines multi-value logic types and related
functions.
IEEE.STD_LOGIC_ARITH.all This package defines a set of arithmetic,
conversion, and comparison functions
for SIGNED, UNSIGNED, SMALL_INT,
INTEGER, STD_ULOGIC, STD_LOGIC, and
STD_LOGIC_VECTOR.
97. Library details
IEEE.STD_LOGIC_MISC.alll This package defines supplemental types,
subtypes, constants, and functions for the
Std_logic_1164 Package.
IEEE.STD_LOGIC_SIGNED.all This package defines a set of signed
arithmetic, conversion, and comparison
functions for STD_LOGIC_VECTOR.
IEEE.STD_LOGIC_TEXTIO.all This package overloads the standard
TEXTIO procedures READ and WRITE.
IEEE.STD_LOGIC_UNSIGNED.all This package defines a set of unsigned
arithmetic, conversion and comparison
functions for STD_LOGIC_VECTOR.
98. Entity
– It is the design’s interface to the external
circuitry
– Equivalent to pinout /package of an IC
– VHDL design must include one and only one
entity per module
– It can be used as a component in other
entities after being compiled into a library
99. Entity declaration
• Defines the input and output ports of the design
• Name of the entity can be anything other than
the reserved VHDL word
• Each port in the port list must be allotted:
– a name ( should be self-explanatory that provides
information about its function
– data flow direction or mode
– a type
• Ports should be well documented with
comments at the end of line providing additional
information about the signal
100. Entity syntax
entity entity_name is
port ( port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ) ;
end entity_name ;
101. Modes
• Ports in the portlist have modes which
indicate the driver direction
• Mode also indicates whether or not the
port can be read from within the entity
• Four modes are available:
– Mode IN
– Mode OUT
– Mode INOUT
– Mode BUFFER
102. • Mode IN
Value can be read from but not assigned to (by
the entity)
ENTITY
Port signal A
Drivers reside
outside the entity
port ( A : in std_logic ) ;
103. • Mode OUT
Value can be assigned to but not read from (by
the entity)
port ( B : out std_logic ) ;
ENTITY
Port signal B
Drivers reside
inside the entity
104. • Mode INOUT
Bi-directional , value can be assigned to as well
as read from (by the entity)
port ( C : inout std_logic ) ;
ENTITY
Port signal C
Drivers reside both
inside and
outside the entity
105. • Mode BUFFER
Output port with internal read capability
port ( D : buffer std_logic ) ;
ENTITY
Port signal D
Drivers reside
inside the entity
Signal can be read inside the entityDO NOT USE UNLESS REQUIRED
106. Entity example
entity and_gate is
port ( 1A , 2A , 3A, 4A : in std_logic ;
1B , 2B , 3B, 4B : in std_logic ;
1Y , 2Y , 3Y, 4Y : out std_logic ) ;
end and_gate ;
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
7
3Y
8
3A
9
3B
10
4Y
11
4A
12
4B
13
VCC
14
107. Entity example
entity ALU is
port ( In1 : in std_logic_vector ( 3 downto 0) ; -- 1st operand
In2 ; in std_logic_vector ( 3 downto 0) ; -- 2nd operand
Opsel : in std_logic_vector ( 3 downto 0) ; -- opn select
Cin : in std_logic ;
Mode : in std_logic ;
Result : out std_logic_vector ( 3 downto 0 ) ;
Cout : out std_logic ;
Equal : out std_logic ) ;
end ALU ;
ALU
In1 In2
Op
sel
Result
Cout
Mode
Cin
Equal
108. Architecture
It specifies
• Behaviour
• Function
• Relationship between inputs and outputs of an entity
Syntax
architecture achitecture_name of entity_name is
[declarations] -- optional
begin
code -- concurrent statements only
end achitecture_name ;
109. • Architecture can contain only concurrent
statements
• A design can be described in an
architecture using various levels of
abstraction
• An entity can have more than one
architectures since a function can be
implemented in a number of ways
• There can be no architecture without an
entity
110. Architectural bodies
• Behavioural
– It is the high-level description
– It contains a set of assignment statements to represent
behaviour
– No need to focus on the gate-level implementation of a design
Example:
architecture behave of and_gate is
begin
process ( a, b )
if a=‘1’ and b=‘1’ then
c <= ‘1’ ;
else
c <=‘0’ ;
end if ;
end process ;
end behave ;
111. • Dataflow
– It uses concurrent signal assignment
statements
Example:
architecture dataflow of and_gate is
begin
c<= a and b ;
end dataflow ;
112. • Structural
– Components from libraries are connected
together
– Designs are hierarchical
– each component can be individually simulated
– it makes use of component instantiation
HALF
ADDER
HALF
ADDER
OR
A
B
Cin
SUM
CARRY
Functional units
Top level design
113. Configuration
• Since a number of architectures can exist
for an entity , using configuration
statement we can bind a particular
architecture to the entity
configuration CONFIGURATION_NAME of ENTITY_NAME is
for ARCHITECTURE_NAME
end for;
end CONFIGURATION_NAME;
Syntax
116. • VHDL is a strongly typed language
– Designers have to declare the type before
using it
• VHDL is not case sensitive ( but avoid
mixed cases as a good programming
practice)
• VHDL supports a wide variety of data
types and operators
– OBJECTS
– OPERATORS
– AGGREGATES
117. Objects
• They are used to represent and store the
data in the design being described
• Object contains a value of specific type
Class Object Data type
SIGNAL COUNT : INTEGER
This results in an object called COUNT that holds
INTEGER value that belongs to class SIGNAL
• The name given to the object is called as
identifier
• Do not use reserved words as identifiers
118. • Each object has a data type and class
• Class indicates how the object is used in the
module and what can be done with that object
• Type indicates what type of data the object
contains
• Each object belongs to one of the following class:
– CONSTANT
– SIGNAL
– VARIABLE
– FILES
CONSTANT SIGNAL VARIABLE
CLASS
FILES
119. Data Types
• In order to write VHDL code efficiently it is
necessary to study the specification and use of
data types
• Following are the categories of data types:
– Pre-defined
– User defined
– Subtypes
– Arrays
– Port arrays
– Records
– Signed and unsigned
120. Pre-defined data types
• Specified by IEEE 1076 and IEEE 1164
Package Library Type/Functions
standard std BIT, BOOLEAN,
INTEGER, REAL
std_logic_1164 ieee STD_LOGIC,
STD_ULOGIC
std_logic_arith ieee SIGNED, UNSIGNED /
data conversion functions
std_logic_signed ieee Functions that allow
operations with
STD_LOGIC_VECTOR
std_logic_unsigned ieee
121. BIT (and BIT_VECTOR): 2 level logic (‘0’, ‘1’)
Examples:
SIGNAL X : BIT ;
X is declared
as a one-
digit SIGNAL
of type BIT
SIGNAL Y : BIT_VECTOR (3 downto 0);
Y is 4-bit
vector,
leftmost bit
is MSB
SIGNAL W : BIT_VECTOR (0 to 7);
W is 8-bit
vector,
rightmost bit
is MSB
122. • To assign a value to the signal use the
operator “ < = ”
• Assignment examples:
X <= ‘1’ ;
X is a single bit SIGNAL whose value is ‘1’
Note that single quotes are used for a single bit
Y <= “0111” ;
Y is a 4- bit SIGNAL whose value
is “0111” . Note that double
quotes are used for vectors
W <= “01110001” ;
W is an 8- bit SIGNAL whose
value is “0111001” . MSB is ‘1’
123. STD_LOGIC (and STD_LOGIC_VECTOR):
8 valued logic (introduced in IEEE 1164 standard)
Symbol Description Remark
‘X’ Forcing unknown Synthesizable unknown
‘0’ Forcing low Synthesizable logic ‘0’
‘1’ Forcing high Synthesizable logic ‘1’
‘Z’ High impedance Synthesizable tri-state buffer
‘W’ Weak unknown
‘L’ Weak low
‘H’ Weak high
‘-’ Don’t care
124. Examples:
SIGNAL X : STD_LOGIC ;
X is declared as a one-digit
(scalar) SIGNAL of type
STD_LOGIC
SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0);
Y is 4-bit
vector, leftmost
bit is MSB
SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0) : = “0001”
for (optional)
initial value use
“ := ”
Most of std_logic levels are intended for simulation
only. However ‘0’, ‘1’ and ‘Z’ are synthesizable with
no restrictions
125. • With respect to
“weak” values, they
are resolved in favour
of the “forcing” values
in multiple-driven
nodes. If any two
std_logic signals are
connected to the
same node, then
conflicting logic levels
are resolved by using
the shown table
X 0 1 Z W L H -
X X X X X X X X X
0 X 0 X 0 0 0 0 X
1 X X 1 1 1 1 1 X
Z X 0 1 Z W L H Z
W X 0 1 W W W W X
L X 0 1 L W L W X
H X 0 1 H W W H X
- X X X X X X X X
•The STD_ULOGIC has 9 valued logic levels : additional
value is ‘U’ for “Un-resolved or ”Un-initialized”
126. • Other types
BOOLEAN TRUE, FALSE
INTEGER 32-bit integers (from - 2,147,483,647 to +
2,147,483,647
NATURAL Non-negative numbers (from 0 to
2,147,483,647
REAL Real numbers (from -1.0E-38 to +1.0E38)
Physical
literals
Used to inform physical quantities like , time,
voltage etc. Useful for simulation but not
synthesizable
Character
literals
Single ASCII character or a string of such
characters. Not synthesizable
SIGNED,
UNSIGNED
They have appearance of
STD_LOGIC_VECTOR, but accept arithmetic
operations which are typical of INTEGER data
type
127. User defined data types
• VHDL allows user defined data types
• Two categories of this data type are:
– Integer
– Enumerated
• User defined integer type
TYPE my_integer IS RANGE -32 to +32 ;
TYPE student_grade IS RANGE 0 to 100 ;
128. • User defined enumerated type
TYPE my_logic IS (‘0’, ‘1’, ‘Z’ );
TYPE my_state IS ( idle, forward, backward, stop) ;
An enumerated type, typically used
in state machines
• The encoding of enumerated types is done
sequentially and automatically
• Since here there are 4 states only two bits
are required hence “00” is assigned to first
state ( idle), “01” to second state (forward)
and so on.
129. Subtypes
• A SUBTYPE is a TYPE with a constraint
• Though operations between data of
different types are not allowed, they are
allowed between the subtype and its
corresponding base type
SUBTYPE sub_state IS my_state RANGE idle to backward ;
This means that the subtype
sub_state =(idle, forward, backward)
130. Arrays
• Arrays are collections of objects of same type
• Can be 1-dimensional, 2-dimensional or
1D X 1D
• Higher dimensional arrays are possible but not
synthesizable
0 0 1 0 0
1 0 1 0
1 1 0 0
0 1 0 0
1 1 0 1
0 1 0 1 0
1 0 1 1 0
0 1 0 1 0
Scalar
1D
1D x 1D
2D data array
131. Array syntax
TYPE type_name IS ARRAY (specification) OF data_type ;
To specify an array :
SIGNAL signal_name : type_name [:= initial_value]
To use an array :
132. Example : 1D x 1D array
– We want to build an array containing 4
vectors, each of size 8 bits
– we will call each vector as row and the
complete array as matrix
TYPE row IS ARRAY (7 downto 0 ) OF STD_LOGIC ;
TYPE matrix IS ARRAY (3 downto 0 ) OF row ;
SIGNAL X : matrix ;
1D x 1D SIGNAL
133. Example : 2D array
– This array will be created with scalars only
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0 ) OF STD_LOGIC ;
L
M L
M
ROWS
COLUMNS
134. Port Arrays
• In the specification of the input or output
pins (PORTS) of a circuit (which is made in
the ENTITY), we might need to specify the
ports as arrays of vectors.
• Since TYPE declarations are not allowed
in an ENTITY, the solution is to declare
user-defined data types in a PACKAGE,
which will then be visible to the whole
design (thus including the ENTITY)
135. ------- Package: --------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------
PACKAGE my_data_types IS
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR(7 DOWNTO 0);
END my_data_types;
--------------------------------------------
------- Main code: -------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_data_types.all; -- user-defined package
---------------------------
ENTITY mux IS
PORT (inp: IN VECTOR_ARRAY (0 TO 3);
... );
END mux;
... ;
--------------------------------------------
136. • As can be seen in the example above, a user-
defined data type, called vector_array,was
created, which can contain an indefinite number
of vectors of size eight bits each (NATURAL
RANGE <> signifies that the range is not fixed,
with the only restriction that it must fall within the
NATURAL range, which goes from 0 to
+2,147,483,647)
• The data type was saved in a PACKAGE called
my_data_types, and later used in an ENTITY to
specify a PORT called inp
• Notice in the main code the inclusion of an
additional USE clause to make the user-defined
package my_data_types visible to the design.
137. Records
• Records are similar to arrays, with the only
difference that they contain objects of
different types.
TYPE birthday IS RECORD
day: INTEGER RANGE 1 TO 31;
month: month_name;
END RECORD;
138. Signed and Unsigned data types
• These types are defined in the
std_logic_arith package of the ieee library
Examples:
SIGNAL x: SIGNED (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3);
139. • An UNSIGNED value is a number never lower
than zero. For example, ‘‘0101’’
represents the decimal 5, while ‘‘1101’’ signifies
13.
• If type SIGNED is used instead, the value can
be positive or negative (in two’s complement
format). Therefore,‘‘0101’’ would represent the
decimal 5, while ‘‘1101’’ would mean 3.
• To use SIGNED or UNSIGNED data types, the
std_logic_arith package, of the ieee library, must
be declared
142. Operators
• VHDL provides several kinds of pre-
defined operators
– Assignment operators
– Logical operators
– Arithmetic operators
– Relational operators
– Shift operators
– Concatenation operators
143. Assignment operators
• Are used to assign values to signals, variables,
and constants.
<= Used to assign a value to a SIGNAL
:=
Used to assign a value to a
VARIABLE, CONSTANT, or
GENERIC
Used also for establishing initial values
=> Used to assign values to individual
vector elements or with OTHERS
144. SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
x <= '1'; -- '1' is assigned to SIGNAL x using "<="
y := "0000"; -- "0000" is assigned to VARIABLE y using
--":="
w <= "10000000"; -- LSB is '1', the others are '0'
w <= (0 =>'1', OTHERS =>'0'); -- LSB is '1', the others
-- are '0'
Then the following assignments are legal:
145. Logical operators
• Used to perform logical operations.
• The data must be of type:
– BIT, STD_LOGIC
– STD_ULOGIC
– BIT_VECTOR
– STD_LOGIC_VECTOR
– STD_ULOGIC_VECTOR
146. • The logical operators
are:
– NOT
– AND
– OR
– NAND
– NOR
– XOR
– XNOR
The NOT
operator has
precedence
over the
others
Examples:
y <= NOT a AND b; -- (a'.b)
y <= NOT (a AND b); -- (a.b)'
y <= a NAND b; -- (a.b)'
147. Arithmetic operators
• Used to perform arithmetic operations. The data
can be of type INTEGER, SIGNED, UNSIGNED,
or REAL (the last cannot be synthesized
directly).
• Also, if the std_logic_signed or the
std_logic_unsigned package of the ieee library is
used, then STD_LOGIC_VECTOR can also be
employed directly in addition and subtraction
operations
148. + ( Addition)
- (Subtraction)
* (Multiplication)
/ (Division)
** (Exponentiation)
MOD ( Modulus)
REM ( Remainder)
ABS ( Absolute value)
•There are no synthesis restrictions regarding addition and
subtraction, and the same is generally true for multiplication
•For division, only power of two dividers (shift operation) are
allowed
•For exponentiation, only static values of base and exponent
are accepted
•Regarding the mod and rem operators, y mod x returns the
remainder of y/x with the signal of x, while y rem x returns the
remainder of y/x with the signal of y
•Finally, abs returns the absolute value
For mod, rem, abs , there
generally is little or no
synthesis support
149. Comparison operators
= Equal to
/= Not equal to
< Less than
> Greater than
<= Less than or equal to
>= Greater than or equal to
Also called RELATIONAL
operators
150. Shift operators
sll shift left logical
srl shift right logical
sla shift left arithmetic
sra shift right arithmetic
ror rotate left logical
rol rotate right logical
0
0
LOGICAL
SHIFTING
ARITHMETIC SHIFTING
(retains sign bit)
ROTATE
• LOGICAL
• ARITHMETIC
• ROTATE
151. Concatenation operator
• Operands can be one-dimensional array type
or element type
• “ &” works on vectors only
& Concatenation
Example:
SIGNAL a : STD_LOGIC_VECTOR ( 5 DOWNTO 0 ) ;
SIGNAL b,c,d : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ;
BEGIN
b <= ‘0’ & c(1) & d(2) ;
a <= c & d ;
. . .
152. Operator summary
Operator type Operators Data types
Logical
NOT, AND, AND
OR, NOR, XOR,
XNOR
BIT, BIT_VECTOR, STD_LOGIC,
STD_LOGIC_VECTOR, STD_ULOGIC,
STD_ULOGIC_VECTOR
Arithmetic
+, -,*,/,**
(mod, rem , abs)
INTEGER, SIGNED, UNSIGNED
Comparison =, /=, <, >, <=, >= All above
Shift
sll, srl, sla, sra,
rol, ror
BIT_VECTOR
Concatenation &, ( , , , )
Same as for logical operators, plus
SIGNED and UNSIGNED
153. Operator overloading
• Operators can be user-defined
• Let us consider the pre-defined arithmetic
operators seen earlier (+,- , *, /, etc.). They
specify arithmetic operations between data
of certain types (INTEGER, for example)
• For instance, the pre-defined ‘‘+’’ operator
does not allow addition between data of
type BIT.
• We can define our own operators, using
the same name as the pre-defined ones
154. • For example, we could use ‘‘+’’ to indicate
a new kind of addition, this time between
values of type BIT_VECTOR. This
technique is called operator overloading
• Example: Consider that we want to add an
integer to a binary 1-bit number. Then the
following FUNCTION could be used
FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS
BEGIN
IF (b='1') THEN RETURN a+1;
ELSE RETURN a;
END IF;
END "+";
155. A call to the function above could thus be the
following:
SIGNAL inp1, outp: INTEGER RANGE 0 TO
15;
SIGNAL inp2: BIT;
(...)
outp <= 3 + inp1 + inp2;
(...)
• In ‘‘outp<=3+inp1+inp2;’’, the first ‘‘+’’ is the pre-
defined addition operator (adds two integers),
while the second is the overloaded user-defined
addition operator (adds an integer and a bit).
156. Aggregates
• It assigns values to elements of an array
a <= (OTHERS => ‘0’ ) ; a <= “0000” ;
• We can assign values to some bits in a
vector and use “OTHERS” clause to assign
default values to remaining bits
a <= (0 => ‘1’, 2 => ‘1’, OTHERS => ‘0’ ) ;
is equivalent to
a <= “00101” ;
Useful when we are
dealing with large vectors
157. • Each object has a data type and class
• Class indicates how the object is used in the
module and what can be done with that object
• Type indicates what type of data the object
contains
• Each object belongs to one of the following class:
– CONSTANT
– SIGNAL
– VARIABLE
CONSTANT SIGNAL VARIABLE
CLASS
Classes re-visited
158. Constants
• These are identifiers with fixed values
• The value is assigned only once when
declared
• Values cannot be changed during
simulation
CONSTANT bus_width : INTEGER :=16 ;
CONSTANT CLK_PERIOD : TIME :=15 ns ;
• Constants make the design description
more readable
• Design changed at later time becomes
easy
159. Signals
Equivalent to wires
within a circuit
Example:
architecture and_gate of myand is
signal TEMP : STD_LOGIC ;
begin
U1 : AND2 portmap ( a, b, TEMP ) ;
U2 : AND2 portmap (TEMP, c , d ) ;
end and_gate ;
a
b
AND2
TEMP
c
AND2
d
160. • Thus signals are used :
– to connect design entities together and
communicate changes in values within a
design
– instead of INOUT mode
• Each signal has a history of values i.e.
they hold a list of values which include
current value of the signal and a set of
possible future values that can appear on
the signal
• Computed value is assigned to signal after
specified delay called DELTA DELAY
161. Variables
• These are objects with single current
value
• They are used to store the intermediate
values between the sequential statements
• Variable assignment occurs immediately
• Variables can be declared and used inside
the process statement only. But they retain
their value throughout the entire simulation
162. process ( a )
variable count : INTEGER : = 1 ;
begin
count : = count+ 1 ;
end process ;
Example :
count contains the total
number of events that
occurred on signal a
165. Attributes
• An attribute is data that are attached to VHDL
objects or predefined data about VHDL objects
• Examples are the current drive capability of a
buffer or the maximum operating temperature of
the device
• Types are
– Data Attributes
– Signal Attributes
– User-defined Attributes
166. Data Attributes
The pre-defined, synthesizable data attributes
are the following:
• d’LOW : Returns lower array index
• d’HIGH : Returns upper array index
• d’LEFT : Returns leftmost array index
• d’RIGHT : Returns rightmost array index
• d’LENGTH : Returns vector size
• d’RANGE : Returns vector range
• d’REVERSE_RANGE: Returns vector range
in reverse order
167. Example
Consider the following signal:
SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
Then:
d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0,
d'LENGTH=8, d'RANGE=(7 downto 0),
d'REVERSE_RANGE=(0 to 7)
168. If the signal is of enumerated type, then:
• d’VAL(pos) : Returns value in the position
specified
• d’POS(value) : Returns position of the
value specified
• d’LEFTOF(value) : Returns value in the
position to the left of the value specified
• d’VAL(row, column) : Returns value in the
position specified; etc
There is little or no synthesis support for
enumerated data type attributes
169. Signal Attributes
Let us consider a signal s
Then:
• s’EVENT : Returns true when an event occurs
on s
• s’STABLE : Returns true if no event has
occurred on s
• s’ACTIVE : Returns true if s = ‘1’
• s’QUIET <time> : Returns true if no event has
occurred during the time specified
• s’LAST_EVENT : Returns the time elapsed since last
event
• s’LAST_ACTIVE: Returns the time elapsed since
last s=‘1’
• s’LAST_VALUE : Returns the value of s before the
last event; etc.
170. Example
All four assignments shown below are synthesizable
and equivalent. They return TRUE when an event (a
change) occurs on clk, AND if such event is upward
(in other words, when a rising edge occurs on clk)
IF (clk'EVENT AND clk='1')... -- EVENT attribute
-- used with IF
IF (NOT clk'STABLE AND clk='1')... -- STABLE
--attribute used
-- with IF
WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT
--attribute used
-- with WAIT
IF RISING_EDGE(clk)... -- call to a function
171. User-defined Attributes
• VHDL also allows the construction of user-defined
attributes
• To employ a user-defined attribute, it must be
declared and specified
Attribute Declaration:
ATTRIBUTE attribute_name: attribute_type ;
Attribute Specification:
ATTRIBUTE attribute_name OF target_name: class IS value;
where:
attribute_type: any data type (BIT, INTEGER, STD_LOGIC_VECTOR, etc.)
class: TYPE, SIGNAL, FUNCTION, etc.
value: ‘0’, 27, ‘‘00 11 10 01’’, etc.
173. Generics
• As the name suggests, GENERIC is a way
of specifying a generic parameter
• a static parameter that can be easily
modified and adapted to different
applications
• The purpose is to make the code more
flexible and reusable
• must be declared in the ENTITY
• More than one GENERIC parameter can
be specified in an ENTITY
174. Syntax
GENERIC (parameter_name : parameter_type := parameter_value);
The GENERIC statement below specifies a parameter called n, of type
INTEGER, whose default value is 8. Therefore, whenever n is found in
the ENTITY itself or in the ARCHITECTURE (one or more) that follows,
its value will be assumed to be 8
ENTITY my_entity IS
GENERIC (n : INTEGER := 8; vector: BIT_VECTOR := "00001111");
PORT (...);
END my_entity;
ARCHITECTURE my_architecture OF my_entity IS
...
END my_architecture;
Example
175. ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
....
Example
176. Delays in VHDL
• In VHDL, there are three types of delay
that are encountered
– Inertial delay
– Transport delay
– Delta delay
177. Inertial Delay
• Inertial delay is the default in VHDL
• Behaves similarly to the actual device
• Output signal of the device has inertia,
which must be overcome for the signal to
change value
• The inertial delay model is by far the most
commonly used in all currently available
simulators
178. Inertial delay prevents prolific propagation of
spikes throughout the circuit
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY buf IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END buf;
ARCHITECTURE buf OF buf IS
BEGIN
b <= a AFTER 20 ns;
END buf;
Due to inertial delay pulse is
swallowed up
179. Transport Delay
• It represents a wire delay in which any
pulse, no matter how small, is propagated
to the output signal delayed by the delay
value specified
• Especially useful for modeling delay line
devices, wire delays on a PCB, and path
delays on an ASIC
180. LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY delay_line IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END delay_line;
ARCHITECTURE delay_line OF delay_line IS
BEGIN
b <= TRANSPORT a AFTER 20 ns;
END delay_line;
Pulse is simply delayed
181. Delta delay
• These are used since the PC that
processes and simulates a concurrent
phenomenon is basically a sequential
machine
• The simulation program mimics
concurrency by scheduling events in some
order
• Simulation deltas are used to order some
types of events during a simulation
• Specifically, zero delay events must be
ordered to produce consistent results
182. Circuit that shows the difference!
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
D
Zero delay components
CLK=‘1’
A=‘1’
Assumptions
183. Problem when no delta delay concept is used
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
1) A becomes 0
2) Evaluate inverter
3) B <= 1
4) Evaluate AND with C=1
5) D<=1
6) Evaluate NAND
7) C<=0CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
8) Evaluate AND
9) D<=0
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
D
Unwanted D assertion
DD
184. Problem when no delta delay concept is used
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
DD
1) A becomes 0
2) Evaluate inverter
3) B <= 1
4) Evaluate NAND
5) C<=0
6) Evaluate AND
7) D<=0
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
D
CLK
D
E
Q'
Q
DFF
CLK
A
B
C
F
185. Delta delay use
Delta 1
Delta 2
Delta 3
Delta 4
10 ns
11 ns
A<=0
Evaluate inverter
B<=0
Evaluate AND
Evaluate NAND
D<= 1
C<=0
Evaluate AND
D<= 0
To summarize, simulation deltas are
an infinitesimal amount of time
used as a synchronization
mechanism when 0 delay events are
present.
187. Combinational vs. Sequential Logic
The output of the circuit
depends solely on the
current inputs
Output does depend on
previous inputs hence
storage elements are
required
Combinational Logic
outputinput
Storage
Elements
Present
State
Next
State
Combinational Logic outputinput
188. Concurrent Code
• Consider the following
statement:
X = X + Y ;
In conventional software
X and Y are register
locations hence contents
of X and Y are added and
stored in X
Register X Register Y
+
189. Difference in VHDL
• In VHDL the same statement will mean a
feedback in a purely combinational logic which is
invalid
+
X Y
190. • VHDL code is inherently concurrent (parallel)
• Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential
• Concurrent code is also called dataflow code
• Order does not matter
• We can only build combinational logic circuits
with concurrent code
• Concurrent assignment produces one driver for
each assignment statement
z <= a;
a z
191. Multiple driver assignment
architecture ABC of XYZ is
signal z,a,b,c,d : std_logic ;
begin
z <= a and b;
z <= c and d;
. . .
?
a
b
c
d
z
Care has to be taken
to handle such conditions
with a hi-impedance state
194. Types of concurrent constructs
• when … else
• with … select
These constructs need not be in the process
195. when…else
• A concurrent statement which assigns one of
several expressions to a signal, depending on the
values of Boolean conditions which are tested in
sequence
• Equivalent to a process containing an if statement
Syntax
[Label:] Target <= [Options]
Expression [after TimeExpression] when Condition
else
Expression [after TimeExpression] when Condition
else
...
Expression [after TimeExpression] [when Condition];
196. Where to use ?
architecture – begin – HERE - end
block – begin – HERE - end
generate – begin – HERE - end
Rules:
• The reserved word guarded may only appear in a
signal assignment within a guarded block. A
guarded assignment only executes when the
guard expression on the surrounding block is
true
• An Expression on the right hand side may be
replaced by the reserved word “unaffected”
197. Synthesis
• Conditional signal assignments are synthesized to
combinational logic
• The Expressions on the right hand side are multiplexed
onto the Target signal
• The resulting logic will be priority encoded, because the
conditions are tested in sequence
Remarks:
• Conditional and selected signal assignments are a
concise way to describe combinational logic in
Register Transfer Level descriptions, although
processes can be easier to read and maintain in some
cases
• A conditional assignment is a neat way to convert from
a Boolean condition to the type Std_logic
198. Example
z <= a when s1=‘1’
else
b when s2=‘1’
else
c ;
c
b
a
s2
s1
z
MUX21
MUX21
200. with…select
• A concurrent statement which assigns
one of several expressions to a signal,
depending on the value of the expression at
the top.
• Equivalent to a process containing a case
statement
Syntax
[Label:] with Expression select
Target <= [Options]
Expression [after TimeExpression] when Choices,
Expression [after TimeExpression] when Choices,
Expression when others;
201. Where to use ?
architecture – begin – HERE – end
block – begin – HERE – end
generate – begin – HERE – end
Rules:
• Every case of the Expression at the top must be
covered once and only once by the choices
• An Expression on the right hand side may be
replaced by the reserved word “unaffected”
• All possible choices must be enumerated
• “others” clause is important since we have 9-
valued logic
202. Synthesis
• Selected signal assignments are
synthesized to combinational logic
• The Expressions on the right hand side
are multiplexed onto the Target signal
Remarks:
• Conditional and selected signal
assignments are a good way to describe
combinational logic in Register Transfer
Level descriptions
203. Example (Multiplexer)
architecture mux41 of mux is -- Assumptions
begin -- a,b,c,d,z are
with control select -- std_logic
z <= a when “00” , -- control is
b when “01” ,-- std_logic_vector(1 downto 0)
c when “10” ,
d when “11” ,
‘Z’ when others ;
end mux41 ;
control
a
b
c
d
z
MUX41
205. Simple block
• The BLOCK statement, in its simple form,
represents only a way of locally
partitioning the code
• It allows a set of concurrent statements to
be clustered into a BLOCK, with the
purpose of turning the overall code more
readable and more manageable (which
might be helpful when dealing with long
codes)
206. Syntax
label: BLOCK
[declarative part]
BEGIN
(concurrent statements)
END BLOCK label;
ARCHITECTURE example
...
BEGIN
...
block1: BLOCK
BEGIN
...
END BLOCK block1 ;
...
block2: BLOCK
BEGIN
...
END BLOCK block2 ;
...
END example ;
General form of
architecture using
block for partitioning
207. • Block can be nested inside another block
Syntax
label1: BLOCK
[declarative part of top block]
BEGIN
[concurrent statements of top block]
label2: BLOCK
[declarative part nested block]
BEGIN
(concurrent statements of nested block)
END BLOCK label2;
[more concurrent statements of top block]
END BLOCK label1;
208. Guarded block
• A guarded BLOCK is a special kind of
BLOCK, which includes an additional
expression, called guard expression
• A guarded statement in a guarded BLOCK is
executed only when the guard expression is
TRUE
Syntax
label: BLOCK (guard expression)
[declarative part]
BEGIN
(concurrent guarded and unguarded statements)
END BLOCK label;
209. • Even though only concurrent statements
can be written within a BLOCK, with a
guarded BLOCK even sequential circuits
can be constructed
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY latch IS
PORT (d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END latch;
ARCHITECTURE latch OF latch IS
BEGIN
b1: BLOCK (clk='1')
BEGIN
q <= GUARDED d;
END BLOCK b1;
END latch;
Latch
210. LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END DFF;
ARCHITECTURE DFF OF DFF IS
BEGIN
b1: BLOCK (clk’EVENT AND clk='1')
BEGIN
q <= GUARDED ‘0’ WHEN rst=‘1’ ELSE d;
END BLOCK b1;
END DFF;
Here, a positive-edge sensitive D-type flip-flop, with synchronous
reset, is designed.
In it, clk'EVENT AND clk='1' is the guard expression, while
q <= GUARDED '0‘ WHEN rst='1' is a guarded statement. Therefore,
q<='0' will occur when the guard expression is true and rst is ‘1’
DFF
212. For ALU in problem 2
sel Operation Function Unit
0000 y <= a Transfer a
Arithmetic
0001 y <= a+1 Increment a
0010 y <= a-1 Decrement a
0011 y <= b Transfer b
0100 y <= b+1 Increment b
0101 y <= b-1 Decrement b
0110 y <= a + b Add a and b
0111 y <= a + b + cin Add a and b with carry
1000 y <= NOT a Complement a
Logic
1001 y <= NOT b Complement b
1010 y <= a AND b AND
1011 y <= a OR b OR
1100 y <= a NAND b NAND
1101 y <= a NOR b NOR
1110 y <= a XOR b XOR
1111 y <= a XNOR b XNOR
213. 3) Priority Encoder
The circuit must encode the address of the input bit of
highest order that is active. ‘‘000’’ should indicate that
there is no request at the input (no bit active)
217. Component
• A component is analogous to a chip socket; it gives an
indirect way to use one hierarchical block within another
• A component is instantiated within an architecture, and
is associated with a (lower level) entity and architecture
during elaboration using information from a
configuration.
• A component declaration is similar in form to an entity
declaration, in that it includes the required ports and
parameters of the component
• The difference is that it refers to a design described in a
separate VHDL file
• The ports and parameters in the component declaration
may be a subset of those in the component file, but they
must have the same names
220. Syntax :
COMPONENT component_name
GENERIC ( parameter_name : string := default_value ;
parameter_name : integer := default_value);
PORT (input_name, input_name : IN STD_LOGIC;
bidir_name, bidir_name : INOUT STD_LOGIC;
output_name, output_name : OUT STD_LOGIC);
END COMPONENT;
Where :
package - <HERE> - end
architecture - is - <HERE> - begin - end
block - <HERE> - begin - end
generate - <HERE> - begin - end
221. Rules:
• For default configuration, the component
name must match the name of the
corresponding entity to be used in its
place, and generics and ports must also
match in name, mode and type
Synthesis:
• A component without a corresponding
design entity is synthesized as a black
box
In VHDL'93, components are not necessary. It is
possible instead to directly instantiate an entity
within an architecture.
222. Example
component Counter
generic (N: INTEGER);
port (Clock, Reset, Enable: in Std_logic;
Q: buffer Std_logic_vector (N-1 downto 0));
end component ;
223. Instantiation
• A concurrent statement used to define the
design hierarchy by making a copy of a
lower level design entity within an
architecture
• In VHDL'93, a direct instantiation of an
entity bypasses the component and
configuration
224. Syntax:
InstanceLabel: [component] ComponentName
[GenericMap] [PortMap];
InstanceLabel: entity
EntityName[(ArchitectureName)]
[GenericMap] [PortMap];
InstanceLabel: configuration ConfigurationName
[GenericMap] [PortMap];
Where:
architecture – begin - <HERE> - end
block – begin - <HERE> - end
generate – begin - <HERE> - end
225. Rules:
• An entity, architecture or configuration
must be compiled into a library before the
corresponding instance can be compiled
• However, an instance of a component can
be compiled before the corresponding
design entity has even been written
Example :
G1: NAND2 generic map (1.2 ns)
port map (N1, N2, N3);
G2: entity WORK.Counter(RTL)
port map (Clk, Rst, Count);
226. Generic Map
• Used to define the values of generics
• Usually given in an Instance, but may also
appear in a configuration
Syntax
generic map ([Formal =>] Actual, ...)
Formal = {either} Name FunctionCall
Actual = Expression
227. Where :
Label : ComponentName <HERE> port map (…);
for - use - <HERE> port map (…)
block – generic (…); <HERE> ; port – begin - end
Rules :
The two forms of syntax (ordered list or
explicitly named choices) can be mixed, but the
ordered list must come before the named choices
A generic map does not end with a semicolon!
228. Example:
architecture Structure of Ent is
component NAND2
generic (TPLH, TPHL: TIME := 0 NS);
port (A, B: in STD_LOGIC;
F : out STD_LOGIC);
end component;
begin
G1: NAND2 generic map (1.9 NS, 2.8 NS)
port map (N1, N2, N3);
G2: NAND2 generic map (TPLH => 2 NS, TPHL => 3 NS)
port map (N4, N5, N6);
end Structure;
229. Port Map
• A port map is typically used to define the
interconnection between instances in a
structural description (or netlist)
• A port map maps signals in an
architecture to ports on an instance within
that architecture
• Port maps can also appear in a
configuration or a block
230. Syntax:
port map ([Formal =>] Actual, ...);
Formal = {either} Name FunctionCall
Actual = {either} Name FunctionCall open
Where:
Label : ComponentName generic map (…) <HERE>;
for - use - generic map (…) <HERE>;
block - port (…) ; <HERE>; - begin - end
231. Rules:
• The two forms of syntax (ordered list or explicitly named
ports) can be mixed, but the ordered list must come
before the named ports
• Within an instance, the formals are ports on the
component or entity being instanced, the actuals are
signals visible in the architecture containing the instance
• Within a configuration, the formals are ports on the
entity, the actuals are ports on the component
• If the actual is a conversion function, this is called
implicitly as values are passed in
• If the formal is a conversion function, this is called
implicitly as values are passed out
Use the port names rather than order to improve readability and
reduce the risk of making connection errors
232. Example:
component COUNTER
port (CLK, RESET: in Std_logic;
UpDown: in Std_logic := '0';-- default value
Q: out Std_logic_vector(3 downto 0));
end component;
...
-- Positional association...
G1: COUNTER port map (Clk32MHz, RST, open, Count);
-- Named association (order doesn't matter)...
G2: COUNTER port map ( RESET => RST,
CLK => Clk32MHz,
Q(3) => Q2MHz,
Q(2) => open, -- unconnected
Q(1 downto 0) => Cnt2,
UpDown => open);
233. Top Level Entity and Lower Level Entity
TOP LEVEL ENTITY
Clk32MHz Q2MHz
Cnt2
RST
COUNT
COUNTER
(LOWER LEVEL ENTITY)
CLK
RESET
Q
Updown
235. A still simpler example
entity ND4 is
port (in1,in2,in3,in4 : in std_logic ;
z : out std_logic);
end ND4;
architecture ND4_CI of ND4 is
component ND2
port (a , b : in std_logic;
c : out std_logic);
end component ;
signal temp1, temp2 : std_logic;
begin
U1 : ND2 port map (a => in1 , b => in2 , c => temp1);
U2 : ND2 port map (a => in3 , b => in4 , c => temp2);
U3 : ND2 port map (a => temp1 , b => temp2 , c => z);
end ND4_CI ;
237. Generate statement
• A concurrent statement used to create
regular structures or conditional structures
during elaboration
• Used to create multiple copies of
components , processes or blocks
• It provides a compact description of
regular structures such as memories ,
registers and counters
238. • Two flavours of generate statement are:
– for … generate
• Number of copies is determined by a discrete
range
– if … generate
• Zero or one copy is made conditionally
• Range must be a computable integer in any
of the following forms:
– integer_expression to integer_expression
– integer_expression downto integer_expression
– Each integer_expression evaluates to an integer
239. Syntax :
Label: for ParameterName in Range generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Label: if Condition generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
240. Where:
architecture – begin - <HERE> - end
block – begin - <HERE> - end
generate – begin - <HERE> - end
Rules :
• The Range and Condition must both be
static, i.e. they cannot include signals
• The Label at the beginning of the generate
statement cannot be omitted
Synthesis:
• Synthesis is straightforward, but not all
synthesis tools support generate!
241. Example:
architecture ABC of full_add4 is
component full_add
port (PA , PB , PC : in std_logic ;
PCOUT , PSUM : out std_logic) ;
end component ;
signal c: std_logic_vector(4 downto 0);
begin
c(0) <= cin ; -- cin is declared in entity
GK : for k in 3 downto 0 generate
FA :full_add port map(A(k),B(k),C(k),C(k+1),SUM(k);
end generate GK ;
cout <= c(4) ; -- cout is declared in entity
end ABC ;
243. architecture SHIFTER_ARCH of SHIFTER is
component DFF
port (D , CLK : in std_logic ;
Q : out std_logic) ;
end component ;
begin
GK : for k in 0 to 3 generate
GK0 : IF k=0 generate
DFILPFLOP : DFF port map (count , clock , Q(k));
end generate GK0 ;
GK1_3 : if k > 0 generate
DFILPFLOP : DFF port map (Q(k-1), clock , Q(k));
end generate GK1_3 ;
end generate GK ;
end SHIFTER_ARCH ;
Another example
245. Ways to describe a circuit!
• Three types of descriptions possible with
VHDL
– Structural
– Dataflow
– Behavioral
246. Structural Method
• At the structural level, which is the lowest level, you
have to first manually design the circuit.
• Use VHDL to specify the components and gates that
are needed by the circuit and how they are
connected together by following your circuit exactly
• Synthesizing a structural VHDL description of a
circuit will produce a netlist that is exactly like your
original circuit
• The advantage of working at the structural level is
that you have full control as to what components are
used and how they are connected.
• But you need to first come up with the circuit and so
the full capabilities of the synthesizer are not utilized
247. Dataflow Method
• At the dataflow level, you use the built-in logical
functions of VHDL in signal assignment statements
to describe a circuit, which again you have to first
design manually
• Boolean functions that describe a circuit can be
easily converted to signal assignment statements
using the built-in logical functions
• The only drawback is that the built-in logical
functions such as the AND and OR function only
take two operands. This is like having only 2-input
gates to work with !
All the statements use in the structural and dataflow
level are executed concurrently
248. Behavioral Method
• Describing a circuit at the behavioral level is
most similar to writing a computer program
• You have all the standard high-level
programming constructs such as the FOR
LOOP, WHILE LOOP, IF THEN ELSE,
CASE, and variable assignments
• The statements are enclosed in a process
block and are executed sequentially
249. Example
BCD to 7- segment display decoder
a
b
c
d
e
f
g
BCD to 7-segment
display decoder
I3
I2
I1
I0
segs(6) {seg 'a'}
segs(5) {seg 'b'}
segs(4) {seg 'c'}
segs(3) {seg 'd'}
segs(2) {seg 'e'}
segs(1) {seg 'f'}
segs(0) {seg 'g'}
251. Logic Equations
2 1 0
3 1 2 0
'
'
2 1 0
' ' ' ' '
1 0 2 0 2 1 2 1 0
' ' '
1 0 2 0
' ' ' '
3 2 1 2 0 1 0
'
3 2 1 1 0
( )
( )
( )
a I I I I
b I I I
c I I I
d I I I I I I I I I
e I I I I
f I I I I I I I
g I I I I I
= + +
= +
= + +
= + + +
= +
= + + +
= + ⊕ +
253. Structural VHDL description
ENTITY myxnor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myxnor2;
ARCHITECTURE Dataflow OF myxnor2 IS
BEGIN
o <= not(i1 XOR i2);
END Dataflow;
ENTITY myxor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myxor2;
ARCHITECTURE Dataflow OF myxor2 IS
BEGIN
o <= i1 XOR i2;
END Dataflow;
ENTITY myand2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myand2;
ARCHITECTURE Dataflow OF myand2 IS
BEGIN
o <= i1 AND i2;
END Dataflow;
254. ENTITY myand3 IS PORT(i1, i2, i3: IN BIT; o: OUT BIT);
END myand3;
ARCHITECTURE Dataflow OF myand3 IS
BEGIN
o <= (i1 AND i2 AND i3);
END Dataflow;
ENTITY myor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myor2;
ARCHITECTURE Dataflow OF myor2 IS
BEGIN
o <= i1 OR i2;
END Dataflow;
ENTITY myor3 IS PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END myor3;
ARCHITECTURE Dataflow OF myor3 IS
BEGIN
o <= i1 OR i2 OR i3;
END Dataflow;
255. ENTITY myor4 IS PORT(i1, i2, i3, i4: IN BIT; o: OUT BIT);
END myor4;
ARCHITECTURE Dataflow OF myor4 IS
BEGIN
o <= i1 OR i2 OR i3 OR i4;
END Dataflow;
ENTITY inv IS PORT (i: IN BIT; o: OUT BIT);
END inv;
ARCHITECTURE Dataflow OF inv IS
BEGIN
o <= not i;
END Dataflow;
256. LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd IS PORT(i0, i1, i2, i3: IN BIT;
a, b, c, d, e, f, g: OUT BIT);
END bcd;
ARCHITECTURE Structural OF bcd IS
COMPONENT inv PORT (i: IN BIT ;o: OUT BIT);
END COMPONENT;
COMPONENT myand2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myand3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor4 PORT(i1, i2, i3, i4: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myxnor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myxor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
257. SIGNAL j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z: BIT;
BEGIN
U1: INV port map(i2,j);
U2: INV port map(i1,k);
U3: INV port map(i0,l);
U4: myXNOR2 port map(i2, i0, z);
U5: myOR3 port map(i3, i1, z, a);
U6: myXNOR2 port map(i1, i0, y);
U7: myOR2 port map(j, y, b);
U8: myOR3 port map(i2, k, i0, c);
U9: myAND2 port map(i1, l, x);
U10: myAND2 port map(j, l, w);
U11: myAND2 port map(j, i1, v);
U12: myAND3 port map(i2, k, i0, t);
U13: myOR4 port map(x, w, v, t, d);
U14: myAND2 port map(i1, l, s);
U15: myAND2 port map(j, l, r);
U16: myOR2 port map(s, r, e);
U17: myAND2 port map(i2, k, q);
U18: myAND2 port map(i2, l, p);
U19: myAND2 port map(k, l, o);
U20: myOR4 port map(i3, q, p, o, f);
U21: myXOR2 port map(i2, i1, n);
U22: myAND2 port map(i1, l, m);
U23: myOR3 port map(i3, n, m, g);
END Structural;
258. Dataflow VHDL description
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd IS PORT (
I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Segs: OUT std_logic_vector (1 TO 7));
END bcd;
ARCHITECTURE Dataflow OF bcd IS
BEGIN
Segs(1) <= I(3) OR I(1) OR NOT (I(2) XOR I(0)); -- seg a
Segs(2) <= (NOT I(2)) OR NOT (I(1) XOR I(0)); -- seg b
Segs(3) <= I(2) OR (NOT I(1)) OR I(0); -- seg c
Segs(4) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)) -- seg d
OR (NOT I(2) AND I(1)) OR (I(2) AND NOT I(1) AND I(0));
Segs(5) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)); -- seg e
Segs(6) <= I(3) OR (I(2) AND NOT I(1)) -- seg f
OR (I(2) AND NOT I(0)) OR (NOT I(1) AND NOT I(0));
Segs(7) <= I(3) OR (I(2) XOR I(1)) OR (I(1) AND NOT I(0)); -- seg g
END Dataflow;
259. Behavioral VHDL description
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BCD is
port( I : in STD_LOGIC_VECTOR(3 downto 0);
segs : out STD_LOGIC_VECTOR(6 downto 0) );
end BCD;
architecture Behavioral of BCD is
begin
with I select
Segs <= "1111110" when "0000",
"0110000" when "0001",
"1101001" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1110011" when "1001",
"0000000" when others;
end Behavioral;
261. Equations for carry_generate(G) and
carry_propagate(P) for ALU 74181
Carry Lookahead Logic
xi
yi
xi-1
x0
yi-1
y0
c0
ci
hsi
si
gi= xi . yi
pi=xi + yi
ci+1= gi + pi . ci
Assignment No 3
267. Sequential Statements
• VHDL code is inherently concurrent
• Sections of code that are executed
sequentially are :
– PROCESS
– FUNCTION
– PROCEDURE
• One important aspect of sequential code is that it is
not limited to sequential logic
• We can build sequential circuits as well as
combinational circuits
• Sequential code is also called behavioral code
• Thus a PROCESS is a concurrent statement which
describes behaviour
268. • Sequential statements are allowed only
inside PROCESSES, FUNCTIONS, or
PROCEDURES
• Sequential statements are:
– IF
– WAIT
– CASE
– LOOP
• VARIABLES are also restricted to be used
in sequential code only
VARIABLE can never be global, so its value
can not be passed out directly
269. SIGNALS and VARIABLES revisited !
• VHDL has two ways of passing non-static values around:
by means of a SIGNAL or by means of a VARIABLE
• A SIGNAL can be declared in a PACKAGE, ENTITY or
ARCHITECTURE (in its declarative part), while a
VARIABLE can only be declared inside a piece of
sequential code
• SIGNAL is global while VARIABLE is local
• The value of a VARIABLE can never be passed out of
the PROCESS directly; if necessary, then it must be
assigned to a SIGNAL
• Update of VARIABLE is immediate whereas new value
for SIGNAL is generally only guaranteed to be available
after the conclusion of the present run of the PROCESS
• Assignment operator for SIGNAL is “<= “ while that for
VARIABLE is “ : = “
270. Process
• A PROCESS is a sequential section of
VHDL code
• It is characterized by the presence of IF,
WAIT, CASE, or LOOP, and by a
sensitivity list (except when WAIT is used)
• A PROCESS must be installed in the main
code, and is executed every time a signal
in the sensitivity list changes (or the
condition related to WAIT is fulfilled)
271. Syntax
[label:] [postponed] PROCESS (sensitivity list)
[VARIABLE name type [range] [:= initial_value;]]
BEGIN
(sequential code)
END [postponed] PROCESS [label];
entity - begin - <HERE> - end
architecture - begin - <HERE> - end
block - begin - <HERE> - end
generate - begin - <HERE> - end
Where “POSTPONED”
is a reserved
VHDL word
272. Rules
• A process must contain either a sensitivity
list or wait statements, but not both
• Every process executes once during
initialization, before simulation starts
• A postponed process is not executed until
the final simulation cycle of a particular
simulation time, and thus sees the stable
values of signals and variables
A process with neither a sensitivity list nor a wait
will loop forever !
273. • To construct a synchronous circuit,
monitoring a signal (clock, for example) is
necessary
• A common way of detecting a signal change
is by means of the EVENT attribute
• For instance, if clk is a signal to be
monitored, then clk ’ EVENT returns TRUE
when a change on clk occurs (rising or
falling edge)
Using EVENT attribute
274. IF construct
• A sequential statement which executes one
branch from a set of branches dependent
upon the conditions, which are tested in
sequence
Syntax
[Label:] if Condition then
SequentialStatements...
[elsif Condition then
SequentialStatements...]
... {any number of elsif parts}
[else
SequentialStatements...]
end if [Label];
Be careful about the spelling of elsif and end if
275. Synthesis
• Assignments within if statements generally
synthesize to multiplexers
• Incomplete assignments, where outputs remain
unchanged for certain input conditions,
synthesize to transparent latches in unclocked
processes, and to flip-flops in clocked
processes
• In some circumstances, nested if statements
synthesize to multiple logic levels. This can be
avoided by using a case statement instead
276. • A set of elsif branches can be used to
impart priority to the conditions tested first
• To decode a value without giving priority to
certain conditions, use a case statement
instead
Example
IF (x<y) THEN temp:="11111111";
ELSIF (x=y AND w='0') THEN
temp := "11110000";
ELSE temp:=(OTHERS =>'0');
277. D Flip-Flop with asynchronous reset
• A D-type flip-flop is the most basic building block
in sequential logic circuits. In it, the output must
copy the input at either the positive or negative
transition of the clock signal (rising or falling
edge)
If rst = ‘1’, then the output
must be q = ‘0’ ,regardless of
the status of clk.
Otherwise, the output must
copy the input (that is, q = d)
at the positive edge of clk
