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EMBEDDED SYSTEMS
Eng : Hatem Abd El-Salam
INTRODUCTION 1
COMPUTER
• The computer is device that I write a code on it and it is doing an operation
Component:
 Processor
 Memory
 IO
Processor
IO Memory
EMBEDDED SYSTEMS
• Embedded systems is computing system have
 Processor
 Memory
 IO
• But minimal specification because it has one job
• It is two ways to impalement Embedded systems
 System On Chip (SOC)
 System Board (SB)
SOC SB
Performance The same The same
Cost Cheaper Costly
Power consumption lower higher
size smaller bigger
SOC VS SB
• Microcontroller is a SOC.
MICROPROCESSOR VS MICROCONTROLLER
MICRO-CONTROLLER
• Basically a microcontroller can be described as a computer on a chip. a
single chip containing a CPU, non-volatile memory (RAM), volatile
memory(ROM), a timer and an I/O control unit.
• A microcontroller apart from the above mentioned components usually also
include serial communication capabilities, interrupt controls and analog I/O
capabilities.
• Used for a few dedicated functions determined by the system designer.
MICRO-CONTROLLER
• Microcontrollers don’t work alone in the circuit it must interfaces with other on
chip devices like Sensors, Switches, Leds, LCD, Keypad and DC Motor
• Microcontroller can accept inputs from some components and provide outputs
to other components within any given system.
• Differences in requirements, make the manufacturers produce different
microcontrollers with different memory sizes, number of I/O lines and number
of integrated peripheral devices. Other wise they are all similar to use.
MICRO-PROCESSOR
• Just a CPU has to add externally memory, clock, input/output interfaces, timer
and all other needed peripheral. This is the reason a microprocessor has so
many pins.
• The difference between a microcontroller and a microprocessor is that the
microprocessor is a general purpose computer while a microcontroller is a
computer dedicated to one or just a few tasks.
It contains :
 Control Unit (CU)
 the Arithmetic Logic Unit (ALU)
 Instruction Decoder and some Special Registers
MICRO-PROCESSOR
• Microprocessor function: is to fetch the instructions from the memory then
decode and execute them.
• Example:
• CPU=ALU + Registers + Control unit
• Microprocessor alone is useless
MICRO-PROCESSOR
Control Unit:
• The control unit is the circuitry that controls the flow of data through the
processor, and coordinates the activities of the other units within it.
• In other word it is in charge of the entire Instruction (Machine) cycle
MICRO-PROCESSOR
Arithmetic Logic Unit :
• An ALU is an integrated circuit within CPU or GPU that performs arithmetic and logic
operations.
• Arithmetic instructions include:
 Addition
 Subtraction
 shifting operations
• Logic instructions include:
 AND
 OR
 XOR
 NOT operations
CPU Registers
• Program Counter
(PC)
• Instruction
Register (IR)
• Instruction
Decoder (ID)
• Stack Pointer
(SP)
• Status Register
(SREG)
• Index Registers
(X,Y)
• Accu. Registers
(A,B)
• General Purpose
Registers (GPR)
(R0, R1,
……R31)
Internal Buses
• Data Bus
• Address Bus
• Control Lines
CPU Architectures
• Harvard
• Von Neumann
Instruction Sets
• CISC
• RISC
CPU Registers
• Program Counter
(PC)
• Instruction
Register (IR)
• Instruction
Decoder (ID)
• Stack Pointer
(SP)
• Status Register
(SREG)
• Index Registers
(X,Y)
• Accu. Registers
(A,B)
• General Purpose
Registers (GPR)
(R0, R1,
……R31)
Internal Buses
• Data Bus
• Address Bus
• Control Lines
CPU Architectures
• Harvard
• Von Neumann
Instruction Sets
• CISC
• RISC
PROGRAM COUNTER (PC)
• Most important CPU register
• Holds the address of the next instruction in program memory space
• The size (width) of the program counter is directly related to the size of the
μC’s program memory
INSTRUCTION REGISTER (IR)
• Contains the next instruction (Op-Code) to be decoded by the Instruction
Decoder.
INSTRUCTION DECODER (ID)
• Takes Op-Code stored in the instruction register and decodes it then tells the
CPU what to do for it and enable the components for this operation
STACK POINTER (SP)
• The stack pointer is basically a register that holds either:
 "the memory address of the last location on that stack where data are stored“ or
 "the memory address of the next available location on the stack to store data"
• The definition depends on the design of the μC
STATUS REGISTER (SREG)
• Contains flags represent the status of the last operation to control the following instructions
• Flags as:
 Overflow flag
o Indicates that the result is too large to fit in the register width.
 Negative flag
o Indicates that the result is negative
 Zero flag
o Indicates that the result was zero.
 Carry flag
o Indicates a carry in the last arithmetic or logical operation
 Half-carry flag
o Indicates that a bit carry was produced between the 4-bit halves of a byte operand as a result of the last arithmetic
operation
 Global Interrupt mask
INDEX REGISTERS
• Index Register : Used in indirect addressing modes, as the accessed
• address = index register + offset mentioned in code
ACCUMULATOR REGISTERS
• An Accumulator is a register in which intermediate arithmetic and logic results
are stored
• Access to main memory is slower than access to a register like the accumulator
because the technology used for the large main memory is slower (but
cheaper) than that used for a register.
GENERAL PURPOSE REGISTERS (GPR)
• General purpose registers are available to store any transient data required
by the program.
• In general the more registers a CPU has available, the faster it can work.
CPU Registers
• Program Counter
(PC)
• Instruction
Register (IR)
• Instruction
Decoder (ID)
• Stack Pointer
(SP)
• Status Register
(SREG)
• Index Registers
(X,Y)
• Accu. Registers
(A,B)
• General Purpose
Registers (GPR)
(R0, R1,
……R31)
Internal Buses
• Data Bus
• Address Bus
• Control Lines
CPU Architectures
• Harvard
• Von Neumann
Instruction Sets
• CISC
• RISC
CPU Registers
• Program Counter
(PC)
• Instruction
Register (IR)
• Instruction
Decoder (ID)
• Stack Pointer
(SP)
• Status Register
(SREG)
• Index Registers
(X,Y)
• Accu. Registers
(A,B)
• General Purpose
Registers (GPR)
(R0, R1,
……R31)
Internal Buses
• Data Bus
• Address Bus
• Control Lines
CPU Architectures
• Harvard
• Von Neumann
Instruction Sets
• CISC
• RISC
DATA BUS
• These are the lines that actually carry the data being transferred
• Wider data buses generally mean higher performance
• The bandwidth of the data bus is how much information can flow through it,
and is a function of the bus width (in bits) and its speed (in MHz)
ADDRESS BUS
• The address bus is the set of lines that carry information about where in
memory the data is to be transferred to or from
• The width of the address bus controls the address ability of the processor,
which is how much system memory the processor can read or write to
• The width of the address and data buses aren't linked
CONTROL LINES
• The control bus carries commands from the CPU and returns status signals
from the devices.
• For example:
 Memory chip READ/WRITE (R/W) lines
 IO device Chip Enable (CE) lines
CPU Registers
• Program Counter
(PC)
• Instruction
Register (IR)
• Instruction
Decoder (ID)
• Stack Pointer
(SP)
• Status Register
(SREG)
• Index Registers
(X,Y)
• Accu. Registers
(A,B)
• General Purpose
Registers (GPR)
(R0, R1,
……R31)
Internal Buses
• Data Bus
• Address Bus
• Control Lines
CPU Architectures
• Harvard
• Von Neumann
Instruction Sets
• CISC
• RISC
HARVARD
• Separate memory areas for program instruction and data
• Two or more internal buses which allow simultaneous access to both instructions
and data
• If the fetched instruction requires an operation on data memory, the CPU can
fetch the next program instruction while it uses the data bus for its data
operation
• Speed up execution time with cost of more hardware complexity
VON NEUMANN
• Has a single common memory space for Data and Program instructions
• Single data bus which fetches both instructions and data
• Each time the CPU fetches a program instruction it may have to perform one
or more read/write operations to data memory space. It must wait until these
subsequent operations are complete before it can fetch and decode the next
program instruction. (Von-Neumann bottleneck)
• The advantage of this architecture lies in its simplicity and economy
HARVARD VS VON NEUMANN
CPU Registers
• Program Counter
(PC)
• Instruction
Register (IR)
• Instruction
Decoder (ID)
• Stack Pointer
(SP)
• Status Register
(SREG)
• Index Registers
(X,Y)
• Accu. Registers
(A,B)
• General Purpose
Registers (GPR)
(R0, R1,
……R31)
Internal Buses
• Data Bus
• Address Bus
• Control Lines
CPU Architectures
• Harvard
• Von Neumann
Instruction Sets
• CISC
• RISC
CISC
• Complex Instruction Set Computer (CISC)
 CISC is an old concepts that dates back when memory access was slow
 CISC aimed to integrate several functionalities in one instruction, in order to limit the
program size, and thus limit memory access in order to gain some speed
 Number of instructions are reduced by having multiple operations within a single
instruction
• Examples: x86, Motorola 68k
RISC
• Reduced Instruction Set Computing (RISC)
 As memory technology developed more and more, memory access became faster
 RISC aims to optimize execution of instructions by limiting the capabilities of a single
instruction and having consistent instructions’ execution time (Instruction Pipelining)
 Large and uniform register file
• Small number of instructions that actually reference memory (e.g. STORE, LOAD)
• All other instructions work on the registers only
 Hardware that helps parallel operations (Harvard architecture)
• Examples: ARM, Atmel AVR, PowerPC
CISC VS RISC
Consider this example:
• This CISC assembly code
clear 0x1000 ; clear memory location 0x1000
• Becomes the following RISC assembly code
xor r1,r1 ; clear register 1
store r1,0x1000 ; clear memory location 0x1000
CISC VS RISC
The Performance Equation:
• The following equation is commonly used for expressing a computer's
performance ability:
 The CISC approach attempts to minimize the number of instructions per program,
sacrificing the number of cycles per instruction.
 RISC does the opposite, reducing the cycles per instruction at the cost of the number of
instructions per program.
introduction to embedded systems part 1

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introduction to embedded systems part 1

  • 1. EMBEDDED SYSTEMS Eng : Hatem Abd El-Salam INTRODUCTION 1
  • 2. COMPUTER • The computer is device that I write a code on it and it is doing an operation Component:  Processor  Memory  IO Processor IO Memory
  • 3. EMBEDDED SYSTEMS • Embedded systems is computing system have  Processor  Memory  IO • But minimal specification because it has one job • It is two ways to impalement Embedded systems  System On Chip (SOC)  System Board (SB)
  • 4. SOC SB Performance The same The same Cost Cheaper Costly Power consumption lower higher size smaller bigger SOC VS SB • Microcontroller is a SOC.
  • 6.
  • 7. MICRO-CONTROLLER • Basically a microcontroller can be described as a computer on a chip. a single chip containing a CPU, non-volatile memory (RAM), volatile memory(ROM), a timer and an I/O control unit. • A microcontroller apart from the above mentioned components usually also include serial communication capabilities, interrupt controls and analog I/O capabilities. • Used for a few dedicated functions determined by the system designer.
  • 8. MICRO-CONTROLLER • Microcontrollers don’t work alone in the circuit it must interfaces with other on chip devices like Sensors, Switches, Leds, LCD, Keypad and DC Motor • Microcontroller can accept inputs from some components and provide outputs to other components within any given system. • Differences in requirements, make the manufacturers produce different microcontrollers with different memory sizes, number of I/O lines and number of integrated peripheral devices. Other wise they are all similar to use.
  • 9. MICRO-PROCESSOR • Just a CPU has to add externally memory, clock, input/output interfaces, timer and all other needed peripheral. This is the reason a microprocessor has so many pins. • The difference between a microcontroller and a microprocessor is that the microprocessor is a general purpose computer while a microcontroller is a computer dedicated to one or just a few tasks. It contains :  Control Unit (CU)  the Arithmetic Logic Unit (ALU)  Instruction Decoder and some Special Registers
  • 10. MICRO-PROCESSOR • Microprocessor function: is to fetch the instructions from the memory then decode and execute them. • Example: • CPU=ALU + Registers + Control unit • Microprocessor alone is useless
  • 11. MICRO-PROCESSOR Control Unit: • The control unit is the circuitry that controls the flow of data through the processor, and coordinates the activities of the other units within it. • In other word it is in charge of the entire Instruction (Machine) cycle
  • 12. MICRO-PROCESSOR Arithmetic Logic Unit : • An ALU is an integrated circuit within CPU or GPU that performs arithmetic and logic operations. • Arithmetic instructions include:  Addition  Subtraction  shifting operations • Logic instructions include:  AND  OR  XOR  NOT operations
  • 13.
  • 14. CPU Registers • Program Counter (PC) • Instruction Register (IR) • Instruction Decoder (ID) • Stack Pointer (SP) • Status Register (SREG) • Index Registers (X,Y) • Accu. Registers (A,B) • General Purpose Registers (GPR) (R0, R1, ……R31) Internal Buses • Data Bus • Address Bus • Control Lines CPU Architectures • Harvard • Von Neumann Instruction Sets • CISC • RISC
  • 15. CPU Registers • Program Counter (PC) • Instruction Register (IR) • Instruction Decoder (ID) • Stack Pointer (SP) • Status Register (SREG) • Index Registers (X,Y) • Accu. Registers (A,B) • General Purpose Registers (GPR) (R0, R1, ……R31) Internal Buses • Data Bus • Address Bus • Control Lines CPU Architectures • Harvard • Von Neumann Instruction Sets • CISC • RISC
  • 16. PROGRAM COUNTER (PC) • Most important CPU register • Holds the address of the next instruction in program memory space • The size (width) of the program counter is directly related to the size of the μC’s program memory
  • 17. INSTRUCTION REGISTER (IR) • Contains the next instruction (Op-Code) to be decoded by the Instruction Decoder.
  • 18. INSTRUCTION DECODER (ID) • Takes Op-Code stored in the instruction register and decodes it then tells the CPU what to do for it and enable the components for this operation
  • 19. STACK POINTER (SP) • The stack pointer is basically a register that holds either:  "the memory address of the last location on that stack where data are stored“ or  "the memory address of the next available location on the stack to store data" • The definition depends on the design of the μC
  • 20. STATUS REGISTER (SREG) • Contains flags represent the status of the last operation to control the following instructions • Flags as:  Overflow flag o Indicates that the result is too large to fit in the register width.  Negative flag o Indicates that the result is negative  Zero flag o Indicates that the result was zero.  Carry flag o Indicates a carry in the last arithmetic or logical operation  Half-carry flag o Indicates that a bit carry was produced between the 4-bit halves of a byte operand as a result of the last arithmetic operation  Global Interrupt mask
  • 21. INDEX REGISTERS • Index Register : Used in indirect addressing modes, as the accessed • address = index register + offset mentioned in code
  • 22. ACCUMULATOR REGISTERS • An Accumulator is a register in which intermediate arithmetic and logic results are stored • Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register.
  • 23. GENERAL PURPOSE REGISTERS (GPR) • General purpose registers are available to store any transient data required by the program. • In general the more registers a CPU has available, the faster it can work.
  • 24. CPU Registers • Program Counter (PC) • Instruction Register (IR) • Instruction Decoder (ID) • Stack Pointer (SP) • Status Register (SREG) • Index Registers (X,Y) • Accu. Registers (A,B) • General Purpose Registers (GPR) (R0, R1, ……R31) Internal Buses • Data Bus • Address Bus • Control Lines CPU Architectures • Harvard • Von Neumann Instruction Sets • CISC • RISC
  • 25. CPU Registers • Program Counter (PC) • Instruction Register (IR) • Instruction Decoder (ID) • Stack Pointer (SP) • Status Register (SREG) • Index Registers (X,Y) • Accu. Registers (A,B) • General Purpose Registers (GPR) (R0, R1, ……R31) Internal Buses • Data Bus • Address Bus • Control Lines CPU Architectures • Harvard • Von Neumann Instruction Sets • CISC • RISC
  • 26.
  • 27. DATA BUS • These are the lines that actually carry the data being transferred • Wider data buses generally mean higher performance • The bandwidth of the data bus is how much information can flow through it, and is a function of the bus width (in bits) and its speed (in MHz)
  • 28. ADDRESS BUS • The address bus is the set of lines that carry information about where in memory the data is to be transferred to or from • The width of the address bus controls the address ability of the processor, which is how much system memory the processor can read or write to • The width of the address and data buses aren't linked
  • 29. CONTROL LINES • The control bus carries commands from the CPU and returns status signals from the devices. • For example:  Memory chip READ/WRITE (R/W) lines  IO device Chip Enable (CE) lines
  • 30. CPU Registers • Program Counter (PC) • Instruction Register (IR) • Instruction Decoder (ID) • Stack Pointer (SP) • Status Register (SREG) • Index Registers (X,Y) • Accu. Registers (A,B) • General Purpose Registers (GPR) (R0, R1, ……R31) Internal Buses • Data Bus • Address Bus • Control Lines CPU Architectures • Harvard • Von Neumann Instruction Sets • CISC • RISC
  • 31. HARVARD • Separate memory areas for program instruction and data • Two or more internal buses which allow simultaneous access to both instructions and data • If the fetched instruction requires an operation on data memory, the CPU can fetch the next program instruction while it uses the data bus for its data operation • Speed up execution time with cost of more hardware complexity
  • 32.
  • 33. VON NEUMANN • Has a single common memory space for Data and Program instructions • Single data bus which fetches both instructions and data • Each time the CPU fetches a program instruction it may have to perform one or more read/write operations to data memory space. It must wait until these subsequent operations are complete before it can fetch and decode the next program instruction. (Von-Neumann bottleneck) • The advantage of this architecture lies in its simplicity and economy
  • 34.
  • 35. HARVARD VS VON NEUMANN
  • 36. CPU Registers • Program Counter (PC) • Instruction Register (IR) • Instruction Decoder (ID) • Stack Pointer (SP) • Status Register (SREG) • Index Registers (X,Y) • Accu. Registers (A,B) • General Purpose Registers (GPR) (R0, R1, ……R31) Internal Buses • Data Bus • Address Bus • Control Lines CPU Architectures • Harvard • Von Neumann Instruction Sets • CISC • RISC
  • 37. CISC • Complex Instruction Set Computer (CISC)  CISC is an old concepts that dates back when memory access was slow  CISC aimed to integrate several functionalities in one instruction, in order to limit the program size, and thus limit memory access in order to gain some speed  Number of instructions are reduced by having multiple operations within a single instruction • Examples: x86, Motorola 68k
  • 38. RISC • Reduced Instruction Set Computing (RISC)  As memory technology developed more and more, memory access became faster  RISC aims to optimize execution of instructions by limiting the capabilities of a single instruction and having consistent instructions’ execution time (Instruction Pipelining)  Large and uniform register file • Small number of instructions that actually reference memory (e.g. STORE, LOAD) • All other instructions work on the registers only  Hardware that helps parallel operations (Harvard architecture) • Examples: ARM, Atmel AVR, PowerPC
  • 39. CISC VS RISC Consider this example: • This CISC assembly code clear 0x1000 ; clear memory location 0x1000 • Becomes the following RISC assembly code xor r1,r1 ; clear register 1 store r1,0x1000 ; clear memory location 0x1000
  • 40. CISC VS RISC The Performance Equation: • The following equation is commonly used for expressing a computer's performance ability:  The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction.  RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.