Low Voltage Ride Through (LVRT) is an important grid requirement for Voltage Source Converter (VSC) based HVDC links. This paper studies the performance of the modular multilevel converter (MMC) VSC based HVDC systems during faults or voltage dips and proposes a new control strategy to improve the LVRT performance. The proposed algorithm controls the system to generate the required active and reactive powers that are calculated mathematically based on the ratings of the MMC-HVDC system and LVRT requirements. The injected active and reactive power values obey the LVRT guidelines and are adaptable to different grid codes. The mathematical calculations are presented and EMTDC/PSCAD simulation evaluates the performance of the proposed method.

1. Low Voltage Ride Through Control of Modular
Multilevel Converter based HVDC systems
Ghazal Falahi
FREEDM Systems Center
Electrical and Computer Engineering Department
North Carolina State University
Raleigh US
Alex Huang
FREEDM Systems Center
Electrical and Computer Engineering Department
North Carolina State University
Raleigh US
Abstract— Low Voltage Ride Through (LVRT) is an important
grid requirement for Voltage Source Converter (VSC) based
HVDC links. This paper studies the performance of the modular
multilevel converter (MMC) VSC based HVDC systems during
faults or voltage dips and proposes a new control strategy to
improve the LVRT performance. The proposed algorithm
controls the system to generate the required active and reactive
powers that are calculated mathematically based on the ratings of
the MMC-HVDC system and LVRT requirements. The injected
active and reactive power values obey the LVRT guidelines and
are adaptable to different grid codes. The mathematical
calculations are presented and EMTDC/PSCAD simulation
evaluates the performance of the proposed method.
Keywords-MMC, HVDC, low voltage ride through
I. INTRODUCTION
Voltage source converter (VSC) based HVDC is a relatively
new type of transmission system incorporating controllable
switching converters. HVDC systems can control active and
reactive power independently therefore they improve power
transfer capability and network stability. With the
development of remote and large renewable energy farms,
VSC HVDC transmission systems are very attractive to
deliver power to demand centers. VSC based HVDC systems
are becoming a competitor of classical thyristor-based HVDC
systems and they may replace the classic HVDC systems one
day [1].
VSC-HVDC systems can produce active and reactive power
independently, which allows them to operate with small or no
AC support. As the power plants increase in size and provide
a larger share of the supply, they should stay operational and
connected to the grid to support the grid by injecting reactive
power during and after voltage sags [2]. When a fault occurs
due to short circuit or any other issue in the grid the voltage
decreases at AC output terminals, which reduces the active
power. The disconnection of a large amount of power may
result in serious power stability problems therefore many grid
codes require the LVRT capability, which infers the system
should be able to supply power to the network even during
grid faults, and voltage sags [2].
Low voltage ride-through also known as fault ride through
(FRT) requirement states that the system should stay
connected when the AC grid voltage is temporarily reduced
due to a fault or large load change in the grid. The voltage may
reduce in one, two or all three phases of the ac grid. Grid
operators define low voltage ride-through (LVRT)
requirement to maintain high availability, stability and to
reduce the risk of voltage collapse [3]. Restraining the power
delivered to the HVDC DC link during voltage sags is a key
point in achieving LVRT requirements. LVRT-capable
systems enrich overall system stability by injecting reactive
power during system events [2-5].
This paper studies the dynamic performance of a transformer-
less MMC-VSC based HVDC system and proposes a LVRT
conforming control technique to improve the performance
during faults or voltage sags. The paper also presents some
mathematical calculations based on LVRT curve and grid
code. The MMC control system is modified based on the
calculations to fulfill the LVRT requirements.
In this paper section II covers MMC mathematical model and
operation principal, part III shows the VSC-HVDC system
diagram and studies MMC-HVDC control, operation and
dynamic performance, part IV proposes a LVRT control
methodology to improve the system performance under faults
and voltage sags. The control diagram is shown and the
PSCAD simulation verifies the performance of the proposed
control method.
II. MMC MATHEMATICAL MODEL AND OPERATION
PRINCIPAL
The three-phase MMC converter configuration used in HVDC
applications is shown in Fig. 1. The converter is composed of
three-phase legs each consisting of two arms made by series
connection of some identical half-bridge modules called cells
or sub-modules (SM). The SMs are inserted or bypassed based
on the switching state of the two switching device in each half
bridge. The two switches are complementary and table 1
shows the sub-module output voltage in different switching
states. The currents in phase-k (k=a, b, c) consist of ik-up and ik-

2. low which are the upper and lower arm current in each phase.
Applying KVL to the arms of the converter yields to the
following:
(1)
(2)
(3)
(4)
Where uk is the phase k voltage, u0 is the potential to ground
DC side neutral point and the inductance of each arm equals
2L. The MMC grid connection dynamic is described as
(5)
Control system for the each MMC converter shown in Fig. 1
includes four parts [6]:
1. An individual capacitor voltage controller, which keeps the
sub module capacitor voltages on their reference values.
2. The averaging controller that controls the total capacitor
voltages in each leg to follow the reference value which is
2Vdc.
3. The system controller, which controls active and reactive
power. The reference of active power is determined by
network demanded active power or the DC-link voltage
controller. The reference for reactive power is either
determined by ac voltage regulator or by the utility issued
reactive power demand.
4. The PWM voltage command generation, which adds up the
output of three mentioned controllers to build the modulation
waveform. The overall control structure is shown in Fig. 4.
The ac voltage command or modulation index for each phase
is calculated by adding the output of three mentioned
controllers as shown in the following equations.
(j:1-n) (6)
(j: n+1 - 2n) (7)
The voltage command is normalized by each dc-capacitor
voltage Vcju and compared with a triangular waveform having a
maximum value of unity and minimum value of zero with a
carrier frequency of fc. Carrier shifted PWM modulation
TABLE I. SWITCHING STATE OF SUB-MODULES
State S1 S2 Vsm
1 ON OFF Vc
2 OFF ON 0
3 OFF OFF 0
Fig. 1: Modular multilevel converter
Fig.2 HVDC MMC single line diagram
technique is used for switching and carrier waveform of each
cell is phase shifted by 360/n [6].
III. HVDC MMC OPERATION PRINCIPAL
The single line diagram of an MMC-HVDC system is shown
in Fig. 2, which consists of two MMC converter stations
connected to the utility grid on one side and to the DC
transmission line on the other side. The DC link voltage in this
system is maintained by the sum of sub-module voltages in the
converter leg and there is no bulky DC link capacitor as in
other VSC-HVDC systems. The two MMC converters can
regulate active and reactive power by changing the amplitude
and phase of the converter line currents with respect to PCC
voltage and there are usually two control loops. The outer
control regulates the power transfer between the AC and DC
systems and the inner or faster controller is responsible for
tracking the generated references by the power control, DC or
AC voltage control loop. MMC 2 is usually the grid side
converter and MMC 1 is the generator side converter. The
main objective of the controller is to keep the DC-link voltage
constant while keeping sinusoidal grid currents.
Cell 2
Cell n
Cell (n+1)
Cell (n+2)
Cell 1
Cell (2n)
DC
link
va
vb
vc
DC
link
u0
ia-up
ia-low
Udc/2
Udc/2
ia
ib
ic
2L
2L
2L 2L
2L 2L
La
Lb
Lc
ib-up ic-up
ib-low ic-low
ua
ub
uc
S1
S2
VS
M
V
c

3. The MMC-HVDC system is simulated to study the effect of
fault and voltage sag. The dynamic performance of the
modeled MMC-HVDC system during active and reactive
power command reversal is shown in Fig. 3. The active power
reversal command is sent at t=0.4 secs and reactive power is
reversed at t=0.5 secs and P1, P2, Q1 and Q2 are plotted. Fig. 4
shows the step change in DC link reference voltage.
Fig. 3 Active and reactive power reversal test
Fig. 4 Step change in DC link voltage
Fig. 5 MMC individual and total capacitor voltage controller
IV. PROPOSED LVRT CONTROL STRUCTURE
As soon as a fault occurs in the MMC-2 AC terminal the
exported active power will reduce significantly according to
the voltage drop. On the other side, generator side continues to
generate the normal active power therefore there is an
enormous amount of energy imbalance. Due to the energy
imbalance the DC-link voltage starts increasing uncontrollably
which will damage both generator and grid side converters [7-
9]. Improved control must be developed to address this issue.
The proposed LVRT control diagram is shown in Fig. 6,
which implements Eq. (8) and LVRT code. In normal
operation reference for active current in the MMC-2 side is
given by system’s demanded active power and DC voltage
controller gives the active current command for MMC-1 side.
On the other hand, the reactive current given/absorbed to/from
the grid is regulated by q component independently and the
reference is specified either by reactive power demand or the
output of the ac voltage regulation controller.
During fault or voltage sag, PCC voltages decrease quickly
and the currents increase due to the energy imbalance in the
HVDC system besides the utility demands to meet the LVRT
requirements. Hence LVRT requirement specifies the
references for active and reactive power in MMC-2 side and
the controller structure changes to avoid system instability,
damage or disconnection.
A voltage vs. time curve defines the demanded low voltage
ride through requirement and represents the minimum required
immunity of the system at point of common coupling (PCC).
Fig. 7 shows a typical LVRT requirement curve, which
consists of four areas; area 1 is a condition where voltage-sag
duration is less than tmin, the voltage magnitude at PCC is equal
or more than Vmin
and the system should remain connected.
Areas 2 and 3 define the voltage recovery specifications. In a
certain time, t1-tmin or t2-t1 if the recovered voltage reaches the
defined levels of v1 and v2 the system should remain
connected. Area 4 states the minimum operational voltage that
system can handle without disconnection for any duration
moreover if voltage is greater than v2
after t2
seconds the
protection should not operate. To summarize, gray area
defines the safe operating area (SOA) of the transmission
system so when PCC voltage is above the curve the system
should remain connected. The voltage levels and time values
may be different in different grid codes [2].
Once the voltage sag is detected, the internal controller
references switch from normal operating condition values to
the commanded values by LVRT requirements. The new
active and reactive power references are found by the LVRT
curve and (8). Fig 8 shows the LVRT curve, based on United
States FERC voltage code for grid fault tmin is 625ms and Vmin
is 0.15 pu. Moreover if the duration of the voltage sag is less
than 150msec and voltages are equal or smaller than 0.15 pu
system should stay connected.
The ratio of required reactive current to the rated current is
defined by (8) according to Fig.8, where vac is the ac voltage.
The numbers in this curve may change based on different grid
codes however the concept stays the same. If fault or voltage
sag is detected in the system and the operating voltage is less
than the defined criteria by the grid code the LVRT controller
changes the active and reactive power references to the values
found by (8) accordingly besides reactive power is injected in
the system to maintain the voltage.
0 0.1 0.2 0.3 0.4 0.5 0.6
-4
-3
-2
-1
0
1
2
time (sec)
P1&P2(pu)
P1
P2
0 0.1 0.2 0.3 0.4 0.5 0.6
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
time (sec)
Q1&Q2(pu)
Q1
Q2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-1
0
1
2
3
4
5
Vdc(pu)
Vdcref
Vdc
PI
Vc*
Vcju
(j=1-2n)
±
-1 :-Ik-up , Ik-low 0
+1 :-Ik-up , Ik-low 0
VBju*
Individual DC voltage controller
PI PI
1/2
Vc*
Vcu
Ik-low
Ik-up
Icir*
Icir
VAu*
Total DC voltage controller

4. Fig. 6 Power controller
vac 0.85 pu
0.5< vac 0.85pu (8)
vac 0.5 pu
An MMC-HVDC system with specifications in Table II is
simulated in PSCAD to evaluate the proposed LVRT
controller. The simulation results for the unmodified typical
controller and the modified controller with LVRT is shown in
Figs. 9 and 11. The fault has been applied in MMC-2 AC side
at t=0.2secs seconds and the AC voltage drops to 0.3 pu for
0.1 secs and return to 1 pu. In MMC VSC there is no
centralized DC link capacitor and sub module capacitors
maintain the DC link voltage, and an additional DC voltage
controller is used in MMC-1 to control the DC link voltage.
The DC link voltage increases by about 30%. When the
proposed LVRT controller is used, the DC link voltage
increase is reduced by about 50% as shown in Fig.11.
TABLE II. MMC-HVDC SYSTEM SPECIFICATIONS
The AC currents in the MMC-2 side are shown in Fig. 9 and
Fig.11 for both cases. With typical control system AC currents
increase to 1.4 pu during the voltage sag however the LVRT
controller limits the AC currents to 1pu. Active and reactive
powers during LVRT control are also shown in Fig.11. When
the voltage drops, the active power is decreased to around 0.1
pu promptly and injected reactive power is boosted to around
0.9 pu to maintain the voltage.
The LVRT profile on Fig. 7 is applied to the MMC-HVDC
system and the three phase voltages, output powers of both
sides and reactive power is plotted in Fig. 10. With regular
power control strategy, the AC currents drop and become
unbalanced after voltage sag is detected. The LVRT controller
commands the system to generate reactive power proportional
to the voltage drop to maintain voltages and active powers are
reduced to avoid overcurrent in the system, which enables the
protection devices. The LVRT controller retains the side one’s
currents during the sag period and maintains the power flow in
the HVDC system.
Fig.7 Low voltage ride through curve
Fig. 8 The required percentage of reactive current during LVRT
I. CONCLUSION
This paper studied the dynamic performance of transformer-
less MMC-HVDC and proposed a LVRT control method for
the grid side converter. The mathematical equations were
derived base on LVRT requirements to indicate the required
reactive power to be injected in the system during the voltage
sag period. The proposed controller changes references
according to derived active and reactive power values form
LVRT control and increases stability by avoiding frequent
disconnection. The simulation results were presented and
compared for both cases, which confirm that incorporating the
proposed control strategy improves the performance of the
MMC-HVDC system.
V*ac
Vmk(k=a,b,c)
PI
i*odref
Vod
iod
PI
i*qref
0Leq
0Leq
ioq
Voq
3dq/abc
System controller
Normal operation
LVRT
Pref
Pref-LVRT
PI
V*dc
Vdc
Q*ref
PI
Vac Qref-LVRT
Voltage
2
3
4
Time
Vmin
tmin t1 t20
V1
V2
Vnom
1
Ireactive/Irated(%)
Voltage(%)
0.2pu
50 85
1pu
105
Normal
operation
Fault
operation
System parameters Values
AC system 138 kV-LL rms
Power 150 MW
Fundamental frequency 60Hz
MMC switching frequency 180Hz
Source inductance Ls 2mH
Arm inductance 7mH
Submodule capacitor 2500uF
DC link voltage 340 KV

5. Fig. 9 System voltages, currents and DC link voltage with typical control,
voltage sag applied at t=0.2 sec
Fig. 10 Dynamic response of the system when LVRT profile in Fig.7 is
applied to MMC-2 side., three phase voltages, active powers and reactive
powers respectively
Fig. 11 System reactive power, currents, DC link voltage and active power
with LVRT control, voltage sag applied at t=0.2 sec
ACKNOWLEDGMENT
This work used ERC shared facilities supported by the
National Science Foundation.
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-2
-1
0
1
2
Time(sec)
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-2
-1
0
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3Phasecurrentsside2(pu)
ia
ib
ic
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1
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Vdc-ref
Vdc
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
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time (sec)
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ia
ib
ic
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
-3
-2
-1
0
1
2
3
time (sec)
P1&P2(pu)
P1
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0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
-1.5
-1
-0.5
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time (sec)
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
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ia
ib
ic
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-1
0
1
2
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4
5
6
Time(sec)
DClinkvoltage(pu)
Vdcref
Vdc
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
-0.5
0
0.5
1
1.5
Time(sec)
Activepower(pu)
P ref
P

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