1. 13
EVEN
SEMESTER
LOW
POWER
VLSI
DESIGN-­‐2-­‐MTech-­‐
Homework
–
UNIT2
Shivananda
Koteshwar
Professor,
E&C
Department,
PESIT
SC
1) Introduction
5) Low
Power
Design
Circuit
Level
2) Device
and
Technology
Impact
on
Low
6) Low
Power
Architecture
and
Systems
Power
3) Power
Estimation,
Simulation
Power
7) Low
Power
Clock
Distribution
Analysis
4) Probabilistic
Power
Analysis
8) Algorithm
and
Architectural
Level
Methodologies
Reference
Books:
1. Kaushik
Roy,
Sharat
Prasad,
“
Low-­‐Power
CMOS
VLSI
Circuit
Design”
Wiley,
2000
2. Gary
K.
Yeap,
“
Practical
Low
Power
Digital
VLSI
Design”,
KAP,
2002
3. Rabaey,
Pedram,
“
Low
Power
Design
Methodologies”
Kluwer
Academic,
1997
UNIT
2:
Device
and
Technology
Impact
on
Low
Power:
Dynamic
dissipation
in
CMOS,
Transistor
sizing
&
gate
oxide
thickness,
Impact
of
technology
Scaling,
Technology
&
Device
innovation
P e o p l e s
E d u c a t i o n
S o c i e t y
S o u t h
C a m p u s
( w w w . p e s . e d u )

2. Low
Power
VLSI
Design
(2nd
Semester)
UNIT
2
HW
v1.0
Paper Submission Team
1 Gate Level Power Optimization Techniques Subramanya / Ravindra
in Synthesis- Technology Mapping, Cell
Sizing, Buffer Insertion, Phase Assignment,
Pin Swapping, Factoring etc
2 3D Chips Shivukumar / Amaranath
3 Design Approaches to reduce Power – Sagar / Akshay
Multi Clock Source, Multi VDD (Multi
Voltage) , MTCMOS Power Gating (Multi
Supply), Multi Voltage with Power Gating
(Multi Supply), Dynamic Voltage
Frequency Scaling, Adaptive Voltage
Scaling etc
4 Write a note on special cells required for Santosh / Ajit
Low Power Design - Level Shifters
(Voltage Interface Cells), Isolation Cells,
Retention Registers, State Retention Power
Gating Registers, Always On Buffer,
Integrated Clock Gating Cell
5 Physical Approaches to reduce Power – Nitin / Zowresh
Power Integrity, Power Gating (Course
Grain MTCMOS, Fine Grain MTCMOS) etc
6 Write a note on load capacitance – Gate Swatishree / Chaitra
Capacitance, Overlap Capacitance and
Diffusion Capacitance and Interconnect
capacitance
7 Write a note on Body Effect, Sub threshold Geetanjali / Harshitaa
current, Sub Threshold Swing, Back bias
Control, Stack Effect, Gate Oxide
Tunneling current and Inverse Biased
Leakage current
8 System Level Low Power Methodology Rajshekhar / Vinayak
(Partitioning, Power-Down, Power State
etc) and Algorithm Level Low Power
Methodology (Complexity, Concurrency,
Regularity, Locality etc)
9 Architectural Level Low Power Sandeep / Muralidhar
Methodology (Parallelism, Pipelining,
Redundancy, Data Encoding etc)
Shivoo
Koteshwar’s
Notes
2
shivoo@pes.edu

3. Low
Power
VLSI
Design
(2nd
Semester)
UNIT
2
HW
v1.0
Questions to be answered by all (All are 8marks
questions unless specified otherwise)
1. Using the mathematical charge model, derive an expression for
threshold voltage VT of MIS Diode
2. Write an explanatory notes on physics of power dissipation in
MOSFET devices
3. Discuss the transistor sizing and gate oxide thickness with a
help of neat diagrams
4. Explain the impact of technology on scaling
5. Explain the technology and device innovations for novel high
speed low power VLSI devices
6. With neat sketches, explain the impact of device scaling on
delay, energy delay product and total capacitance
7. What are the technology and device innovations available to
reduce total capacitance?
8. A chip operating at 300MHz and 3.3V has dimensions of length
equal to 1.5 times the width. The length of the clock track is
double the chip circumference. Chip length is 30mm and clock
track width is 1.2µm; if the parasitic capacitance of clock track is
I f F/µm2, determine the power dissipation of the clock signal.
Shivoo
Koteshwar’s
Notes
3
shivoo@pes.edu