3. Background & Motivation
⢠One of the most critical functions carried out
by ALU
⢠Digital multiplication is the most extensively
used operation (especially in signal
processing), people who design digital signal
processors sacrifice a lot of chip area in order
to make the multiply as fast as possible
⢠Innumerable schemes have been proposed for
realization of the operation
4. Objective
⢠In array multiplier we use the
signed,unsigned numbers separetly but
we want to perform the both
signed,unsigned operations at the same
time for time delay by using the
verilogHDL.
5. Introduction
ď The booth encoding performs the signed unsigned
modified encoding multiplier.
ď The requirement of the modern computer system is
dedicated and very high speed unique multiplier unit
for signed and unsigned numbers.
ď The carry save adder(CSA) tree and the final carry
look ahead(CLA) adder used to speed up the
multiplier operation.
6. Multiplication Schemes
⢠Serial Multiplication (Shift-Add)
â Computing a set of partial products, and then
summing the partial products together.
â The implementations are primitive with simple
architectures (used when there is a lack of a dedicated
hardware multiplier)
⢠Parallel Multiplication
â Partial products are generated simultaneously
â Parallel implementations are used for high
performance machines, where computation latency
needs to be minimized
7. EXISTING METHOD
⢠IN general a multiplier uses array of full adders or wallace
tree instead of the array of fas.,i.e.,this multiplier mainly
consists of the two parts: a tree to compress the partial
products such as wallace tree,and final adder.
⢠Because wallace tree is to add the partial products from
encoder as parllel as possible,its operation time is
proportional to, where is the number of outputs
⢠The most effective way to increase the speed of a multiplier is
to reduce the number of the partial products.
10. For 4*4 Array Multiplier, it needs 16
AND gates, 4 HAs, 8FAs (total 12
Adders)
For m*n Array Multiplier, it needs
m*n AND gates, n HAs, (m-2)*n FAs,
(total (m-1)*n Adders)
11. Advantages & Disadvantages
⢠Advantages:
â Minimum complexity
â Easily scalable
â Easily pipelined
â Regular shape, easy to
place & route
⢠Disadvantages:
â High power consumption
â More digital gates
resulting in large chip area
12. PROPOSED METHOD
⢠TO reduce the number of calculation steps for partial
products,MBE algorithm has been applied mostly where
wallace tree has taken the role of increasing the speed to add
the partial products.
⢠To increase the speed of the MBE algorithm many parallel
multiplications have been detected but a configurable booth
multiplier has been designed which provides a flexible
arithmatic capacity an d a tradeoff between output precision
and power consumption.
13. Booth's Algorithm Advantages
⢠Multiplication can be sped up
⢠When large number of consecutive 1s in
multiplier
⢠Replace consecutive additions
⢠Subtract at least-significant end
⢠Add at position to the left of the most-
significant end
15. Conclusions
⢠Array multiplier is implemented and verified in
Verilog
⢠Although it utilizes more gates, the
performance can easily be increased using
pipeline technique
⢠As a parallel multiplication method, array
multiplier outperforms serial multiplication
schemes in terms of speed.