1. Modeling and Analysis of a Micro-Inverter Configuration
for High Power Phosphoric Acid Fuel Cell Application
Somasundaram Essakiappan1
, Harish S. Krishnamoorthy1
, Jorge Ramos-Ruiz1
,
Prasad Enjeti1
, Mohamed Arifujjaman2
, Tejinder Singh2
1
Department of Electrical & Computer Engineering, Texas A&M University, College Station, USA
2
UTC Power, South Windsor, Connecticut, USA
Abstract— In this paper a micro-inverter configuration for utility
and commercial scale fuel cell (FC) power systems is proposed. A
conventional system uses multiple FC stacks connected in series
and is interfaced to the utility grid through a centralized inverter.
This system suffers from disadvantages such as the FC current
being limited by the weakest stack and the requirement for high
voltage semiconductor devices under light loads, due to the
voltage vs. power characteristics of FCs. In the proposed
configuration each FC stack is individually connected to a micro-
inverter. Each micro-inverter contains an off-the-shelf 3-phase
inverter fed by a three-level boost converter with four interleaved
converters termed as stages. This new configuration enables
independent operation of the FC stacks leading to increased
energy processing and wide power range operation without the
need for high voltage semiconductor devices. The interleaved
three-level boost converter leads to increased efficiency through
stage-shedding, depending on load level. The topology also makes
FC systems more modular in design and control. This paper
discusses the operation, modeling and design of the proposed
topology for a 100 kW FC stack. Simulation results demonstrate
that this topology can be attractive for commercial fuel cell
power plants. A scaled-down laboratory prototype was designed
and experimental results are also provided in this paper.
Keywords – Fuel cells, grid integration, DC-DC boost converter,
three-level, interleaved, phase shedding.
I. INTRODUCTION
Fuel cells (FC) have a unique position among modern high
power systems as they are more stable, regulated, and less
intermittent compared to other alternative power sources like
wind or solar photovoltaic power systems. The adoption and
market penetration of fuel cell power plants for commercial
establishments has been increasing [1]. Fuel cell power plants,
in conjunction with solar PV systems and small wind turbine
generators also form the back-bone of micro-grids, which have
shown great promise as islanded power systems during
emergencies [2]. Various architectures for fuel cell power
conversion are currently being employed by manufacturers and
further explored by researchers [3].
Conventional fuel cell systems consist of FC stacks
connected in series which are then connected to a DC-DC
converter which forms the DC bus of the system. It is then
connected to a centralized inverter. Such configurations suffer
from the disadvantage that individual FC stacks cannot be
closely regulated due to the series connection. Also, there are
limitations on minimum operating power levels. Since the
output voltage of fuel cells exhibits an inverse relationship with
the load level - with an almost 2:1 ratio of no-load to full load
voltage, as seen from fig. 1 - fuel cells are considered to be
‘soft’ voltage sources [4]. Therefore, a reduction in operating
power levels can lead to large rise in DC bus voltage. Then the
centralized DC-DC converter and inverter system has to be
designed using high voltage devices, with light load operation
capabilities that would make the system operate at sub-optimal
efficiencies even under full load. Otherwise, the minimum
operating power point may have to be limited to 70-80% of full
power, which reduces the operational flexibility. The micro-
inverter system proposed in this paper addresses these
limitations of conventional FC systems.
Fig. 1: V-I and output power characteristics of a 100 kW fuel cell
stack; output voltage exhibiting a 2:1 variation from no-load to full
load. Light load operation requires high voltage semiconductor
devices due to higher FC output voltages
II. PROPOSED MICRO-INVERTER BASED FUEL CELL SYSTEM
Phosphoric acid fuel cells are a mature technology and they
are well suited for stationary power generation on a
commercial scale [5]. Fig. 2 shows the proposed micro-inverter
configuration. It is envisioned that each micro-inverter
configuration will have a dc-dc converter to boost the output
voltage of each PAFC stack. A standard off-the-shelf three
phase inverter is then employed to interface to 480 V, 60 Hz
electric utility. The 3-level configuration provides significant
advantages over a conventional boost converter:
• The entire system becomes more modular – easier to
add or reduce installed capacity
• The FC stacks are better utilized – since each stack is
interfaced to the utility grid through separate power
1110978-1-4799-0336-8/13/$31.00 ©2013 IEEE

2. converters, the power flow from one stack is not
affected by the others
• Interleaving and stage-shedding in the DC-DC
converter stage improve the system efficiency
• Requirement for a smaller boost inductor and lower
switching frequency, since the interleaved design
reduces the ripple in FC current.
• The FC stacks can be operated with high efficiencies at
light loads ( such as <30%) as the DC-DC converter
regulates the output voltage even for high FC stack
voltages (as per the FC characteristics shown in fig. 1)
• Power semiconductor devices of lower ratings can be
employed for the boost converter and inverter stages
The overall architecture of the micro-inverter configuration
rated at 100 kW is shown in fig. 3. As the FC stack power
varies from no-load to full-load, the output voltage drops from
450 V to 225 V. The DC-DC converter is a non-isolated
topology with four parallel-connected, interleaved stages of 3-
level boost converter, which produces a DC bus voltage of 750
V [6][7]. Since each FC stack follows the V-I characteristics in
figure 1, the minimum FC voltage of 225 V at full load and the
voltage gain of the boost converter must be greater than 3 to
generate a DC-link voltage of 750 V.
Grid interconnection is realized through a commercially
available inverter chosen with the following specifications:
i. The THD at the AC side should be less than 3% at the
base load.
ii. The current reference for the inverter d-q control is
generated based on the available fuel cell power.
Fig. 2: Schematic of proposed ‘micro-inverter’ configuration for a
100 kW rated fuel cell power system
iii. Reactive power supply can be adjusted as per grid
demand.
iv. The system is directly interfaced to the utility and no
isolation is provided at the inverter side.
v. A fault protection scheme at the utility side to isolate
the system on fault detection.
Fig. 3: Overall system architecture of proposed high power PAFC commercial system rated 100 kW
3‐phase, 480 V, 60 / 50 Hz
Stack 1
Stack 2
Stack ...
Stack n
Micro-inverter 1
Micro-inverter 2
Micro-inverter ...
Micro-inverter n
Utility grid or
Load
3 phase 480 V,
50/60 Hz
1111

3. III. OPERATION AND ANALYSIS OF INTERLE
BOOST CONVERTER STAG
The proposed topology shown in fig. 2
inverter blocks which are individually con
stacks in the FC system. Each micro-inverte
stage shown in fig. 4 along with the control
fuel cell stack voltage to a standard DC bus
the input to the inverter.
-
+
Gate
Logic
PI
Voltage
Error
VDC
IFCS1
_ +
PI
Limiter
Carrier
+
_
Comparator
VDCVFCS
FUEL CELL
STACK
(225 to 450V) IFCS1
VDCVFCS
IFCS4
IFCS
V*DC(rI*FCS1(ref)
}
3-Level Boost – Stage 1
3-Level Boost – Stage 4
Fig. 4: Structure of 4-stage interleaved 3-level
rated 100 kW, connected to one FC stack; repr
system shown for one DC-DC stage
III.A. DC-DC 3-Level Converter Operation:
The circuit diagram of one stage of the
boost converter is given in fig. 5 for referen
transformation ratio is given by the boost c
gain expression
)1(
1
DV
V
FCS
DC
−
= , where D is the
IGBTs. For a voltage gain of 4, the theore
would be 0.75.
The 3-level DC-DC converter has two mo
When the input voltage of the converter is less
output voltage, the converter operates in mode
input voltage is greater than 50% of the o
operates in mode 2.
Fig. 5: 1-stage 3-level DC-DC boost converter with
EAVED 3-LEVEL
GE
2 uses n micro-
nnected to the n
er has a DC-DC
ller, to boost the
voltage, forming
P*avail
Inverter &
Grid Interface
IDC
ef)
DC-DC converter
resentative control
e 4-stage 3-level
nce. The voltage
converter voltage
duty cycle of the
etical duty cycle
odes of operation.
s than 50% of the
e 1 and when the
output voltage, it
h high DC gain
Operation mode 1: VFC (Vin) < 0.5
is less than half of the output volt
from the above expression that the d
The waveforms for the switch ga
current are given below in fig. 6a. W
the full input voltage Vin is applied
the inductor current and the load
output capacitors C1 and C2. When
the top switch) is off the inductor cu
also charges the top output capacit
bottom switch S2 is off and the to
capacitor C2 gets charged. The c
profiles and load current are given
cycle of the converter remains a
converter input voltage is less than
and the operation remains in mode 1
Fig. 6a: Gating signals for top (S1) an
three level DC-DC converter and th
mode 1 (VFC < 0.5Vo)
Fig. 6b: Gating signals for top (S1)
currents through the top capacitor C1 an
the load current in the three level D
mode 1 (VFC < 0.5Vo)
Operation mode 2: VFC > 0.5Vo:
since the input voltage is greater
voltage, the duty cycle of the con
than 0.5. This means that there are
of the both switches in the conver
patterns of the top and bottom devi
7a. When one of the switches (say
0.5Vo is applied to the inductor and
up, at the same time, charging
During this time the load curren
capacitor C1. Similar operation occu
S2 is on. The operating waveform
and the load currents are given
Vo: When the input voltage
tage, if can be easily seen
duty cycle is more than 0.5.
ating signals and inductor
When both S1 and S2 are on,
to the inductor, ramping up
current is supplied by the
one of the switches (say S1,
urrent supplies the load and
tor C1. Similarly, when the
p switch is on, the bottom
capacitor charging current
n in the fig. 6b. The duty
above 0.5, as long as the
n half of the output voltage
1.
nd bottom (S2) IGBTs in the
e inductor current, operation
and bottom (S2) IGBTs, the
nd the bottom capacitor C2 and
C-DC converter operating in
In this mode of operation,
r than half of the output
nverter in this mode is less
zero states, in which none
rter are on. The switching
ices are as given in the fig.
y, S1, top device) is on, Vin-
d the inductor current ramps
the bottom capacitor, C2.
nt is supplied by the top
urs when the bottom device
s of the capacitor currents
in fig. 7b. The converter
1112

4. operation switches from mode 1 to mode 2
depending on the input voltage, without any a
of the controller.
Figure 7a: Gating signals for top (S1) and bottom
three level DC-DC converter and the inductor
mode 2 (VFC > 0.5Vo)
Figure 7b: Gating signals for top (S1) and bottom
currents through the top capacitor C1 and the bottom
the load current in the three level DC-DC conv
mode 2 (VFC > 0.5Vo)
III.B. DC-DC Converter PWM Switch Model:
The PWM switch model for the 3-level co
for controller modeling and efficiency estimat
can be derived using the equivalent model
model can capture the efficiency reduction du
losses; though switching losses have to be eva
Fig. 8: PWM switch model equivalent diagram of 1
DC boost converter
2 and vice versa,
action on the part
(S2) IGBTs in the
current, operation
m (S2) IGBTs, the
m capacitor C2 and
verter operating in
onverter is useful
tion purposes and
l in fig. 8. This
ue to conduction
aluated separately.
1-stage 3-level DC-
Analyzing the circuit in fig.
(voltage gain) of the non-ideal
evaluated as given in equation (1).
(
(⎪
⎪
⎩
⎪
⎪
⎨
⎧
⋅
⋅+
+
⋅⎟
⎠
⎞
⎜
⎝
⎛
−
=
CELfcs
dc
R
rD2r2
1
D1
1
V
V
where Vdc is the inverter DC bus
voltage of the fuel cell stack, D is
steady state, rL is the inductor ESR,
on-state resistance and rDD is the
resistance.
The closed loop control strategy
is similar to that of a conventional
be an outer voltage loop and an i
stage, as seen in fig. 4. The tran
derived using small signal state
[8][9]. The right-half plane zero
evident from the equation (2). Tho
one stage is shown in fig. 4, all th
controllers.
( )
( ) ( )
( )⎜
⎜
⎝
⎛
−
+
⎜
⎜
⎝
⎛
−
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
=∧
∧
2
2
fcs
RD1
L
s1
s1
D1
V
sd
sv
III.C. Stage-Shedding for improved
In a multiphase DC-DC c
efficiency is a function of load an
operation. As the power level decre
which are processing power is redu
achieve maximum efficiency, a t
called phase-shedding or phase-dro
shall be referred to as stage-sheddi
to decide the number of interleav
particular load level is given below
is designed to process one-fourth of
one FC stack, the number of stag
75%, 50% and 25% of the power
updated based on extended experim
number of stages with maximum
level.
TABLE I. STAGE-SHEDDING ALGORITHM
OF 4-STAGE 3-LEVEL DC-D
Power
processed
Input
voltage
(FC)
Out
voltag
bu
25% 393 V 750
50% 327 V 750
75% 279 V 750
100% 225 V 750
8, the transfer function
converter
fcs
dc
V
V
could be
( ) )
( ) ⎪
⎪
⎭
⎪
⎪
⎬
⎫
−
⋅−⋅+
2
DDE
D1
rD12
1 (1)
voltage, Vfcs is the output
the operating duty cycle at
rCE is the equivalent IGBT
equivalent diode on-state
y of 3-level boost converter
boost converter. There will
nner current loop for each
nsfer function is popularly
space averaging technique
in the boost converter is
ugh the controller for only
he stages employ identical
( ) ⎟
⎟
⎠
⎞
−
+
⎟
⎟
⎠
⎞
2
2
fcs
L
D1
LC
s
R
V
LI
s
(2)
efficiency:
converter the operational
nd the number of phases in
eases, the number of phases
uced accordingly in order to
technique which has been
opping, which in this paper
ing. A candidate algorithm
ved stages to operate at a
in table I. Since each stage
f the total system power for
ges to operate is chosen at
level. This table might be
mental results to choose the
efficiency at every power
FOR HIGH OPERATING EFFICIENCY
DC CONVERTER
tput
e (DC
us)
No. of
stages
Duty
cycle
0 V 1 0.48
0 V 2 0.57
0 V 3 0.63
0 V 4 0.7
1113

5. IV. DESIGN EXAMPLE OF A COMMERCIAL MICRO-INVERTER
BASED FC SYSTEM
A 100 kW commercial scale FC system is considered for
design. In designing the DC-DC 3-level boost converter, the
following specifications and operating conditions given in
table II were used.
TABLE II. SYSTEM SPECIFICATIONS FOR 100 KW COMMERCIAL FC SYSTEM
Input voltage 225 V (full load), 450 V (no load)
DC bus voltage 750 V
Power rating of one 3-level DC-DC
stage
25 kW
Number of interleaved DC-DC
stages
4
Switching frequency 10 kHz
Inductor design Critical inductance at 10% power
Capacitor design
5% output voltage ripple at full
load, low ESR
The fuel cell stacks are assumed to follow the V-I
characteristics in fig. 1. Based on this assumption, the DC-DC
converter stage in the micro-inverter must be designed for the
worst-case scenario, i.e., when the input voltage is at its
minimum. In order to interface to the 480 V grid, the DC link
voltage should be regulated to at least 750 V.
IV.A. Boost Inductor Design:
At 10% power, the output voltage of the fuel cell stack is
calculated to be 428 V and the current output is 23.4 A. At
such low power levels, one DC-DC stage would be operated.
The inductor is designed for this operating condition to have
critical conduction, and as if the full DC input voltage is
applied to it, to ensure CCM under all possible load conditions.
Since for every switching cycle of the IGBTs the inductor
voltage has two cycles, the current ripple occurs at 20 kHz.
The calculations are shown in equations (3) and (4).
43.0
750
)750(
=
−
= inV
D (3)
H200
)8.46()1020(
)43.0()428(
I2f
DV
L 3
Ls
in
μ≈
⋅×
⋅
=
Δ⋅
⋅
= (4)
IV.B. DC-DC Converter Output Capacitor Design:
The DC-DC converter output capacitor is sized to provide
5% output voltage ripple at full load. At 100% load for one
stage, the output current is 33.33 A. The capacitor should
supply the load current for the biggest possible duty cycle,
which occurs at full load condition. The calculations are
shown in equations (5) and (6). A 100 µF output capacitor is
chosen.
7.0
750
)750(
=
−
= inV
D (5)
F
Vf
DI
C
os
o
o μ63
)05.0()750()1010(
)7.0()33.33(
)05.0( 3
≈
⋅⋅×
⋅
=
⋅⋅
⋅
= (6)
IV.C. Semiconductor Devices for DC-DC Converter and
Efficiency Estimation:
The four stages of DC-DC converter operate based on the
required power. As the power processed decreases, the number
of stages of converter in operation is reduced accordingly. The
design values for semiconductor devices are for a single stage
of DC-DC conversion, operating at full power. The ratings of
the semiconductor switches required are given in the table
below. The losses in the circuit can be analyzed using the
conduction loss calculation with PWM switch model, along
with switching loss calculation from manufacturer datasheets.
TABLE III. SPECIFICATIONS FOR CHOICE OF SEMICONDUCTOR DEVICES FOR
DC-DC STAGE
Component
Voltage rating
(V)
Current rating
(A)
Notes
Boost converter -
IGBT
800 200
VCEsat = 1.75 V,
2.05V for Tj =
125°C [10]
Boost converter -
Fast Recovery
Diode
800 200 trr = 500 ns [11]
Using manufacturers’ datasheets for the IGBT and the
diode, the switching loss can be estimated at 25 kW operating
power level. The switching loss characteristics show the per-
cycle switching loss to be 15 mJ/cycle for one IGBT and 15
mJ/cycle for diodes. At a switching frequency of 10 kHz, this
corresponds to a switching power loss of 450 W. The
conduction power loss can be readily calculated using a duty
cycle of 0.72 and the published forward drop voltages of
semiconductor devices and the estimated losses are 380 W.
The full load efficiency of the DC-DC stage is thus estimated
to be 97%. The switching frequency of the converter may be
changed to improve the efficiency, but the size of passive
components will have to be increased to ensure similar voltage
and current ripple performance.
V. SIMULATION RESULTS
In simulating the 100 kW commercial FC system using
PSIM, the operation of DC-DC converter stages follows the
candidate algorithm given in table I. The FC system is
emulated in software using the mathematical expression
450P25.2V FCSFCS +⋅−= which represents the V-I
characteristics discussed before. The simulation waveforms
for the operation of DC-DC converter and then the overall
system interfaced to a 480 V grid are provided in this section.
V.A. Operation of DC-DC converter at 55% power (55 kW):
Two stages in operation:
When the power output is 55% (55kW) two stages are
operated as in fig. 9. The switches in the two stages are
interleaved by 180°. The inductor currents in the two stages,
input and output voltage waveforms are given in fig. 10. From
fig. 11 it can be seen that the input current (FC current) and
the output voltage ripple occur at twice the switching
frequency and within design specifications.
1114

6. Fig. 9: Two stages out of the four stages in the 3-
in operation for 55% power level
Fig. 10: Simulation waveforms for two DC-DC
operation to produce 55 kW: Inductor currents in
DC-DC converter, input and output voltages of the
power processed
Fig. 11: Input current (FC current) and output vol
DC converter with two stages in operation. C
voltage ripples occur at twice the switching frequen
V.B. Operation of DC-DC converter at 100% p
Four stages in operation:
When the power output is 100% of the de
kW) all four stages process power as illustrate
switches in the four stages are interleave
inductor currents in the all stages, as given in
the interleaving of stages reduces the curren
Fig. 14 shows the FC current and the outpu
occurring at four times the switching.
Fig. 12: All stages of the 4-stage, 3-level converte
for 100% power level
level converter are
C converter stages
n the two stages of
e converter and the
ltage ripple in DC-
Current and output
ncy
power (100 kW):
esign power (100
ed in fig. 12. The
ed by 90°. The
fig. 13 show that
nt ripple to 25%.
ut voltage ripple
er are in operation
Fig. 13: Simulation waveforms for f
operation at 55 kW power: Inductor cu
converter, input and output voltages of
processed
Fig. 14: FC current and output voltag
with all four stages. Current and outpu
times the switching frequency, enablin
sizes
V.C. Operation of the overall system
– Inverter:
The overall FC micro-inverter sy
converter and three phase inverter
grid is simulated for 100% and 50%
results are given below. The line –
inverter can be compared with the g
15. It can be seen in fig. 16 that
shifted from the phase – neutral
phases, providing a high displacem
power factor is maintained at unity.
Fig. 15: FC micro-inverter system ope
line-line voltages and inverter line-li
modulation index control for the invert
voltage is tightly regulated by the DC-D
four DC-DC converter stages
urrents in all stages of DC-DC
f the converter and the power
ge ripple in DC-DC converter
ut voltage ripples occur at four
ng smaller passive component
m: FC – DC/DC converter
ystem of four stage DC-DC
r interfacing with a 480 V
% power and the simulation
– line output voltage of the
grid-side line voltages in fig.
the grid currents are 180°
voltages of the respective
ment power factor. The grid
erating at 100% power – Grid
ine output voltage VAB. The
ter is simple since the DC bus
DC operation to within 5%
1115

7. Fig. 16: The grid currents are at 180° shifted from
resulting in a high displacement factor. The fu
smooth due to multiphase operation with <10% ripp
voltage ripple is <5%
Fig. 17: Simulation results of DC-DC converter
three phase inverter, operating at 50% power. The
is still maintained at a very high value (~0.9
regulation is better than at 100% power
The DC bus voltage is maintained with
steady state operation. The simulation wave
system operates at 50% power are given in
bus regulation is tighter than 100% operat
reduction in power, hence the output current.
are, as before, 180° shifted from the phase-neu
V.D. Power level step-change performance of
inverter system:
The closed loop controller designed to reg
voltage is simulated for a step change in refer
the rated power 100 kW to 50 kW. The cont
to (a) regulate the DC bus voltage (b) choos
stages to turn-off depending on the new refe
(c) control the inverter so that the new refere
into the grid at high power factor. Fig.
performance of the system under abrupt
reference real power from 100 kW to 50 k
voltage is found not to rise beyond 10% of the
the AC side the system power factor remain
The currents in the boost inductors of the fo
seen in fig. 19. Based on the new refer
controller chooses to turn-off an appropriate n
which in this case is 2. It may be noted th
performance of a more realistic system is expe
than these simulation results since in a real sy
in reference power does not happen with zero
m the grid voltages,
uel cell current is
ple and the DC bus
r (two stages) and
e grid power factor
95). The DC bus
hin 5%, for this
eforms when the
fig. 17. The DC
tion, due to the
The line currents
utral voltages.
f FC micro-
gulate the DC bus
rence power from
troller is required
se the number of
rence power and
ence power is fed
18 shows the
step-change in
kW. The DC bus
e rated value. On
ns close to unity.
our stages can be
rence power the
number of stages,
hat the transient
ected to be better
ystem the change
transition time.
Fig. 18: Performance of FC micro-inve
in real power demand from 100 kW to
value given to the system is abruptly c
case scenario and the controller perform
Fig. 19: Inductor currents in the four
converter during step change in real po
chooses to turn-off two stages in respon
demand
VI. PRELIMINARY EXPERI
A scaled-down prototype for th
stage rated 300 W was constructed
The semiconductor devices used
diodes (Cree CMF20120D and C
efficiency. The controller was
Instruments microcontroller TMS32
DC-DC converter was operated in
2.During steady state operation th
not only that the reference DC
individual output capacitor voltage
output DC bus voltage. Doing so
MOSFETs dissipate fairly equal a
ensuring uniform thermal dissipatio
Fig. 20 shows the operation o
mode 1, wherein the input voltag
output voltage. The power process
The duty cycle is more than 0.5,
device voltage VDS. When both sw
inductor voltage is equal to the inpu
inductor ramps up. The operation o
can be seen in fig. 21. The duty cyc
input voltage is more than half of o
current increases when one of the
Vin-0.5Vo is positive. The current fa
off.
erter system under step-change
o 50 kW. The reference power
changed to evaluate the worst
ms satisfactorily
stages of interleaved DC-DC
ower processed. The controller
nse to the change in real power
IMENTAL RESULTS
e 3-level DC-DC converter
and tested in the laboratory.
were SiC MOSFETs and
C4D40120D) for increased
designed using Texas
20F28035. One stage of the
n both mode 1 and mode
he controller should ensure
output voltage, but the
s should be one-half of the
o will ensure that the two
amounts of power, thereby
on.
of the 3-level converter in
ge is less than half of the
sed at this time is 265 W.
as can be seen from the
witches are on, (VDS =0) the
ut DC and the current in the
of the converter in mode 2
cle is less than 0.5 since the
utput voltage. The inductor
two switches is on, since
alls when both switches are
1116

8. Fig. 20: Three-level converter device voltage (VDS) during mode 1
operation – Channel 1 shows top switch S1 and channel 2 shows
bottom switch S2. Channel 3 shows the AC component of inductor
current waveform. Current ramps up when both the devices are on,
applying the input voltage across inductor
Fig. 20: Three-level converter device voltage (VDS) for mode 2
operation – Channel 1 shows top switch S1 and channel 2 shows
bottom switch S2. Channel 3 shows the AC component of inductor
current waveform. Inductor current increases when either of the two
switches is on and decreases when both switches are off
VII. CONCLUSION
In this paper, a micro-inverter based commercial / utility
scale FC power system operating over a wide load range was
proposed. The micro-inverter architecture makes the use of
lower voltage power semiconductor devices than conventional
systems, which are limited in their operational power range.
The proposed system also makes the regulation of individual
FC stacks possible. The interleaved design of the DC-DC
converter provides high efficiency operation over varying
power levels, using stage-shedding techniques. The grid
interface converter has two stages, the first one being a 4-stage
3-level DC-DC boost converter and the second being an off-
the-shelf 3-phase inverter. Analysis and modeling of power
electronic converters and their control were discussed in this
paper.
A design example for a 100 kW FC system integrated to a
480 V grid was provided. Simulation results showed that this
topology is very effective for commercial fuel cell power
plants and makes the system more modular. The utilization of
the fuel cell as well as power devices could be made more
effective over a wide operating power range. A scaled-down
laboratory prototype was also described and the experimental
results verify the operation of the 3-level boost converter.
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