hard ware discriptive language programming

1. CHAPTER 4
VHDL PROGRAMMING

2. COMPARISON BETWEEN DIFFERENT MODELLING
BEHAVIORAL DATA FLOW STRUCTURAL
IT consist of sequential
program statement
It consist of concurrent
statements
It is set of interconnect
component
It requires truth table for
design
It requires Boolean
expression
for design
It requires logical
diagrammed for design
It represents behavior It represents behavior It represents structure
It consist gate level
abstraction
It consist gate level
abstraction or algorithm
It consist RTL abstraction
It is expressed in a
sequential VHDL process
The view of data flow as
flowing a design from input
to output
The view is closest to
hardware

3. Syntax for VHDL programme
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ………………. is
Port ( ……. : in STD_LOGIC;
……….. : in STD_LOGIC;
……………: out STD_LOGIC);
End……………….;
architecture Behavioral of ………..is
begin
……………;
……………………..;
……………………….;
end Behavioral

4. Write a VHDL Code for AND gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and-gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and-gate;
architecture Behavioral of and-gate is
begin
y <= a and b;
end Behavioral;

5. Write a VHDL Code for OR gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or-gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and-gate;
architecture Behavioral of or-gate is
begin
y <= a or b;
end Behavioral;

6. Write a VHDL Code for NOR gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nor-gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and-gate;
architecture Behavioral of nor-gate is
begin
y <= a nor b;
end Behavioral;

7. Write a VHDL Code for NAND gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nand -gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and-gate;
architecture Behavioral of nand-gate is
begin
y <= a nand b;
end Behavioral

8. Write a VHDL Code for EX-OR gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exor-gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and-gate;
architecture Behavioral of exor-gate is
begin
y <= a xor b;
end Behavioral

9. Write a VHDL Code for EX-NOR gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity exnor-gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end and-gate;
architecture Behavioral of exnor-gate is
begin
y <= a xnor b;
end Behavioral

10. Write a VHDL Code for HALF ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half-adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum: out STD_LOGIC
Carry : out STD_LOGIC);
end half-adder;
architecture Behavioral of half-adder is
begin
Sum <= a xor b;
Carry <= a and b;
end Behavioral

11. Write a VHDL Code for HALF SUBSTRACTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity half-substractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
diff : out STD_LOGIC
barrow : out STD_LOGIC);
end half-substractor;
architecture Behavioral of half-substractor is
begin
diff <= a xor b;
barrow <= ( not a ) and b;
end Behavioral

12. Write a VHDL Code for FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full-adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c: in STD_LOGIC;
sum: out STD_LOGIC
Carry : out STD_LOGIC);
end full-adder;
architecture Behavioral of full-adder is
begin
Sum <= a xor b xor c;
Carry <=( (a and b) or ( a and c ) or (b and c)) ;
end Behavioral

13. Write a VHDL Code for FULL SUBSTRACTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity full-substractor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c: in STD_LOGIC;
difference : out STD_LOGIC
Barrow : out STD_LOGIC);
end full-substractor
architecture Behavioral of full-adder is
begin
Difference <= a xor b xor c;
Barrow <=((not a) and b) or ( not a ) and c) or ( b and c));
end Behavioral

14. TYPES OF STATEMENTS
a) USING IF ELSE STATEMENT
b) USING CASE SELECT STATEMENT
c) USING WHEN ELSE STATEMENT
d) USING WITH SELECT STATEMENT

15. Write VHDL CODE FOR 4:1 MUX USING IF ELSE STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer_4_1 is
port(
din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC );
end multiplexer_4_1;
architecture Behavioral
multiplexer4_1 is
begin
mux : process (din,sel) is
begin
if (sel="00") then
dout <= din(3);
elsif (sel="01") then
dout <= din(2);
elsif (sel="10") then
dout <= din(1);
else
dout <= din(0);
end if;
end process;
end multiplexer4_1_arc;

16. Write VHDL CODE FOR 4:1 MUX USING CASE STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
• entity multiplexer_case is
port(
din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC );
end multiplexer_case;
• architecture multiplexer_case_arc of
multiplexer_case is
begin
mux : process (din,sel) is
begin
case sel is
when "00" => dout <= din(3);
when "01" => dout <= din(2);
when "10" => dout <= din(1);
when others => dout <= din(0);
end case;
end process mux;
end multiplexer_case_arc;

17. Write VHDL CODE FOR 4:1 MUX USING when else STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
• entity multiplexer_case is
port
• ( din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
dout : out STD_LOGIC );
end multiplexer_case;
• architecture multiplexer4_1_arc
of multiplexer4_1 is
begin
dout <= din(0) when (sel="00")
else
din(1) when (sel="01")
else
din(2) when (sel="10")
else
din(3) when others
• end multiplexer4_1_arc;en

18. Write VHDL CODE FOR 4:1 MUX USING with select STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
• entity multiplexer_case is
port
• ( din : in STD_LOGIC_VECTOR(3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto
0);
dout : out STD_LOGIC );
end multiplexer_case;
architecture multiplexer4_1_arc of
multiplexer_4_1 is
begin
with sel select
dout <= din(3) when "00",
din(2) when "01",
din(1) when "10",
din(0) when others;
end multiplexer4_1_arc;

19. Write VHDL CODE FOR 1:4 DMUX USING IF ELSE STATEMENT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Dmultiplexer 1-4 DMUX
is
port( din : in;
sel : in STD_LOGIC_VECTOR(1
downto 0);
a : out STD_LOGIC
b : out STD_LOGIC
b : out STD_LOGIC
d : out STD_LOGIC);
end Dmultiplexer 1-4 DMUX ;
• architecture Behavioral
Dmultiplexer 1-4 DMUX is
begin
mux : process (din,sel) is
begin
if (sel="00") then
a <= din;
elsif (sel="01") then
b<= din;
elsif (sel="10") then
c <= din;
else
d <= din;
end if;
end process;
end Dmultiplexer 1-4 DMUX ;

20. Write VHDL CODE FOR 1:4 DMUX USING when else
STATEMENT
library IEEE;use
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Dmultiplexer 1-4 DMUX
is
port( din : in;
sel : in STD_LOGIC_VECTOR(1
downto 0);
a : out STD_LOGIC
b : out STD_LOGIC
b : out STD_LOGIC
d : out STD_LOGIC);
end Dmultiplexer 1-4 DMUX ;
• architecture Dmultiplexer 1-4
DMUX is
begin
a<= din when (sel="00")
• else
b<= din when (sel="01")
• else
c<= din when (sel="10")
• else
d<= din when others
• end Dmultiplexer 1-4 DMUX arc;