bucu2_5

Everything you ever wanted to know about Buck Converter
Design for LED Lighting - unless you are writing a book
Woody Smith
-Design Geek
LINE-IN
PART 1: ANALOG
CONTROLLERS
1

2
Index
Agenda and goals pages 5,6,7
LED drivers first thoughts and spec’s pages 8-14
Basic Buck Theory pages 15-19
a) current mode page 20-158
1) First order models pages 21-36
2) Averaged models pages 37-46
3) more accurate models pages 47-158
a)intro pages48-57
b)block diagram CPM transfer functions pages 58-64
c) Tymerski model and transfer func’s pages 65-67
d) Effect of current feedback on Q pages 68
e) Low Q approx and transfer functions pages 69-77
f)example design pages 78-81

AGENDA AND GOALS
1.)Develop a complete design procedure for advanced controller buck converters for
LED Drivers Systems
•Focusing on:
•Overall power efficiency of the lighting assembly
•LED operating efficacy (lumen output per watt of input power)
•Thermal management of the LEDs and their driver circuit
•AC power factor correction (PFC) for the driver circuitry
•AC harmonics generation (distortion)
•Meeting EMI restrictions
•Whether or not dimming is required
•LED driver reliability and service life (to match that of the LEDs)
•Circuit protection devices needed
•Electronics space efficiency (assembly size)
•Cost/competitive position
5

AGENDA AND GOALS
Design Approach
1.)Matlab/LTpice macro simulation to handle the majority of the design tasks
--Combined with an Excel spreadsheet for spec and equations
---Showing the strengths of each controller
Current Mode
1.)Peak, Average, OCPM
V2 mode
Sliding Mode
COT
1.)Fixed on time
2.)Fixed off time
Sigma Delta
2.) Comparison of the various architectures
Decision based on the overall system spec
3.) final design in Spectre/Hspice 6

AGENDA and GOALS
Design Criteria
•LED operating efficacy (lumen output per watt of input power)
•Overall power efficiency of the lighting assembly
•Thermal management of the LEDs and their driver circuit
• only 10-25% of the power is converted to Lumens!!
•AC power factor correction (PFC) for the driver circuitry
•AC harmonics generation (distortion)
•Meeting EMI restrictions
•Whether or not dimming is required
•LED driver reliability and service life (to match that of the LEDs)
•Circuit protection devices needed
•Electronics space efficiency (assembly size)
•Cost/competitive position
-From an EDN article by
Jim Young, ON Semiconductor, and
Usha Patel, Littelfuse, Inc. - October 8, 2012
7

First some thoughts on a possible new
direction for LED Lighting
8

AC dimmer
Optional LED
Microcontroller
AC
Control
(I2C, PWM, Analog)
Voltage,
current,
frequency,
Harmonics, etc.
Monitor
Temperature,
Brightness,
Monitor
GWSnet
Interface
BACnet Bus
Smart Light - Rethink
Customized for building
communication medium
Gateway
Power supply built into the socket
RF
Interface
9

AC dimmer
Optional
LED
Microcontroller
AC
Control
(I2C, PWM, Analog)
Voltage,
current,
frequency,
Harmonics,
etc.
Monitor
Temperature,
Brightness,
Monitor
BACnet
Interface
BACnet Bus
Smart Light – Rethink 2
Customized for building
communication medium
Gateway
Power supply built into the socket
RF
Interface
SMPSPFC
Optional
10

The following is a primer for a top-level down design
methodology. It emphasizes behavioral modeling and design
oriented analysis(to borrow a phrase from Middlebrook).
Our goal is to shorten the
design cycle and
increase physical insight.
-Chip and board
11

First Steps
• What’s your key specs?
• Rank and review them in comparison to existing designs
• Build an Excel spreadsheet and project timeline
• Review this with your team
• Revise and review again
• Build a complete system level behavioral model-Matlab and spice
• Check all spec’s!
• Revise your Excel spreadsheet and timeline
• Verify your resource needs
• List all assumptions
• Make sure your Timeline has “guard bands.”
TORA, TORA, TORA!
12

Strawman Spec
• 90% efficiency
• 50,000 hr. lifetime with greater than 70% of the original luminosity
• 100W equivalent
• Assume 100 lm/W for Leds and 15lm/W for Incandescent -6’ish X advantage
• Assume Iout=700mA
• Vled(700mA) ~ 3.2v (phosphorous coated blue for white’ish light )
• 100W/6*700mA÷3.2≤8 leds required
• Thermal temp≤ 125°C
• 10-100% dimming Triac based
• Triac bleeder ~20mA
• Class B EMI spec
13

1. Tmax =125C
2. Tmin= -25C
3. PFC= .9
4. Power eff=.85% min
5. 10-100% dimming
6. Front edge, triac dimmers
7. 20mA bleeder current
8. Vin =100-140V
9. Iout=500mA ±10ma
10.Vout= 30-32V
11.Inductor ripple=20-40%
12.vout-ripple=?
13.50k hr lifetime
14.Driver dimensions less than
2x3x5mm-working on it
15. driver cost ≤ $1.50 in 100k lots
16. internal OTP, OVP OCP
1. OTP at 125±5
2. OVP at input (MOV fuse-
typically at 200V)
3. OCP-TBD
17. class C EN6001
18.UL approved
Specification list
14

Ok, let’s get down to it. Let’s start with peak mode Buck theory
………let’s start with some solid insights from Abraham Pressman and follow it
with a few(hundred) slides from:
U. of Colorado, ECEN 5807
Great stuff with a solid balance between theory,
design and ……math.
15

From A. Pressman, Switching Mode
Power Supply , pp 177-178
Fig.
5.5a
Fig. 5.5b
Fig. 5.5c
16

From A. Pressman, Switching Mode Power Supply , p 178
KEY
POINTS!!
17

From A. Pressman, Switching Mode Power Supply , p 179
18

Time to start the work
of understanding the
theory and math of
Buck Converters
19

What’s the
optimal ramp
Size?
23

Pertubation is
dying, but what
are you losing?
24

1st Order models work
For small bandwidth systems
Download the Fairchild:
fan4810_http://www.fairchildsemi.com/products/analo
g/fan4810designtools.xls
A wonderful tool for it’s purpose. Use it to explore the
design space.
Read the appnotes and enjoy the wonderful design process, but with your
eyes wide open for it’s limitations
26

Read the appnotes; look at pfc setup, check the EMI filtering
There is a ton of things to be learned here-dissect it!!
27

This a useful large signal, quasi- linearized model w/o averaging or
small signal considerations.
ic
iL
28

Play with the ramps, the compensation. Observe the simplicity of
the switch structure
29

1st order model’s limitations foster a need for a
more advanced approach.
• Start with the large signal models and average
them over the duty cycle phases
• Good, but not yet high frequency aware or
sensitive to sampling effects
• or linear
• Now let’s add State Space matrix formulation and
add small signal perturbations and linearize
• Excellent, but still not complete
• Time to include sampling-Ridley and gang to the
rescue. But which model?
30

Ah, the small
signal
perturbation
32

Positive effects on noise
and Vin sensitivity too
34

LOOP
Even if D is always less than .5(for any setup) use a ramp. CPM
means faster response, lower noise, max-current control on
startup
36

Tan model
Study this
closely
43

Starting with either state space equations or the Tymerski-Vorperian models
you will arrive at this schematic. The only remaining question.: how to model
sampling effects?
46

∞
Or
At least greater than one
56

Ignore this for the moment
How cool is this equation. Look how Fm (ie, comp ramp)influences
both loops. Later we will add loop compensation, loop delay, and
sampling effects and it gets really interesting. 60

You’ll want to
derive this
70

Compare to first-order approximation of the
sampled-data control-to-current model
hfs
s
sT
sT
c
L
sssT
e
esi
si s
s















1
1
)/(1
1
1
11
1
1
)(ˆ
)(ˆ
)/(
1
)/(
1


s
ssT
s
s
e s




 s
a
s
hf
f
m
m
DD
f
f
2
221
1
1
1





Control-to-inductor current response behaves
approximately as a single-pole transfer function
with a high-frequency pole at
Model (4) is consistent with the sampled-data small-signal model
71

A quick aside on
2nd order
transfer function
roots
72

Wow, Q< 1 gain is pretty nicely behaved
and the phase variation is getting smooth
74

At low Q the poles are separate but interact depending
on their frequency separation(a decade of frequeny to
really separate them phase-wise. Gain-wise decades of
separation removes most interaction)
75

Compare to first-order approximation of the
high-frequency sampled-data control-to-current
model
hfs
s
sT
sT
c
L
sssT
e
esi
si s
s















1
1
)/(1
1
1
11
1
1
)(ˆ
)(ˆ
)/(
1
)/(
1


s
ssT
s
s
e s



kHz32
221
1
1
1
2







 ss
a
s
hf
ff
m
m
DD
f
f
with a high-frequency pole at 32k vs.39kHz~20%
with Ma=M2. play with
Ma. I grew up using
Ma=( .5-.75) x M2, but
is that opt?
79

2nd-order approximation in the small-signal averaged model
Except Fm
80

Example
• CPM buck converter:
Vg = 10V, L = 5 mH, C = 75 mF, D = 0.5, V = 5 V,
I = 20 A, R = V/I = 0.25 W, fs = 100 kHz
• Inductor current slopes:
m1 = (Vg – V)/L = 1 A/ms
m2 = V/L = 1 A/ms
A/V25.0
2
'

L
TDD
F s
g
D = 0.5: CPM controller is stable for any compensation ramp, ma/m2 > 0
Select: ma/m2 = Ma/M2 = 1, Ma = 1 A/ms
1/A1.0
1
2
1
21




s
a
m
TMM
M
F
81

Example (cont.)
kHz2.8
1
2
1

LC
fo

1
L
C
RQ
47.047.0
1
1



 Q
L
VRCF
R
VF
QQ
gm
gm
ckHz3.1851  o
gm
oc f
R
VF
ff
kHz4.81  ccp fQf
kHz39/2  cchfp Qfff
Duty-cycle control
Peak current-mode control (CPM)
82

Repeating the obvious about these models
• Averaged models depend on small variations on all variables
• Particularly duty cycle
• It works well for DCM too, but only if key control variables are well
controlled
• Peak current mode wants small ∆IL to minimize switching uncertainty;
minimum peak to average error(always check this at low current levels)
• Low peak/average means low distortion but big inductors
• Leading to shallow current ramps and more noise sensitivity at low
vin
• Why? Low vin shallow ramps and the same level of
switching noise (comparator switching spikes(~.1-.2v?)
• Serious layout worries
86

2nd-order approximation in the small-signal averaged model
87

][ˆ)1(]1[ˆ][ˆ ninini cLL  
Discrete-time dynamics: )(ˆ)(ˆ zizi Lc 
Z-transform: )(ˆ)1()(ˆ)(ˆ 1
zizzizi cLL   
1
1
1
)(ˆ
)(ˆ




zzi
zi
c
L

Discrete-time (z-domain) control-to-
inductor current transfer function:
ss TjsT
ee 










1
1
1
1
Difference equation:
• Pole at z = 
• Stability condition: pole inside the unit circle, || < 1
• Frequency response (note that z1 corresponds to a delay of Ts in
time domain):
89

Equivalent hold: )(ˆ)(ˆ),(ˆ][ˆ sizitini LLLL 
ic[n]
m1
m2
ic + ic
iL[n]
d[n]Ts
iL[n-1]
ma(t)
iL(t)
iL[n]
Ts
90

Equivalent hold
• The response from the samples iL[n] of the
inductor current to the inductor current
perturbation iL(t) is a pulse of amplitude iL[n] and
length Ts
• Hence, in frequency domain, the equivalent hold
has the transfer function previously derived for
the zero-order hold:
s
e ssT
1
£[u(t)-u(t)𝛿(t+Ts)]=
91

Complete sampled-data “transfer
function”
s
sT
sT
c
L
sT
e
esi
si s
s






1
1
1
)(ˆ
)(ˆ


2
2
1
2
'
1
m
m
D
D
m
m
mm
mm
a
a
a
a






Control-to-inductor current small-signal response:
Ridley, Tan,
Middlebrook-
whoever. The
central issue is
this equation.
How do we
approximate it?
92

Example
Vg = 10V, L = 5 mH, C = 75 mF, D = 0.5, V = 5 V,
I = 20 A, R = V/I = 0.25 W, fs = 100 kHz
m1 = (Vg – V)/L = 1 A/ms
m2 = V/L = 1 A/ms
2
2
2
2
1
2
1
1
'
1
m
m
m
m
m
m
D
D
m
m
mm
mm
a
a
a
a
a
a









s
sT
sT
c
L
sT
e
esi
si s
s






1
1
1
)(ˆ
)(ˆ


93

Control-to-inductor current responses
for several compensation ramps (ma/m2 is a
parameter)
10
2
10
3
10
4
10
5
-40
-30
-20
-10
0
10
20
magnitude[db]
iL/ic magnitude and phase responses
10
2
10
3
10
4
10
5
-150
-100
-50
0
frequency [Hz]
phase[deg]
ma/m2=0.1
ma/m2=0.5
ma/m2=1
ma/m2=5
5
1
0.5
0.1
MATLAB file: CPMfr.m
Look how the comp ramp kills
the Ti loop gain and BW
Large Fm approx
94

First-order approximation
hfs
s
sT
sT
c
L
sssT
e
esi
si s
s















1
1
)/(1
1
1
11
1
1
)(ˆ
)(ˆ
)/(
1
)/(
1


s
ssT
s
s
e s



with a high-frequency pole at
Same prediction as HF pole in basic model (4) (Tan)

 s
a
s
hf
f
m
m
DD
f
f
2
221
1
1
1





PADE 1st order
Delay of
the control
signal
95

for several compensation ramps (ma/m2 = 0.1, 0.5, 1,
5)
10
2
10
3
10
4
10
5
-40
-30
-20
-10
0
10
20
magnitude[db]
iL/ic magnitude and phase responses
10
2
10
3
10
4
10
5
-150
-100
-50
0
frequency [Hz]
phase[deg]
1st-order transfer-function approximation
96

Second-order approximation
2
2/)2/(1
1
2
1
11
1
1
)(ˆ
)(ˆ






















ss
s
sT
sT
c
L
sssT
e
esi
si s
s



2
2
2/)2/(2
1
2/)2/(2
1















ss
sssT
ss
ss
e s




2
221
12
1
12
m
m
DD
Q
a








Control-to-inductor current response
behaves approximately as a second-
order transfer function with corner
frequency fs/2 and Q-factor given by
Pade 2nd order
approximate
2nd order polynomial
97

10
2
10
3
10
4
10
5
-40
-30
-20
-10
0
10
20
magnitude[db] iL/ic magnitude and phase responses
10
2
10
3
10
4
10
5
-150
-100
-50
0
frequency [Hz]
phase[deg]
for several compensation ramps (ma/m2 = 0.1, 0.5, 1,
5)
2nd-order transfer-function approximation
Vs
Ideal transfer function
98

Example
Vg = 10V, L = 5 mH, C = 75
mF, D = 0.5, V = 5 V,
I = 20 A, R = V/I = 0.25 W, fs
= 100 kHz
m1 = (Vg – V)/L = 1 A/ms
m2 = V/L = 1 A/ms
A/V25.0
2
'

L
TDD
F s
g
Select: ma/m2 = Ma/M2 = 1, Ma = 1 A/ms
1/A1.0
1
2
1
21




s
a
m
TMM
M
F
101

Example (cont.)
kHz2.8
1
2
1

LC
fo

1
L
C
RQ
47.047.0
1
1



 Q
L
VRCF
R
VF
QQ
gm
gm
ckHz3.1851  o
gm
oc f
R
VF
ff
kHz4.81  ccp fQf
kHz39/2  cchfp Qfff
Duty-cycle control
Peak current-mode control (CPM)
102

Fig. 9
These
is the
key
point
104

Here’s the
another key
point, look at the
phase at fs/10
105

Placeholder until
I do my sense
section
106

How Do I Model Current Mode Converters?
I follow a dual Pantheon of “Gods”
Middlebrook
Erickson
Ridley
Tymerski/Vorperian
Basso
Dixon
Lehman Brooks
Versus
• My goal to get a solid physical insight into the operation and modeling of SMPS
• Study carefully the approximations in the models
• We are taking nonlinear devices and developing :
<averaged> small signal linearized duty cycle controlled models
So you need the math too!
If they have written it, read it!!
112

Simon Ang and Olivia’s book, “Power-Switching converters,”
wonderfully summarizes the process as follows:
This a quite general method that when coupled with the Middlebrook/Cûk dc-dc
transformer produces insightful physical models and great matlab models
113

For Spice ac sim, I head for the Tymerski/Vorperian switching model. Where the
nonlinear switches are replaced with a linearized switching module.
Part of the VPI “masters of
power” group
• Assuming <vL>=0
• D x Vac =D’ x Vcp
• During D, Va=Vc Vcp=D x Vap
• During D,’ Vc=Vp Vac=D’ x Vap
• for ton=D, <ia>=D x <ic> and for toff, <ip>=D’ x <ic>
Applying the small signal variations
• IA + ia(ac) =(D + d(ac))(Ic +ic(ac))
• Ia(ac)= D x ic
• and ip(ac)+ Ip =(D’-d’(ac))(Ic + ic(ac))= D’x ic(ac) - d’ x Ic
• Similarly vcp(ac)= D x vap(ac) + Vap x d(ac)
• And vac(ac) =D’ x vap(ac) –Vap x d(ac)
Eq. 1
Eq. 2
Eq. 3
My crude derivation:
114

Leading to a simple, elegant model with all the essential physics
It averages, linearizes and embeds AC and DC duty cycle effects into the
switching elements- with bias point sensitivity
115

A quick aside on
2nd order
transfer function
roots
117

Wow, Q< 1 gain is pretty nicely behaved
and the phase variation is getting smooth
118

At low Q the poles are separate but interact depending
on their frequency separation(decades of separation to
really separate them phase-wise, but gain-wise only a
decade separation removes most interaction)
120

My Quick and Dirty Model for a Peak CPM buck
Recently working at LED lighting house, I inherited an PCPM low-side buck
without an output cap leading to 100% modulation. I needed to rethink my usual
model. It’s not very original(see the included TI app; and Rendon Holloway’s
(PET/Nov. 2008, and Ridley) inner-current loop model.
Resistor and gain
Pwm Discrete sampling
+ -
ic^ iL
^
131

Woody’s: the inductor is a current source-sort of current loop model
Nonlinear switching
Ave large
Small signal
perturbation
Linear small
signal
1+
Vin and Freq
sensitive
^
^
Simple 1st order and
not very original, but 132

no voltage
loop comp,
min delay Always start with
miminal comp-maybe
add 1/s to get stable,
if needed
Modeling delays
in both loops
133

Demo specification
• Vin(min)=10v
• Vin(max)=15
• Vout=5v
• Vripple=∆v=25mVpp
• Vout(droop)=200mV max(Iout changes from 1A to 10A <1us)
• Iout(max)=15A
• Ts=1us(fs=1Mhz)
• Iin-ripple<15mA
On my TODO list
134

Low Q(≤. 5) Approximation:
or
R*C
Quick re-cap of the
formulas for a peak
current buck
135

“designing
Stable Control
loops”
-D. Mitchell and B.
Mamman
136

Solid, clear thinking about
the process of SMPS
design
144

All these need to worst-case
quantified and ranked in importance
145

In this app
this isn’t a
priority, but
for RGB,
power
supplies,
etc
146

No external
comp ramp
Built this following Brooks Lehman’s notes
from his course at SantaClara Univ
F1 and vind1 handle the current sensing. Look how clearly it shows the sub-harmonic
instability
149

3 ranges of Vin and Inductor current
150

External
ramp
Play with ramp and comparator gains and observe
comp1- what about with a little noise and offset
151

Current Mode decision process
CCM DCM
Pro: Pro:
• Lower ripple
• Lower peak current
• Lower distortion
• No sub-harmonics
• Faster transient
• Less problem light loads
• No external ramp
• No load dump
Con: Con:
• Slower transient
responsible
• Light loads eff
• Sub-harmonic distortion
• Big Caps
• Cap stress
• High inductor peak current
• Bsat increase
• Magnetic core losses
• Higher wire losses
• Mosfet stress increase
153

SYNC Non-sync
Pro:
• less diode losses
• better light load reg
• Lower Qrr, Trr losses
Con:
• Bigger Switches?
• Shoot-thru conduction
• Slower response
• Without a schottky diode
Pro:
• Simpler design
• Good at high current
• Lower cost(?)
Con:
• Higher Thermal
• Trr, Qrr losses
• Rd losses
Unless you go GaN and
Pay the cost
154

Project Design Procedure (part 1)
Questions:
1. What are the Top 3 design criteria
1. Is the design specification approved
2. is the schedule done and approved
1. No, do it now!
2. What are the biggest milestones
3. resources needed
3. Is a custom chip required
1. Process
2. Design tools
3. Chip level spec
4. Any special test or packaging requirements
1. Always check the thermals first and revisit frequently
5. Kick-off meeting w/ the Whole Team
1. As manager, build a complete presentation and discuss it openly
2. if you are a team number be prepared to contribute
3. GET EVERYONE ON BOARD AND COMMITTED
1. Communicate, organize, plan and execute 155

Part II: Design- chip/board Top level
1.) Go thru the specification in-depth
a.)clarify and define
2.) build A macro-model
a.) matlab or spice or verilogA- your call
b.) verify it’s correctness
c.) run it thru the spec
1.) where are the hot points?
d.) present the results
3.) Revisit the spec and schedule
a.)revise and get approvals
Part III: Chip Design
Always start with the specification
1.) Is the package(s) defined.
a.) heatsink
b.) wirebonds
2.) latest sim models available
3.) pin out 156

2.) process requirements
a.)latest Cad models
b.) optional layers
3.) layout tools
a.) chip
b.) board
4.) test Requirements
a.) room temp testing only?
b.) trimming
1.) chip
2.) board
c.) Test port needed?
157

LED Driver Design Strategy
Let’s assume that we are going to design a CCM, current mode buck,
meeting USA standards with a PWM controller.
Reread the specification doc. For LED lighting with dimming it’s all about
lifetime; efficiency; EMI; PFC(>.9); footprint and full range dimming. Where are
the compromises?
Hint 1: the eye is log sensitive and acutely sensitive to light changes at low
illumination. This says be aware of the need for excellent light load regulation,
clean, smooth startups and full range dimming w/o killing the efficiency.
Hint 2: dimming front edge, rear edge, both?
We will assume front edge(USA typical)
Hint 3: EMI class B
Radiated EMI needs to be checked, but for this task it will be conducted EMI
that is the problem. A buck converter is basically a square wave generator
followed by a filter. Square wave means lots of harmonics distortion; line
filtering leading to possible instability(always include effects of the filters in
your design stability modeling.)
158

Hint 4: Lifetime > 50, 000 hours.
Tough, tough, tough. Interplays with cost, performance, size and expensive caps
Hint 5: Is this the base for a multi-product design?.
How are you going to trim and tune it for a range of product specs.
Current limit needs to accurate and fast.
Hint 6: Power supplies for LED driver are about lumens/Watt.
Know your LED’S! Be aware of lot to lot variations, aging, lumen output versus
temperature
159

fc being the current loop unity gain
∆
LED driver Design flow
First-cut-no ESR
or ESL
160

Let’s look at the equilibrium case now for output cap ripple
given: 1. <IL>=0
2. IL(0)=IL(Ts)
3. Ivalley=Iave-∆IL/2 and Ipeak=Iave+∆IL/2
4. Iave=Vout/Rload=ILeds
Find the max
Ton=D*Tsw and toff=(1-D)*Tsw
Step 4b cont’ed
using We arrive at
161

Review the fo and Q formula’s in the ECEN 5807 slides(summary slide 62-63)
Put another way:
Using ∆vout( last slide) we see
Observe that this formula is kinda “toplevel-
ish” with some insight into fo/fsw on ripple
2
2
where
162

Iave
Tsw
ton
Ipeak
Ivalley
∆Q
∆Q
IL
1/fs
∆Q=1/2*(Tsw/2)*iripple/2
Area=.5*base*height
A solid design
equation
163

Rule of Thumb: dv=f(C, fs, Resr, Iripple) For equilibrium voltage ripple approx
Allocate 2/3’s of the allowable ripple to the ESR, and a 1/3 for the cap
Step 5. Calculate the inductor
Inductors are a complete ebook in themselves. I have put a file my dropbox with
an assortment of really interesting reads and it also include class notes from a
couple professors I’ve found enlightening.
I’m going to start with a less sophisticated approach for my first cut value
165

IAve
Iac/2=∆I/2=Ipeak-Iave
Ipeak
166

What are the tradeoffs when chosing an Inductor?
 More ripple means faster transient response.
--Higher peak current- higher Isat requirements
--More core loss
 Typical ripple ratio 20-50% of Iave
 Isat should be a minimum 20-30% greater than max Ipeak
 packaging
--Cost, parasitic coupling, size
 Can the inductor handle load changes fast enough-slew rate
--DCR-resistance
 Aging
--Ipeak, Isat,
 Switching frequency vs inductor size
--switching losses
My rule
167

Also consider for the buck inductor
∆Iup=∆Idown
(Vin-Vout)
2.) V1/L*ton = V2/L*toff
3.) ∆Iave=(∆Iup +∆Idown)/2
1.)
Using 2 and 3 it follows
Lenz’s law
Insights
1.) as L increases, Iripple decreases and Pcore losses decreases and
Isat requirements decrease,
2.) but system response slows too
Voltage cross L:
At Equilibrium:
(Vout)
168

-
vref
-
Gci FmGcv
ˆd
Gvd
Gid
Gvg
Gig
ˆvg
Rs
H
vˆ
ˆiL
Average current CPM
The d gain equation is
the key to all these
models for CM
Gcv and Gci tie the voltage and current loops together. The
questions are: how much do they affect each other and which one do
we tune first.
Power
supply
196

-
vref
-
Gci FmGcv
ˆd
Gvd
Gid
Gvg
Gig
ˆvg
Rs
H
vˆ
ˆiL
Drawn for average CM
SET Gci=1, modify Fm(add ramp) for Peak CM
Note that Gci and
Fm are common
to Tc and Tv
loops
Tv
Tc
Current loop
comp for AveCM
197

CPM design
Always start(finish) with the current loop- it the wide bandwidth one
• Now assuming we are
208

INPUT FILTER DESIGN
Rule 1: Zoutfilter<< ZinSMPS
Rule 2: All poles in the left plane to
main stability
209

A first approach
Why do we need an EMI filter?
• To stop interference with the power source
• HOW? By minimizing the mismatch between the power source
and converter(making resistive)
What are the two conduction modes of EMI?
• Common mode
• CM EMI is noise relative to the ground plane
• Ground return bus or chassis to outputs or supplies
• Parasitic cap between driver FET drain and
chassis is a stereotypical killer
• Differential mode
• Between two outputs or two supplies
• Leading cause is the input EMI filter cap impedance
and
• Switching devices reverse recovery characteristics
211

Undamped filter Buck converter
At low freq |Zemi| is small; but at filter resonance,
|Zemi| can be quite large
simple Input filter
Voltage decreases
Current increases
212

Buck input impedance vs
frequency
213

Zin(f)
Zemi(f)
No overlap
For Stability
• Zin>>Zemi,max
• all poles in left plane
• EMI filter resonance
frequency in the flat in
the flat band of the
buck input impedance
214

Assumptions:
1. At low frequency, a buck converter is constant load.
2. or a current/voltage regulator
3. Or as a neg load resistor from an AC prospective
4. State equation methodology works
P
X1
+
-
X2
Approach 2 -old school
215

Old School II- with apologies to my professors
Following the FHA method(fundamental Harmonic analysis) we assume that
the first harmonic has 90% of the energy and it is a sine wave.
• Ipeak =2*Iavg(converter 50% duty cycle)
• IFH=.636*Ipeak
we find:
216

What about resonance peaks?
• Time for the damping
• And the bench
• But first
217

ESRL1=.02 Light
damping
Very high Q
And well
above 0db
218

Neg. input
Impedance
Moderate Q
Ouch! Filter Zmax is greater than low
frequency Zin- Resonance peaks are
too close too
219

Add a transient
Phase margin has left the house
221

The following is taken from a thesis by Prasanta Kumar
Thakur, EE Dept., National Institute of Technology
Rourkela
228

Very good stuff, but does it give us any physical design insights?- Big yes!
-
233

Really useful stuff here. Observe the criteria for stability and
for a minimally affected current loop- tied to the load. The
only missing is the frequency and transient responses. We
also need a tool to quickly iterate between filter
modifications
235

Middlebrook Extra Element Theorem -EET
Erickson’s book IS on your shelf-read this section now and then come
back to my excerpts from his class notes at the U. of Colorado
236

No problem with
one loop, but what
about 4?
1
Quick re-derive
Added
component
Simple ckt. To
illustrate the
process
Classic
divider
237

ZD=Vtest/itest=(R1+1/sC1)
itest
238

Now we adjust V1 until vout=0
Nulled!
we adjust itest to null
v(out)≜0
Same
as 1
itest
null
Back 2 pages
239

The Elegant WayThe Elegant Way
• Matlab allows us to do cycle-to-cycle simulation and small signal design
with the same circuit
• Add a couple scripts and we can implement Middlebrook’s EET method and
optimize the design with minimal design cycles
• Transients, FFT analysis all in the same package
• It will be our focal tool for exploring advanced controllers
• The following matlab based slides very generated directly from materials
from ECE 5807, U. of Col taught by Prof Dragan Maksimovic. Masterful
Stuff. A serious advantage of running a design group is you get to work with
a group of people from various colleges with different perceptives. Through
them I got introduced to COPE institute writings and dissertations. My next
step is trying to figure out when I can take their Photovoltaic class-hopefully
this summer 240

Using state space
equations to model the
converter (any type) and
the filters
SyncBuck-Converter model
PWM –switching
and small signal
241

Driving point input impedance(ZD) and the nulled input impedance(ZN) using the
EET scripts. It is a linearized, averaged, small signal model of the converter
Change the
Rload, and D
and observe
Of course, you could do it in Ltspice ……..
243

Zo≙filter
output Z Look at their relationships-
peaks separated, but to my
taste, too close in magnitude.
I prefer the filter peak to be
at a lower freq and the ZN to
peak spacing greater than
20db
Investigate the tradeoffs in L versus Cap sizes with parasitics.-Consider space, cost
and aging effects as part of the process
244

Looks pretty solid as is, but the
bench and EMI tester will be
the final arbiters
You might want to bode plot just the extra element
addition to the duty cycle to vout transfer function
245

Why all the worry about input filters?
[ can ruin a great design]
And make the product unsalable
246

Quick and
fast
Slow and
accurate
The following pages will explain the process
248

Output impedance and caps
Start with the obvious: we assume that the output cap is large
enough to keep output voltage constant- its almost true
IC=iL-IR
The following derivation is
from Daniel Hart’s book
An introductory text with enough
knowledge to do some pretty
smart designs
I derived this
earlier, but for
continuity….
259

C. Basso Circuit with slope
comp and PI voltage comp
Output Impedance with PCM and PI voltage comp
• At low frequency Zout(PCM) > Zout(voltage only)
• However at LC resonance the game changes
• For excessive current loop gain it degenerates back to voltage mode
261

Rule of thumb: comp
slope should be 50-75%
Of the off slope in a buck
converter(it is a good
starting pt )
Excessive comp
Looks like std
voltage comp
Why?
262

Vin
Ro
AoL
FB1
FB2
• R0 is the open loop output resistance of Gain amp with the current loop
• FB1 is the current loop
• And FB2 is the voltage loop
It is a quick and dirty model, but you can see that feedback lowers
sensitivity, and see how excessive current LG kills the total loop gain
Zoutcl= Zoutopen loop/[1 + Aol* T(loop gain)]
Ideal
gain
Consider a Classic FB setup with output impedance
263

Optimal Power FET and Driver
Design
264

Time to talk of Cabbages and Kings; or at
least, Power FETs
265

Back of the envelope switching loss
Tr
Tr )
Skips more than a little, but it
is a good starting place
1. Add the Tf losses(turn off)
2. Add Rdson losses
And you have a first cut total
loss estimate
Now cut to the simulation
~Vin
{Vin}
273

True in
2002,
2013??
Basic Rules to Avoid Reverse Recovery Problems
300

Thanks Peter for some really useful advice
302

Thermal design is an iterative process
• Always verify your assumptions
• Check isothermal vs. gradient effects
312

Analogy Between Thermal and Electrical
Resistance
316
Electrical => Q is Charge Thermal => Q is Heat 316

What is the Difference Between θ Type vs.
ψ Type Parameter?
θ Type
• All the heat flows from the junction to location X
(which remains isothermal)
• Location X serves as the external heat sink to the package
ψ Type
• Only a fraction of the heat flows from the junction to location X
(non-isothermal)
• Temperature gradient exists in location X (different points have different
temperature readings)
(non-isothermal)
317
=Gradient 317

Thermals (RӨJA, & RӨJC Definitions)
RӨJA
Thermal impedance from silicon junction to ambient
air temperature. The units of measurement are
˚C/Watt.
RӨJC
Thermal impedance from silicon junction
to device case temperature (all six
sides).
nDissipatio
AJ
θJA
P
TT
R


nDissipatio
CaseJ
θJC
P
TT
R


318
318

Thermal Design Terminology
At each interface from the junction to the ambient
air there is an associated thermal resistance
319
319

Thermal Design 101
Typical Values
• θCU ≈ 71.4°C/W
• Based on 1oz copper, W=1cm
L=1cm. λCU= 4 W/cm K
• θVIA ≈ 261°C/W
• Based on 0.5oz plating
thickness, for 300um via (12mil)
.
• θFR4 ≈ 13.9°C/W
• Based on 320um thickness,
W=1cm L=1cm. λFR4=0.0023
W/cm K
• θSA ≈ 1000°C/W
• W=1cm L=1cm. h= 0.001 W/cm K
320
320

Darn Chip Companies Can’t Make Up Their
Minds.
θJA is a good metric for thermal performance only
when the board used for measurement is known.
321
Check if it was measured per
Jedec standards.
321

Heat Sink Placement
• Add the heatsink in
parallel with the
appropriate thermal
resistance based upon
location.
• Remember
θSA
≈ 1000°C/W per cm
squared
θVIA
≈ (261°C/W) / (# vias)
322
322

323
Design Strategy
1. Determine Max ambient temperature of the application
2. Calculate Internal power dissipation of the IC
– Efficiency, loss elements
3. Make an accurate estimate for required θJA
4. Estimate the Board Heat-sinking Area
TJMAX = (PDMAX * θJA) + TA
323

324
Layout Guideline 1 – Copper Area
• Estimate Board Heatsinking size
– Assumes 1oz full copper on top and bottom
– Assumes natural convection
– Assumes ~1W PD
– Assumes infinite thermal vias
BoardArea(in2
) ≥
77.5 °Cxin2
W
θJA -θJC
BoardArea(cm2
)≥
500 °Cxcm2
W
θJA -θJC
BoardArea(cm2
)≥ 15.29
BoardArea(in2
) ≥ 2.37
xPD
xPD
W
cm2
W
in2
• If qJC is known
• If unknown
324

PCB Area Vs. Junction Temperature
Calculator
PCB
Thermal
Calculator
325
http://www.ti.com/adc/docs/midlevel.tsp?contentId=76735
325

Module PCB qJA Examples
• AN-2026:
– Curves show qJA vs. Cu area, board size, airflow, heatsink
326
326

327
Module qJA Estimator
• AN-2020:
http://www.national.com/assets/en/tools/Thermal_Resistance_Estimate.
xls
327

Solution Size Example
328
328
• Max ambient temp = 80C
• Max temp rise = 125C – 80C = 45C
Determine allowable Temp rise
Ambient Temp Limited
1
• Power requirement = 2.5W (loss, assume
worst case temp)
• θJA requirement = 45C / 2.5W = 18C/W
Determine θJA requirement2
• PCB size > 3” x 3”
• How much board space is available?
• Do I need heat sinking or Airflow?
Determine PCB size3
• Max allowed PCB = 1.5” square
• 4-layer θJA = 30C/W
Determine θJA
PCB Size Limited
1
• Power requirement = 2.5W (loss)
• Temp rise = 2.5W x 30C/W = 75C
• Max allowable ambient = 50C
Determine Max Ambient Temp2
• What is the application’s max ambient?
• Airflow or heat sinking may be required
Will it work?3

329
Layout Guideline 2 – Copper Weight
• Use thick enough copper
– Example 3”x3” board: 2oz Cu qJA is 25% lower than 1oz
• Flood top and bottom with copper if possible
qCu =
Width x Thickness
x Length1
λCu
329

330
Layout Guideline 3 – Thermal Vias
• Use lots of vias
– Thermal resistances in parallel
• Typical 12mil thermal vias:
• Each via:
TC
(TA)
Junction Temperature
TJ __
θVIA
θSAθSAθSAθSA
θSAθSA
θJC
θCu
θCu
θCu
θCu
θCu
θCu
θFR4
θFR4
θFR4
θFR4
θFR4
θFR4
θCu
θCu
θCu
θCu
θCu
θCu
θCu
θVIAS ≈
# of Thermal Vias
261
°C
W
qVIA =
x Length1
λCu
π x [(radius)2
- (radius – plating thickness)2
]
330

331
Layout Guideline 3
• More thermal via guidelines in AN-1520
 qJA vs size, #, and arrangement of vias
– Also qJA vs airflow and PD
This is Must Read! I
originally read as an
Nat Semi Appnote.
It’s insights will blow
you away.
331

332
Layout Guideline 3
• More thermal via guidelines in AN-1520
 qJA vs size, #, and arrangement of vias
– Also qJA vs airflow and PD
332

Active Bleeders and Damping circuits
Or
The Myth of the Universal Dimmer
334

Typical application with active damper and passive damper combo
335

Let’s talk about output resistance
and Droop under load changes in
voltage and current mode
converters
But first, read this article
368

The synopsis: to prevent output droop under load change, we need a
constant, small output impedance under any load and input voltage and a
way to adapt the output voltage
And then read this
369

Let’s start with voltage mode
Std Voltage Buck
Small signal voltage Buck
370

Small signal Voltage mode Buck during state one
V’
V’
Zo w/o load
Îo
+
V
-
IL
Let’s take it to state space now
Buck converter with
load current. For this
analysis I didn’t
include the Fet/diode
Rons or back body
Qrr. Easy enough to
do but I a wanted
“clean” (i.e., small)
equations
SS input-inductor current
SS input 2
cap voltage
371

weThe state space equations for the Buck with output load current as a second
input
Std SS analysis
done in the freq
domain. We will
do it again in the
z domain
372

Now let’s look at the current mode controller
tuned for minimum droop
Av
Look at the
Loops
•They only share Av
376

Great, we can tune the current loop
independent of the voltage loop
•Tune Ti first
• Note: Ti reduces the overall loop
gain
What’s the total loop gain?
G
T2
Reduce the current loop to a Block
•We merged Gcv into Gvd
effectively
377

What was I expecting you to learn from this
section?
•See the usefulness of state space analysis
•As an alternative to the Tymerski-Voperian model
•See how the loops interact
•And now let us simulate a couple examples
379

N is the number of phases being
summed at the output cap
Think about this carefully. The Iin-rms (
of a duty cycle dependent square wave)
vs Vo/Rload(DC load current). Now add
in EMI concerns and stability and
parasitics and cost and space
ή=efficiency
D=duty scale
Reasonable starting point, but you really
need to add in the emi filter, layout and
type-sim and bench required
383

Synchronous-Buck Converter Circuit
• Synchronous-Buck Converter Circuit
• Test Setup
• Test Circuit
• Synchronous-Buck Controller
• MOSFET: TPC8014
• Inductor L1: Würth Elektronik Inductor
• Capacitor C9: 820uF (25V)
• Switching Waveform
• High Side MOSFET(QH): VGS, VDS, ID
• Low Side MOSFET(QL): VGS, VDS, ID
• Gate Drive Signal
• VIN-VOUT
• VOUT,RIPPLE
• Output Inductor Voltage and Current
441

Synchronous-Buck Converter Circuit
Duty Cycle (D)
≈ Vin/Vout,
D = 0.368
442

Test Setup
Test Circuit
Power Supply:
VCC 12V
VIN 5V
Measurement Waveform
443

Test Circuit Schematic
444
Synchronous-Buck Converter using TPS5618 controller from Texas Instruments

Test Circuit (Breadboard)
Controller
Q1
Q2
445

Test Circuit (Top View)
446
L1
C9
C10
Controller

Synchronous-Buck Controller (1/2)
Synchronous-Buck Controller Circuit with IC
TPS5618 from Texas Instruments
Synchronous-Buck Controller Block Model
(Open Loop Setting)
• The Syn-Buck_Ctrl is a block model that generates gate drive pulse signal to control MOSFET
switches of the Synchronous-Buck Converter. The duty cycle, switching frequency, and the
switching dead-time are input into the model to match the real circuit.
HIDR
LODR
High side gate driver
Low side gate driver
447

Synchronous-Buck Controller (2/2)
V1
TD = {1/FREQ}
TF = 1n
PW = {D/FREQ}
PER = {1/FREQ}
V1 = 0
TR = 1n
V2 = 1.709
PARAMETERS:
FREQ = 152kHz
D = 0.36
tdly = 80n
0
Rdly 1
1k
N4
CHDR
1nCdly 1
{tdly /1k}
0
0
Rdly 2
1k
N3
0
Cdly 2
{tdly /1k}
HDR
LDR
N1
U1
AND2_ABM
VOH = 12
VOL = 0
Dclmp
DHDR1
U2
AND2_ABM
VOH = 8
VOL = 0
N2
N5
Dclmp
DHDR2
N7
RHDR1
0.01
U5
INV_ABM
VOH = 1.709
VOL = 0
RHDR2
0.01
N6
Pulse
Control
Signal
Dead-time
generator
The Syn-Buck_Ctrl Equivalent Circuit
Parameters
• FREQ = Switching frequency, set to match
the measurement switching frequency.
• D = Duty Cycle, calculated by D≈VOUT/VIN
• tdly = HDR and LDR dead-time, the tdly is set
to match the measurement dead time value.
Gate drive signal (measurement)
1/frequency
Dead-time, the time
when QH and QL
are both off
448

MOSFET: TPC8014 (1/2)
TPC8014 LTSpice Symbol
Device mounted on an epoxy board
*$
*PART NUMBER: TPC8014
*MANUFACTURER: TOSHIBA
*VDSS=30V, ID=11A
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2011
.SUBCKT TPC8014 1 2 3 4 5 6 7 8
X_U1 6 4 3 MTPC8014_p
X_U2 4 3 DZTPC8014
X_U3 3 6 DTPC8014_p
R_R1 1 3 0.01m
R_R2 2 3 0.01m
R_R5 5 6 0.01m
R_R7 7 6 0.01m
R_R8 8 6 0.01m
.ENDS
*$
449

MOSFET: TPC8014 (2/2)
1. *$
2. .SUBCKT MTPC8014_p D G S
3. CGD 1 G 1.7n
4. R1 1 G 10MEG
5. S1 1 D G D SMOD1
6. D1 2 D DGD
7. R2 D 2 10MEG
8. S2 2 G D G SMOD1
9. M1 D G S S MTPC8014
10. .MODEL SMOD1 VSWITCH
11. + VON=0V VOFF=-10mV RON=1m ROFF=1E12
12. .MODEL DGD D (CJO=0.950E-9 M=.52396 VJ=.54785)
13. .MODEL MTPC8014 NMOS
14. + LEVEL=3 L=720.00E-9 W=.45 KP=66.000E-6 RS=1.0000E-3
15. + RD=6.8436E-3 VTO=2.3063 RDS=3.0000E6 TOX=40.000E-9
16. + CGSO=2.7726E-9 CGDO=1E-12 RG=22.95
17. + CBD=342.86E-12 MJ=.70573 PB=.3905
18. + RB=1 N=5 IS=1E-15 GAMMA=0 KAPPA=0 ETA=0.5m
19. .ENDS
20. *$
*$
1. .SUBCKT DTPC8014_p A K
2. R_R2 5 6 100
3. R_R1 3 4 1
4. C_C1 5 6 195p
5. E_E1 5 K 3 4 1
6. S_S1 6 K 4 K _S1
7. RS_S1 4 K 1G
8. .MODEL _S1 VSWITCH
9. + Roff=50MEG Ron=100m Voff=90mV Von=100mV
10. G_G1 K A VALUE { V(3,4)-V(5,6) }
11. D_D1 2 K DTPC8014
12. D_D2 4 K DTPC8014
13. F_F1 K 3 VF_F1 1
14. VF_F1 A 2 0V
15. .MODEL DTPC8014 D
16. + IS=824.87E-12 N=1.2770 RS=6.2420E-3 IKF=7.3139
17. + CJO=3.0000E-12 BV=60 IBV=100.00E-6 TT=24.062E-9
18. .ENDS
19. *$
20. .subckt DZTPC8014 1 2
21. D2 1 3 DZ2
22. D1 2 3 DZ1
23. .model DZ1 D
24. + IS=0.01p N=0.1 ISR=0
25. + CJO=3E-12 BV=22.423 IBV=0.001 RS=0
26. .model DZ2 D
27. + IS=0.01p N=0.1 ISR=0
28. + CJO=3E-12 BV=22.423 IBV=0.001 RS=411.11
29. .ENDS
30. *$
450

Inductor L1: Würth Elektronik Inductor
*$
*PART NUMBER: L7447140
*MANUFACTURER: Würth Elektronik
*All Rights Reserved Copyright (c) Bee Technologies Inc. 2011
.SUBCKT L7447140 1 2
R_RS 1 N1 10.366m
L_L1 N1 2 4.84796uH
C_C1 N1 2 0.357pF
R_R1 N1 2 15.3375k
.ENDS
*$
LTSpice Symbol
Würth Elektronik Inductor part no. 7447140
451

Capacitor C9: 820uF (25V)
*$
*PART NUMBER: EEUFM1E821L
*MANUFACTURER: Panasonic
*CAP=820uF, Vmax=25V
*All Rights Reserved Copyright (C) Bee Technologies Inc. 2011
.SUBCKT C820U 1 2
L_L1 1 N1 8.16935nH
C_C1 N1 N2 812.73uF
R_R1 N2 2 15.695m
.ENDS
*$
LTSpice Symbol
Capacitor 820uF (25V)
452

Switching Waveform
Measurement Simulation
V(Vout)
I(L1)
VDS(Q1)
V(Vout)
I(L1)
VDS(Q1)
453

High Side MOSFET(QH): VGS, VDS, ID
ID(Q1)
VDS(Q1)
VGS(Q1)
ID(Q1)
VDS(Q1)
VGS(Q1)
454

Low Side MOSFET(QL): VGS, VDS, ID
ID(Q2)
VDS(Q2)
VGS(Q2)
ID(Q2)
VDS(Q2)
VGS(Q2)
455

Gate Drive Signal
VGS(Q2)
VGS(Q1)
VGS(Q2)
VGS(Q1)
456

VIN – VOUT
VOUT
VIN
VOUT
VIN
457

VOUT,RIPPLE
VOUT,RIPPLE VOUT,RIPPLE
458

Output Inductor Voltage and Current
V(L)
I(L)
V(L)
I(L)
459

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