VLSI Physical Design Flow(http://www.vlsisystemdesign.com)

Kunal Promode Ghosh
M.Tech (IIT Bombay)
9/11/2012 http://www.vlsisystemdesign.com/ 1

Physical Design (PD) Flow

• Physical Design Flowchart (What to do ?, Why to do ?
And How to do ? in Physical Design)
• Physical Design Learning Methodology

1. Physical Design Flow (What to do?)
2. Fundamentals Related to Flow (Why to do?)
3. PD Tools Introduction (How to do?)

9/11/2012 www.vlsisystemdesign.com 2

Physical Design (PD) Flow


What to do?

1. A 'core' is the section of the chip
where the fundamental logic of Hcore Hdie
the design is placed.

2. A ‘die’, is small semiconductor
material specimen on which the
fundamental circuit is fabricated. Die
Wcore
Core
Wdie
Define Width & Height of Core & Die


What to do?

1. The preplaced cells are the
critical cells, related to clocks, viz. Clock Mux
clock buffers, clock mux, etc. and
Output
also few other cells such as Clock
RAM's, ROM's etc. Buffer

Input
2. These cells are placed into core Clock
before placement and routing Buffer Die
stage, and hence are called
'preplaced cells'.
Core

Define Locations of Pre-Placed cells


What to do?

Decap

Decap
Decap
1. A decoupling capacitor is used to
decouple the critical cells from Clock Mux
Decap
main power supply, in order to

Decap
Decap
Output
protect the cells from the Decap
Clock
disturbance occurring in the Decap Buffer
power distribution lines and

Decap
Decap
Decap
Input
source Clock
Buffer Die
2. The purpose of using decoupling Decap
capacitors is to deliver required
current to the gates during Core
switching
De-Coupling Capacitors surrounding
Pre-placed Cells

What to do?

Decap

Decap
Decap
1. While drawing any circuit Clock Mux
Decap
on paper, we have only one

Decap
Decap
'vdd' at the top and one Decap
Output
Clock
'vss' at the bottom
Decap Buffer

Decap
Decap
Decap
2. But on a chip, it becomes Input
necessary to have a grid Clock
Buffer Die
structure of power, with
Decap
more than one 'vdd' and
'vss' Core

Power Planning


What to do?

Decap

Decap
Decap
Decap

Decap
Decap
Output
Clock
'vss' at the bottom
Decap Buffer

Decap
Decap
Decap
Buffer Die
Decap
'vss' Core

Power Planning
Vdd
Vss

What to do?

X X X X X

Decap
X X X X X

Decap
Decap
1. While drawing any circuit X X
Clock Mux X X X
Decap

Decap
Decap
X X X X X

Output
X X X X X
Clock
'vss' at the bottom
X DecapX X
Buffer
X X

Decap
Decap
Decap
2. But on a chip, it becomes X Input
X X X X

X X X X X
Buffer Die
structure of power, with X X X X X
Decap
X X X X X
'vss' Core

Vdd Power Planning
Vss

What to do?

1. The space between core and die is
reserved for pin placement. For eg.
an 8085 has around 40 pins viz.
reset, AD0, AD1, etc.

2. The clock pins are wider compared
to other pins on the chip, as it
drives most of the logic inside the
chip.


What to do?

1. To avoid the placement of cells by
placement tools, in the area
between core and die (which is
reserved for pin placement), it
needs to be blocked by logical cell
placement blockages


What to do?

1. The ‘Clk’ should be distributed to
all flops in such a way that the
skew is minimal

2. ‘Skew’ is the relative delay
between clocks reaching at each
flop on chip.


What to do?


What to do?

1. Engineering Change Order (ECO) is the process of modifying the PNR netlist in
order to meet timing (i.e. setup, hold, transition and max_capacitance)
requirements

2. For eg. if there's a setup violation in the design, it implies that a combinational
path has large delay than required. In this case, we need to reduce the delay by
upsizing cell, which reduces resistance, in turn, reduces RC delay of the path.

3. Refer to diagrams in following slides to understand how to modify delay of cells.
Inverter has been taken as an example.


What to do?


What to do?
Propagation Delay of inverter

TPHL need not be equal to TPLH


What to do?


Why to do?

1. The abstract level behavioral
description of the processor is
written using an RTL program.

2. Large designs (e.g. microprocessor
in our case) are usually
synthesized into small modules.

3. These modules are the basic
building blocks of a
microprocessor e.g. memory unit,
adder/subtractor (ALU) unit,
multiplexer unit, etc.


Why to do?

1. The arrangement shown in left
occupies minimum area, whereas
the one on the right occupies
larger area on chip, and hence
facilitates the user to add more
blocks (i.e. additional functionality)
in to the chip.

2. If, the specifications demands for
minimum area, the left
arrangement is selected, whereas,
if the specification demands
decent area as well as additional
functionality, the second
arrangement is selected.

Why to do?

1. Noise margin is the amount of noise that a CMOS
circuit could withstand without compromising the
operation of circuit.

2. Noise margin does makes sure that any signal which
is logic '1' with finite noise added to it, is still
recognised as logic '1' and not logic '0'.


Why to do?

NML (NOISE MARGIN low) = VIL - VOL = Vss' - 0 = Vss‘

NMH (NOISE MARGIN high) = VOH - VIH = Vdd - Vdd'

Why to do?

1. If the wires were
ideal, i.e. 'zero'
resistance, 'zero'
inductance and
infinitely short, thus
no issue of power
distribution


Why to do?

1. Consider capacitance to be
zero for the discussion. Rdd,
Rss, Ldd and Lss are well
defined values.

2. During switching operation,
the circuit demands
switching current i.e. peak
current (IPEAK).

3. Now, due to the presence of
Rdd and Ldd, there will be a
voltage drop across them and
the voltage at Node 'A' would
be Vdd' instead of Vdd.

Why to do?

Switching Activity of CMOS Circuit.


Why to do?


Why to do?

1. When input of the inverter
switches from logic '1' to logic
'0', output of inverter should
switch from logic '0' to logic '1'.

2. This essentially means that the
output capacitance of inverter
should charge till the supply
voltage Vdd'.

3. But if Vdd' goes below the
noise margin, due to Rdd and
Ldd, the logic '1' at the output
of inverter wont be detected
Vdd - Vdd' = Ipeak*Rdd + Ldd * (dI/dt)
as logic '1' at the input of the
circuit following the inverter.

Why to do?

Solution
1. Keep Rdd and Rss minimum
by increasing width of wire.
2. Keep peak current Ipeak and
change in current (dI/dt) as
small as possible.

Icap = CL * dV / dt
Ipeak = CL * (Vdd – 0) / (tr - 0)
Ipeak = CL * (Vdd) / (tr )
dI/dt = CL * Vdd / tr2
3. Limit the rise time (tr). If a
circuit could run at 500 ps,
its unnecessary to run the
circuit at 300 ps. The largest
possible value of tr should be Vdd - Vdd' = Ipeak*Rdd + Ldd * (dI/dt)
selected.

Why to do?

1. Addition of Decoupling
Capacitor in parallel with
the circuit

2. Everytime the critical cell (in
above daigram,an inverter)
switches, it draws current
from Cd , whereas, the RL
network is used to replenish
the charge into Cd


Why to do?

1. The ‘Clk’ should be distributed to
all flops in such a way that the
skew is minimal

2. ‘Skew’ is the relative delay
between clocks reaching at each
flop on chip.


Why to do?


Why to do?

In deep sub-micron technology (i.e. <130nm) and below, the lateral capacitance
between nets/wires on silicon, becomes much more dominant than the interlayer
capacitance.


Why to do?


Why to do?

1. The disturbance at 'A' can potentially cause
a disturbance at 'V', because of the mutual
coupling capacitance.

2. If the disturbance at 'V' crosses noise
threshold of the receiving gate 'R', then it
may change the logic at the output of 'R'


Why to do?


Why to do?

1. If both 'A' and 'V' nodes have signal
switching event at the same time
interval, then, due to noise induced
by signal transition at agressor 'A', a
change in the timing instant of the
signal transition occurs at 'V‘

2. Due to this, the propagation delay
of the driver 'D' increases by 'dt'
amount of time, thus increasing the
overall propagation delay of the
circuit, which might lead to
potential setup violation.


Why to do?

Crosstalk Modeling and Analysis


Why to do?



Why to do?

Therefore, we have 3 solution.
1) Controlling Peak Voltage (Vp)


Why to do?

2) Tuning Pulse Width


Why to do?

3) Shielding


Why to do?

The common component between the flip-flops X, Y and Z is the 'clock'.


Why to do?

1. Correctness of the system can be judged by
tracing each Sender - Receiver pair.
2. Assume, identical clock goes to both and
there's some delay between Sender and
Receiver
3. This delay will not be fixed as the effective load
capacitance seen by each gate in the design is
different
4. Other factors that affect the delay of a gate
such as input transition, threshold voltage,
drive strength, etc.


Why to do?


Why to do?

Setup time (S) = Data input ‘D’ must be valid before clock transition
Hold time (H) = Data input ‘D’ must remain valid after clock edge


Why to do?



Why to do?

Mux2

Mux1
D Q 0
1 Q
F/F
1
0 QM
D
CLK

CLK
Positive Edge Triggered ‘D’ F/F



Why to do?

Mux2
Mux1

0
1 Q
1
0 QM
D

CLK Positive Edge Triggered ‘D’ F/F
Hence Setup Time => Time required (before clk edge) for ‘D’ to reach QM
i.e. internal delay of Mux1
Hence Hold Time => Time required (after clock edge) for QM to reach ‘Q’
i.e. internal delay of Mux2

Why to do?

m > H i.e. Minimum propagation delay of the combinational logic should be greater than
Hold Margin


Why to do?

1. If m < H , it results into timing violation,
called as Hold violation.

2. This means, that the combinational logic
delay is very less and hence data change is
very fast.

3. To satisfy the 'hold' requirement, the
combinational logic delay should be
increased.


Why to do?

M < Tclk - S i.e. Maximum propagation delay of the combinational logic should be less
than Clock period (Tclk) minus the Seup Margin


Why to do?

1. If M > Tclk - S , it results into timing
violation, called as Setup violation.

2. This means, that the combinational logic
delay is very large and hence data change
is very slow.

3. To satisfy the 'setup' requirement, the
combinational logic delay should be
decreased.


Why to do?

m > H + Δ1 i.e. Minimum propagation delay of the combinational logic should be
greater than Hold Margin + the clock network delay for sender

Why to do?

M < (Tclk - S) + Δ2 i.e. Maximum propagation delay of the combinational logic should be less
than Clock period (Tclk - Setup Margin ) + clock network delay for receiver i.e. Δ2

Why to do?


How to do?
General Tools Used for Placement and Routing

1. Synopsys ICC
2. Magma Talus
3. Cadence First Encounter
4. Mentor Graphics

General Tools Used for RC parasitics Extraction

1. Synopsys StarXT

General Tools Used for STA and noise Analysis

1. Synopsys Primetime
2. Synopsys Primetime SI


Thank You

For queries mail us:
vsd@vlsisystemdesign.com


VLSI Physical Design Flow(http://www.vlsisystemdesign.com)

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