chameleon chip

Chameleon Chip PRESENTED BY:- NAME:- Sucharita Bohidar ROLL NO:-10031016 BRANCH:- 1 st Semester MCA

CONTENTS 1.Introduction 2.Multifunction Implementation 3.The General Architecture Of Reconfigurable Processor 4.Architecture of Chameleon Chip 5.Reconfigurable Processing Fabric 6.Programmable I/O 7.Technologies Used In Chip 8.Design Process 9.Comparison With Other Technologies 10.Advantages 11.Disadvantages 12.Applications 13.Conclusion

[object Object],[object Object],[object Object],[object Object],[object Object],1.Introduction

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2.Multifunction Implementation ,[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],3.The General Architecture Of Reconfigurable Processor

4.Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

5.Reconfigurable Processing Fabric(RPF) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

6.Programmable I/O ,[object Object],[object Object],7.Technologies Used In Chip 1. eCONFIGURABLE™ TECHNOLOGY: This technology reconfigures fabric in one clock cycle and increases voice/data/video channels per chip. As mentioned earlier, each Slice can be configured independently. Loading the Background Plane from external memory requires just 3 µsec per Slice; this operation does not interfere with active processing on the Fabric. Swapping the Background Plane into the Active Plane requires just one clock cycle. with eConfigurable Technology; the four algorithms are loaded into the entire reconfigurable processing Fabric one at a time.

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8. DESIGN PROCESS eBIOS C SOURCE CODE VERILOG SOURCE CODE LIBRARY C COMPILER SYNTHESISER OBJECT CODE LAYOUT LINKER CHAMELEON EXECUTABLE CONFIGURATION BITS HARDWARE CHANGE

9.Comparison With Other Technologies ,[object Object],[object Object]

COMPARISON WITH OTHER TECHNOLOGIES(tabular representation) RCP ASIC FPGA FLEXIBILITY HIGH LOW HIGH COST LOW LOW HIGH PERFORMANCE HIGH HIGH MEDIUM TIME-TO-MARKET MEDIUM LONG MEDIUM

10.Advantages ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

12.Applications ,[object Object],[object Object],[object Object],[object Object]

13.Conclusion These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the outmost speed. Its applications are in, data-intensive Internet,DSP,wireless basestations, voice compression, software-defined radio. Its advantages are that it can create customized communications signal processors ,it has increased performance and channel count, and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk.

chameleon chip

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