from OO to Multicore SST. An overview of SST describing Checkpoint and Transactional Memory Support for ROCK

1. From Superscalar OO to Multicore SST Checkpoint and Transactional memory support for SST © dave+stratusdesign@gmail.com stratusdesign.squarespace.com

13. SST logic Wakeup Behind Thread DQ Full? DQ Empty for current & spec ckpt? L1 Miss Set ‘ S ’ bit in Cache Start Behind thread in wait mode to handle Defers Start Executing Main thread Speculatively ahead Behind Thread Runs Thru DQ for Active Checkpoint Done Ahead Thread • Normal Mode Behind Thread • Pause L1 Resolved Ahead Thread • Scout Mode Behind Thread • Pause High Level SW initiates a Memory Transaction Restore Checkpoint Tx Fail ‘ S ’ bit Detect Mem Order Violation Br Mispredict Exception WAIT Begin SST Episode Arch Checkpoint Active • Architectural Inactive • Speculative Instr has Data Dependencies? Execute Instr and Retire OO Enqueue DQ with Instr & All Resolved Opr Instr has no Data Dependencies? WAIT more data expected Speculation Successful Program Execution resumes were speculation finished

14. SST scheduling Program Order LDX addr1, %r1 ADD %r1, 0x04, %r2 STX %r2, addr2 SETHI 0x01, %r2 STX %r2, addr3 etc.. ; Ahead-Thread 1 LDX addr1, %r1 ; Load Miss on addr1, Defer and set R1 [ NT ]) To Defer Q ; Checkpoint Start Ahead-Thread, Behind-Thread Waits for data read 2 ADD %r1, 0x04, %r2 ; Source Operand has NT bit set Defer and set R2 [NT] To Defer Q 3 STX %r2, addr2 ; Source Operand has NT bit set Defer) To Defer Q 4 SETHI 0x01, %r2 ; Ahead Thread Executes Independently) 5 STX %r2, addr3 ; Ahead Thread Executes Independently & continues speculative execution of more program instructions ; Load Miss resolves start Behind-Thread 6 ADD %r1, 0x04, %r2 [NT=0,SNT=1] ; NT was reset at 4, set waw bit 7 STX %r2, addr3 SST Order LDX addr1, %r1 ADD %r1, 0x04, %r2 STX %r2, addr2 SETHI 0x01, %r2 STX %r2, addr3 etc.. Deferring data-dependent instructions prevents RAW – here %r2 was read at 3 but written before at 2 Saving operands in DQ prevents WAR as any valid data in register at that time is captured and saved for Behind-Thread to use later regardless of future writes by Ahead-Thread Registers with WAW bit not committed to Architectural state – here %r2 was written at 4 & 6 ;Deferred Queue LDX addr1, %r1 [ NT ] ADD %r1 [ NT ], 0x04, %r2 [ NT ] STX %r2 [ NT ] , addr2 WAW WAR RAW