logic gates implementation in verilog hdl

1. 2. write a verilog code for half adder and full adder
module hfadr(a, b, sum, cr);
input a;
input b;
output sum;
output cr;
assign sum = a ^ b;
assign cr= a & b ;
endmodule
// alternate code for half adder
module hfadr(a, b, sum, cr);
input a;
input b;
output sum;
output cr;
xor x1 (sum ,a, b);
and a1 (cr,a,b);
endmodule
//verilog code for full adder
module fadr(a, b, c, sum, cr);
input a;
input b;
input c;
output sum;
output cr;
wire t ;
assign t = a^b;
assign sum = t^c;
assign cr = ( a & b)| (a&c)|(c &b);
ull
endmodule
// alternate code for full adder
module fadr(a, b, c, sum, cr);
input a;
input b;
input c;
output sum;
output cr;
wire [4:0] t;
xor x1 ( t[0],a ,b); // t[0]= a xor b
xor x2 ( sum,t[0],c );// sum = t[0] xor c = a xor b xor c
and a1( t[1], a , b);// ab
and a2 (t[2], c , b);// bc
and a3 (t[3], a, c);// ca
or o1 ( t[4], t[1], t[2]);// ab+bc
or o2( cr , t[3],t[4]); // cr= ab+bc+ca
endmodule