2016年2月20日(金)のZynq Ultrasclae+ MPSoC 勉強会で使った資料です。
追記) 2016.05.08
公式ARM Trusted Firmwareのサイトに、Zynq UltraScale+ MPSoCの実装が追加されていていることを明記した
This is the material I used at Zynq Ultrasclae + MPSoC SIG on 20th February (Friday).
Addendum) 2016.05.08
We stated that the implementation of Zynq UltraScale + MPSoC was added to the official ARM Trusted Firmware site.
2. 自己紹介
Twitter ID :@Vengineer 2009年〜
Blog :@Vengineerの戯言 2007年〜
http://blogs.yahoo.co.jp/verification_engineer
:昭和の時代(1987年)〜 C++を書いているプログラマ
AT&T C++ Translator => Zortech C++ … GCC/Intel/LLVM
:「SystemVerilog設計スタートアップ(2008年)」の中の人のひとり
http://www.cqpub.co.jp/hanbai/books/36/36191.htm
3. ZynqMP:参考資料
1)、Zynq UltraScale+ MPSoC Technical Reference Manual,
UG1085 (v1.0) November 24, 2015
2)、Zynq UltraScale+ MPSoC Software Developers Guide,
UG1137 (v1.0) November 18, 2015
3)、Xilinx Github : https://github.com/xilinx
4)、Xilinx Wiki : http://www.wiki.xilinx.com/
5)、QEMU User Guide, UG1169 (v1.0) November 18, 2015
4. ZynqMPの特徴
参考文献1)、P.11
• Scalable PS with scaling for power and performance
• Low-power running mode and sleep mode
• Flexible user-programmable power and performance scaling
• Advanced configure system with device and user-security support
• Extended connectivity support including PCIe®, SATA, and USB 3.0
• Advanced user interface(s) with GPU and DisplayPort in the PS
• Increased DRAM and PS-PL bandwidth
• Improved memory traffic QoS
• Improved safety and reliability
16. PMU : Platform Management Unit
参考文献1)、Chapter 6
The platform management unit (PMU) controls the power-up, reset, and monitoring
of resources within the entire system. Earlier power management mechanisms were
implemented using hardware state machines. Modern MPSoCs include a dedicated
centralized and user-programmable processor for power management to reduce
risk and increase scalability. The Zynq® UltraScale+™ MPSoC PMU performs the
following set of tasks.
• Initialization of the system during boot.
• Management of power gating.
18. PMUって何だ?
参考文献1)、PMU System-level View, Page.89-90, Figure 6-1
• Dedicated, fault-tolerant triple-redundant processor.
• ROM to hold PMU ROM code that includes the PMU startup sequence, routines
to handle power-up or down requests, and interrupts.
• 128 KB RAM with ECC used as the storage for data and also the optional
user/firmware code.
どうやら、PMU Processorというものがある。
20. で、ブートシーケンスは?
参考文献2)、Chapter 7、Page.73、Detailed Boot Flow
1. Determines the boot mode by reading the boot mode register, which captures the
boot-mode pin strapping at the POR.
2. Initializes the OCM.
3. Reads the boot header. <= ブートデバイスにアクセスする
4. If the FSBL in the boot image is authenticated, the SHA engine checks for its
authentication. If the FSBL passes the authentication test, the configuration unit
checks if the FSBL is encrypted. In case the FSBL is encrypted, AES-GCM engine
decrypts the FSBL and configuration unit loads it into the OCM of either APU or
RPU and FSBL handoff to APU/RPU software.
22. FSBLは何をする?
参考文献2)、Chapter 7、Page.73、Detailed Boot Flow
・Load FSBL to OCM
・FSBL configures the PS
・FSBL configures the PL with the bitstream
・FSBL loads the RPU software
・FSBL loads ths AP software
・FSBL handoff to AP software
23. FSBL
参考文献3)、embeddedsw/lib/sw_apps/zynqmp_fsbl/ data/zynqmp_fsbl.tcl
proc swapp_get_description {} {
return "First Stage Bootloader (FSBL) for Zynq Ultrascale+ MPSoC. The FSBL configures the FPGA with HW bit stream (if it exists)
and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the
non-volatile memory (NAND/SD/QSPI) to RAM (DDR) and takes A53/R5 out of reset. It supports multiple partitions,
and each partition can be a code image or a bit stream.";
}
proc swapp_get_supported_processors {} {
return "psu_cortexa53 psu_cortexr5";
}
# based on the CPU (A53 64-bit, A53 32-bit or R5),
25. MPSoC Non Secure Boot
参考文献4)、MPSoC+Non+Secure+Boot
The purpose of this page is to describe booting of QEMU in Non-Secure
mode using the following boot devices:
- QSPI24
- NAND
- SD
各種デバイスに対するブートイメージを作成し、QEMUで動作確認しています。
Secure Bootに関しては、
まだ書かれていないようです。
43. ARM64のパワーマネージメント
Linux Kernel Power Management Framework for ARM 64-bit Processors
L.Pieralisi、21/8/2014 - LinuxCon North America 2014
http://events.linuxfoundation.org/sites/events/files/slides/lp-linuxcon14.pdf
HKG15-404: Standardizing Linux Kernel Power Management on ARM
32/64-bit
https://www.youtube.com/watch?v=YB7W-v1At4o
PSCI (Power State Coordination Interface)
46. EL3 Runtime Service
参考資料)3、arm-trusted-firmware/blob/master/docs/rt-svc-writers-guide.md
Software executing in the normal world and in the trusted world at exception levels lower
than EL3 will request runtime services using the Secure Monitor Call (SMC) instruction.
These requests will follow the convention described in the SMC Calling Convention PDD
(SMCCC). The SMCCC assigns function identifiers to each SMC request and describes how
arguments are passed and results are returned.
・Standard Service calls => 標準サービスの提供 ( PSCI )
・SiP Service calls => Xilinx独自サービスの提供
47. Standard Service calls : PSCI
参考資料)、http://infocenter.arm.com/help/topic/com.arm.doc.
den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
・POWER STATE COORDINATION INTERFACE の略
このドキュメントを読めばいいよ!
51. Sip Service calls:PM-API (Xilinx独自)
参考資料)3、linux-
xlnx/blob/master/Documentation/devicetree/bindings/soc/xilinx/zynq_mpsoc.txt
Zynq MPSoC based systems rely on the "psci" node to detect the presence of PMU
firmware as well as to determine the calling method (either "smc" or "hvc")
to the PM-API firmware layer.
zynqmp.dti
firmware {
compatible = "xlnx,zynqmp-pm";
method = "smc";
};
53. LinuxからATFへはどのように伝える?
参考資料)3、linux-xlnx/blob/master/drivers/soc/xilinx/zynqmp/pm.c
static int invoke_pm_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload)
* Invoke power management function for SMC or HVC call, depending on configuration
* Following SMC Calling Convention (SMCCC) for SMC64:
* Pm Function Identifier,
* PM_SIP_SVC + PM_API_ID
* PM_SIP_SVC - Registered ZynqMP SIP Service Call
* PM_API_ID - Power Management API ID
65. 再び、PMUのお仕事
参考文献1)、Chapter 6
The platform management unit (PMU) controls the power-up, reset, and monitoring
of resources within the entire system. Earlier power management mechanisms were
implemented using hardware state machines. Modern MPSoCs include a dedicated
centralized and user-programmable processor for power management to reduce
risk and increase scalability. The Zynq® UltraScale+™ MPSoC PMU performs the
following set of tasks.
• Initialization of the system during boot.
• Management of power gating.
66. IPI : Inter-Processor Interrupt (ATF側)
参考資料)1、P.189
参考資料)3、arm-trusted-firmware/blob/master/plat/xilinx/zynqmp/pm_service/pm_ipi.c
pm_ipi_init() - Initialize IPI peripheral for communication with PMU
pm_ipi_send_sync() - Sends IPI request to the PMU
pm_ipi_send() - Sends IPI request to the PMU
pm_ipi_send_common() - Sends IPI request to the PMU
pm_ipi_buff_read() - Reads IPI response after PMU has handled interrupt
pm_ipi_wait() - wait for pmu to handle request
ipi_fiq_handler() - IPI Handler for PM-API callbacks
67. IPI : Inter-Processor Interrupt (PMUFW側)
参考資料)3、embeddedsw/tree/master/lib/sw_apps/zynqmp_pmufw/src/xpfw_user_startup.c
static void PmIpiHandler(const XPfw_Module_t *ModPtr, u32 IpiNum, u32 SrcMask)
{
switch (IpiNum) {
case 0:
isrVal = XPfw_Read32(IPI_PMU_0_ISR);
ipiStatus = XPfw_PmCheckIpiRequest(isrVal, &apiId);
if (XPFW_PM_IPI_IS_PM_CALL == ipiStatus) {
/* Power management API processing */
status = XPfw_PmIpiHandler(isrVal, apiId, &isrClr);
if (XST_SUCCESS == status)
XPfw_Write32(IPI_PMU_0_ISR, isrClr);
73. PmProcTrActiveToSuspend
参考資料)1、P.97(PMU GPI2 : GPI2 monitors power control requests)
参考資料)3、embeddedsw/tree/master/lib/sw_apps/zynqmp_pmufw/src/pm_proc.c
static int PmProcTrActiveToSuspend(PmProc* const proc)
{
PmDbg("ACTIVE->SUSPENDING %sn", PmStrNode(proc->node.nodeId));
/* Enable/disable macros for processor's wfi event in GPI2 register */
#define ENABLE_WFI(mask) XPfw_RMW32(PMU_LOCAL_GPI2_ENABLE, mask, mask);
ENABLE_WFI(proc->wfiEnableMask);
proc->node.currState = PM_PROC_STATE_SUSPENDING;
return XST_SUCCESS;
}
74. WFI
ARM®
Compiler armasm User Guide, Version 6.3
http://infocenter.arm.com/help/topic/com.arm.doc.dui0801d/pge1427897721360.html
lib/sw_apps/zynqmp_pmufw/src/pm_proc.c
Wait For Interrupt is a hint instruction that permits the PE to enter a low-power state until
one of a number of asynchronous event occurs.
● Traps to EL1 of EL0 execution of WFE and WFI instructions.
● Traps to EL2 of Non-secure EL0 and EL1 execution of WFE and WFI instructions.
● Traps to EL3 of EL2, EL1, and EL0 execution of WFE and WFI instructions.