2. Introduction
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Skakti is a family of processors being developed
by the CAS Lab at IIT Madras
The RISC-V ISA from UC Berkeley was chosen
since it is open, patent free (outside India) and
well supported by OS and toolchains
While the ISA will be standard across the Shakti
family, implementations will have different
micro-architectures and a total of 7-8 classes of
devices are planned.
12/11/13
Computer Architecture and Systems Lab, CSE Dept., IIT Madras
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3. Shakti Variants
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Since the Shakti series of processors span across a vast
range of functionality, ranging from microcontrollers to 100
core HPC processors, a single microarchitecture will not
suffice
So initially six microarchitecture variants are being proposed.
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Each variant will in turn have sub-variants catering to varying
requirements in that segment
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The micro-architecture will not vary significantly but a set of
functional blocks will be optioal on top of a base set
12/11/13
Computer Architecture and Systems Lab, CSE Dept., IIT Madras
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4. Shakti Variants
C class microcontrollers
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32 bit 3-5 stage in-order variant aimed at 50-200 Mhz microcontroller variants
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Unified L1 cache/Scratchpad RAM, optional memory protection
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very low power , static design
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Fault tolerant variants for ISO 26262/IEC61508/EN50128 applications
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HW multiply/divide, Security Module
I class processors
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32/64 bit, 1-4core, 5-8 stage in-order/minimal out of order, 200-800Mhz, L1/L2 cache
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industrial control / general purpose applications
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Optional MMU, FP/SIMD, AXI bus, SMT, fault tolerant variants, LPAE, Security Module
M Class processors
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Mobile and GP computing - 64 bit, 1-8core, 8-13 stage OO, 800Mhz-2.5 Ghz, L1/L2 cache
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128/256 bit AXI, SMT, FP/SIMD, Virtualization, Security Module
12/11/13
Computer Architecture and Systems Lab, CSE Dept., IIT Madras
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5. Shakti Variants
S class processors
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64 bit superscalar, multi-threaded variant for desktop/server applications
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1-3Ghz, 2-16 cores, crossbar interconnect, segmented L3 cache, Virtualization
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RapidIO based external CC interconnect, optional Hybrid Memory Cube support, 256/512
bit SIMD, security module
H class processors
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64 bit in-order, multi-threaded, HPC variant with 32-256 cores
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512 bit SIMD, SRIO based external CC interconnect
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Power optimal internal NoC interconnect
T class processors
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experimental security oriented 64 bit variants with tagged ISA, single addres space
support, fat pointers, HW based capability support
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decoupling of protection from memory management
12/11/13
Computer Architecture and Systems Lab, CSE Dept., IIT Madras
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6. SW toolchain
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Standard GCC + Linux for MMU variants
SRIO based lightweight message passing for
MPI type applications
L4 OS support on MMU and non-MMU variants
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12/11/13
Trusted variant requires mandatory use of L4 as VM
Computer Architecture and Systems Lab, CSE Dept., IIT Madras
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