2. 1. Draw the complete Microprocessor system block
diagram with Address decoder having 2x1Kx8
RAM that can be used for 16-bit operation
starting at the Address FF000h.
9. :
mov al, 55
mov dx, 0F000h
out dx, al
:
74LS245
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
E DIR 5V
543210
A
1
A
1
A
1
A
1
A
1
A
1
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IOW
via bidirectional
8086
Minimum
Mode
A18
A0
:
D7
D6
A19
D5
D4
D3
D2
D1
D0
What is the
problem ?
10. :
mov al, 55
mov dx, 0F000h
out dx, al
:
74LS373
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
G EN 0V
543210
A
1
A
1
A
1
A
1
A
1
A
1
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IOW
8086
Minimum
Mode
A18
A0
:
D7
D6
A19
D5
D4
D3
D2
D1
D0
12. a
b
c
g
d
e
f
Digit -abcdefg- hex Digit -abcdefg- hex
0 -1111110- 7Eh 1 -0110000- 30h
2 -1101101- 6Dh 3 -1111001- 79h
4 -0110011- 33h 5 -1011011- 5Bh
6 -1011111- 5Fh 7 -1110000- 70h
8 -1111111- 7Fh 9 -1111011- 7Bh
A -1110111- 77h B -0011111- 1Fh
C -1001110- 4Eh D -0111101- 3Dh
E -1001111- 4Fh F -1000111- 47h
15. :
mov al, 55
mov dx, 0F000h
in al, dx
:
74LS245
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
E DIR 0V
543210
A
1
A
1
A
1
A
1
A
1
A
1
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IOR
8086
Minimum
Mode
A18
A0
:
D7
D6
A19
D5
D4
D3
D2
D1
D0
Be careful to
the DIR
control
5V
16.
17. 1. Draw the complete block diagram for an 8086
Microprocessor system with 8-push button
switches and 8-LEDs.
2. Redraw the same block diagram in detail assigning
the switches address at (00020) and the LEDs
address at (00020) also .
3. Redraw the same block diagram if you have
16-switches and 16-LEDs.
18. M/IO RD WR BHE A0 A15 –A3 A2 A1 SLD1 SLD0 SLS1 SLS0
1 X X X X X X X 1 1 1 1
0 0 1 0 0 0 1 0 1 1 0 0
0 0 1 1 0 0 1 0 1 1 1 0
0 0 1 0 1 0 1 0 1 1 0 1
0 1 0 0 0 0 1 0 0 0 1 1
0 1 0 1 0 0 1 0 1 0 1 1
0 1 0 0 1 0 1 0 0 1 1 1
X X X X X X 0 X 1 1 1 1
TRUTH TABLE
19. 74LS373 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
G
EN
74LS373 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
G
EN
5
4
3
2
1
0
A 1
A 1
A 1
A 1
A 1
A 1
A9
A 8
A 7
A 6
A 5
A 4
A 3
A 2
A 1
5V
74LS245
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
E
DIR
5V
74LS245
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
E
DIR
M/ IO
WR
RD
BHE
BAD0-BAD15
SD8-SD15
DD8-DD15
DD0-DD7
SD0-SD7
8086 CPU
74LS245
SLD0
SLD1
SLS0
SLS1
IORD
IOWR
A0
20. Basic Data Read Timing
Bus Timing, Contd.
Timing for a basic Read cycle
• Can be for either memory or I/O
On the 8088:
- For memory, IO/#M = 0
- For I/O: IO/#M = 1
Bus
To Device
Or I/O Device
mP floats bus (HiZ)
mP strobes
data in
Also DT/#R = 0
21. Basic Data Write Timing
Bus Timing
Timing for a basic write cycle
• Can be for either memory or I/O
On the 8088:
- For memory, IO/#M = 0
- For I/O: IO/#M = 1
Device
strobes data in
Also DT/#R = 1
24. T1 T2 T3 T4 T1 T2 T3 Tw T4
Bus Cycle Bus Cycle
One Wait State
CLK
(RD is kept high)
Mem Write I/O Output
Status Status
A(19-16)
BHE
AD(15-0) Data Out
A
A Data Out
Latch
Address
Latch
Address
ALE
Mem I/O
M / IO
Write Write
WR
Latch
Data Latch
Data
Transmit Transmit
DT/R
Disable Enable Disable Enable
DEN
Ready Ready
Wait
READY
Valid Valid
AB(19-0)
Data Out Data Out
DB(15-0)
A,BHE
A,BHE
25. T1 T2 T3 T4 T1 T2 T3 Tw Tw T4
Bus Cycle Bus Cycle
Two Wait States
States
CLK
Status Status
A(19-16)
BHE
A,BHE
A,BHE
(WR is kept high)
Mem Read I/O Input
A Data In A Data In
AD(15-0)
Latch
Address
Latch
Address
ALE
Mem I/O
M / IO
Read Read
RD
Receive Receive
DT/R
Disable Enable Disable Enable
DEN
Ready Ready
Wait Wait
READY
Valid Valid
AB(19-0)
Data In Data In
DB(15-0)
