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VEDIC MULTIPLIER FOR "FPGA"

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SAIKRISHNA KOPPURAVURI

Vedic multiplier for FPGA based on arthimatic ckt

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 The proposed Vedic multiplier is based on the Vedic Sutras "Urdhva Tiryagbhyam Sutra” and “Nikhilam Sutra" multiplication techniques.  These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system
• • • It multiples two numbers & adds It with accumulator register. The output of the register given to one input of adder. Computes the product much quicker than conventional shifting & adding.
Vedic Multiplier Architecture
 It is faster than the booth & array multiplier…  The area needed for this very small as compared to other multiplier.  It is used in modern ‘‘Digital Signal Processing’’
 For complex multiplications, even system becomes complex…
The proposed Vedic multiplier based MAC unit proves to be highly efficient in terms of speed & area.
Submitted by RAJENDAR SAIKRISHNA SANDEEP

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