Vidyasagar Mukala is seeking a full-time position in circuit/digital design. He has a M.S. in Electrical and Computer Engineering from Georgia Tech and a B.Tech in Electronics and Communication Engineering from Vellore Institute of Technology. He has experience as a hardware engineer at Oracle and CAD engineer at Sandisk. His skills include C, C++, Java, VerilogHDL, and CAD tools like Cadence and Synopsys. He has published papers and worked on projects in computer architecture, ATPG, VLSI memory systems, and ALU design.

1. Vidyasagar Mukala
sagarthearagorn@gmail.com
http://www.sagarmukala.com/
Present Address Permanent Address
500 Mansion Ct., Apt # 305 504 B, Sector 6, Ukkunagaram
Santa Clara, CA 95054 Visakhapatnam, India 530032
(713) 410-7054 (91) 9441262798
Goal Seeking a full time position to extend my knowledge in Circuit/Digital Design and to
put to use my fine analytical abilities and problem solving skills
Education M.S. in Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA, Aug 2009 - Dec 2010
GPA 3.8/4.0
B.Tech. in Electronics and Communication Engineering,
Vellore Institute of Technology, Vellore, India, May 2005 - Apr 2009
GPA 9.16/10.00
Computer Languages: C, C++, Java, HTML, VerilogHDL
Skills Scripting: Perl, PHP, Tcl
Cadence Design Tools: Virtuoso, RTL Compiler
Mentor Graphics Design Tools: Modelsim, Calibre-Layout, DRC, LVS, PEX
Synopsys Design Tools: HSpice
Other Softwares: HFSS, FEKO, NEC, Matlab, Opnet, CCStudio,
IAR Systems, PSpice, LTSpice
Platforms: Redhat 4, Sun OS 10, Windows
Experience Hardware Engineer, Oracle Apr 2012 - Present
• Circuit Design and schematics design
• Timing analysis
• Power analysis
CAD Engineer, Sandisk Jan 2011 - Mar 2012
• Writing tcl scripts for Insight ERC plugins
• Writing tcl scripts for developing module files for Tool environment setup and
installation
• Writing perl scripts to enhance reports generated from flows
• Writing skill scripts for in house tool development
Intern, EDA Microprocessor Methodology Division, IBM Jun 2010 - Aug 2010
• Developed a tool to analyze RLM flow in ICs and perform back end checks
• Attended training sessions on Static Timing Analysis (using IBM Einstimer) and
Floorplanning (using IBM Chipbench)
Course Advanced VLSI Systems, Physical Design Automation of VLSI Systems, Advanced
Work Computer Architecture, Digital Systems Test, Digital Integrated Circuits, Wireless
Networks, EM Radiation and Antennas
Academic Dean’s scholarship for best academic performance 2006-07, 2007-08
Honors ECE Department, Vellore Institute of Technology

2. Potential Filed patent on Zig-G (Wireless ECG Technology) Mar 2009
Patent
Publications [1] V. Mukala, V. Lakafosis, A. Traille, and M. M. Tentzeris ”A Novel Zigbee- based
Low- cost, Low- Power Wireless EKG system”, Proc. of IEEE IMS 2010, Anaheim,
US, May 2010
[2] M. Taneja,V. Mukala, and S. Muthukumar ”Low Power 4 Bit Ripple Carry Adder
using the GDI Technique”, Proc. of 2008 IASTED Conference on Circuits and systems,
Hawaii, US, Aug 2008
Projects • Automation of Analysis and report generations from IC design flows (includes
Synthesis, Placement, Routing, Back End Checks)
Supervised by: Niranjan Vaish, R&D Manager, IBM Summer 2010
• Computer Architecture: Tomasulos Algorithm and branch predictors
Supervised by: Dr. Schimmel, ECE Department, Georgia Tech Spring 2010
• ATPG: Test Generation, Fault Detection, verification of a given digital circuit
Supervised by: Dr. A. Chatterjee, ECE Department, Georgia Tech Fall 2009
• VLSI Memory System and Arithmetic Unit: Design of SRAM and peripherals
Supervised by: Dr. Saibal M., ECE Department, Georgia Tech Fall 2009
• Designing 32-bit Arithmetic Logic Unit
Supervised by: Dr. Paul Hasler, ECE Department, Georgia Tech Fall 2009
Activities Graduate Representative,
ICGT, Georgia Tech Jan2010 - Aug 2010
References http://users.ece.gatech.edu/~vmukala3/references.pdf