Diese Präsentation wurde erfolgreich gemeldet.
Die SlideShare-Präsentation wird heruntergeladen. ×

Architectures for mobile computing dec12

Weitere Verwandte Inhalte

Ähnliche Bücher

Kostenlos mit einer 30-tägigen Testversion von Scribd

Alle anzeigen

Ähnliche Hörbücher

Kostenlos mit einer 30-tägigen Testversion von Scribd

Alle anzeigen

Architectures for mobile computing dec12

  1. 1. Dr. Rajveer S Shekhawat GM, New Products Development, Secure Meters Ltd
  2. 2. Performance and Power Challenges to mobile computing HD Video playback Steaming audio & video 3D Gaming 3D interfaces Web browsing Multiple application Location-based services (maps and satellite images) So single processors are being replaced by multicore processors to meet the above requirements.04/07/15 CMCTAR2012 2
  3. 3. Predictions 04/07/15 CMCTAR2012 3
  4. 4. 04/07/15 CMCTAR2012 4
  5. 5. Major Mobile Devices using MCPs Smart phones PDAs Tablets Laptops Game Stations Vehicle navigation systems 04/07/15 CMCTAR2012 5
  6. 6. Performance Challenges Multi core architectures with high integration of peripherals are needed to deliver ever increasing performance. The likely peripherals are: Graphics/image/video Voice/speech Intelligent keys/trackballs 3D motion GPS Communication (Bluetooth, WiFi, IR, GSM/UMTS) 04/07/15 CMCTAR2012 6
  7. 7. Challenge areas Hardware Architecture Computation Speed Power Complexity Graphics speech Software System programming Application programming User interface 04/07/15 CMCTAR2012 7
  8. 8. Cost Optimization 04/07/15 CMCTAR2012 8
  9. 9. Power Optimization 04/07/15 CMCTAR2012 9
  10. 10. 04/07/15 CMCTAR2012 10
  11. 11. 04/07/15 CMCTAR2012 11
  12. 12. 04/07/15 CMCTAR2012 12
  13. 13. 04/07/15 CMCTAR2012 13
  14. 14. 04/07/15 CMCTAR2012 14
  15. 15. 04/07/15 CMCTAR2012 15
  16. 16. 04/07/15 CMCTAR2012 16
  17. 17. Parallel Programming Multi-core architectures can help in reducing power consumption of single CPU to increase computational power. However to best make use of them, we need to write efficient parallel programs for both systems and application programming. This area is still evolving and needs better programming tools to support faster, accurate and efficient programs. Multi-core processors can have two configurations:  Symmetric multiprocessing (SMP)  Assymetric multiprocessing (ASMP) 04/07/15 CMCTAR2012 17
  18. 18. Symmetri Multi Processing SMP architecture consists of two or more identical CPU cores. All cores share a common system memory and are controlled by a single Operating system. Each CPU is capable of operating independently on different workloads and whenever possible, is also capable of sharing workloads with the other CPU. 04/07/15 CMCTAR2012 18
  19. 19. Example NVIDIA Tegra 2 and Tegra 3 04/07/15 CMCTAR2012 19
  20. 20. 04/07/15 CMCTAR2012 20
  21. 21. 04/07/15 CMCTAR2012 21
  22. 22. Architectural Features of Tegra 2 04/07/15 CMCTAR2012 22  Dynamic length 8-stage pipeline supporting speculative out-of-order execution. This allows the processor to dynamically reorder instructions to improve performance by avoiding stalls due to instruction latencies and resource conflicts. Older generation Cortex-A8 processors use an in-order pipeline and are unable to avoid the penalties that arise from branching and cache misses support for speculative branch predictions to avoid branching penalties.  A Dual-core Symmetrical Multiprocessing (SMP) configuration operating either independently, or in lockstep to deliver peak performance when needed, and consuming almost zero power when idle.  32KB Instruction cache and 32KB Data cache per core with both cores sharing a common 1MB L2 Cache. The 1MB L2 cache is large enough to load an entire browser memory footprint into cache to provide a faster Web browsing experience.  CPU cores that are optimized to operate at a frequency of one Gigahertz with the ability to scale up to even higher frequencies. The two cores are assisted by a common snoop control unit that enforces coherency between the cores and manages the common 1MB L2 cache shared by the two cores.
  23. 23. 04/07/15 CMCTAR2012 23
  24. 24. Intelligent Power Management Long battery life along with high computing power is only feasible if we can use multi-core architectures with low power consumption. A popular technique is Dynamic Voltage and Frequency Scaling (DVFS). Here the voltages (both supply and threshold) can be reduced to for lower power operation. Further frequency of operation can also be scaled down. However, to keep the execution timing of tasks intact, multitasking/mutit-threading can be used. There appropriate scheduling algo’s for multi-cores. 04/07/15 CMCTAR2012 24
  25. 25. 04/07/15 CMCTAR2012 25
  26. 26. Tegra 3 from Nvidia (vSMP) 04/07/15 CMCTAR2012 26
  27. 27. Renesas Dual Core (EMMA) 04/07/15 CMCTAR2012 27
  28. 28. EMMA Features It is an application processor for smart mobiles. It has two ARM Cortex-9 cores with two Neon extensions It has an integrated audio/video engine, A 3D graphics block A number of communication interfaces It uses hardware accelerator for HD quality decoding It consumes minimal power 04/07/15 CMCTAR2012 28
  29. 29. 04/07/15 CMCTAR2012 29
  30. 30. 04/07/15 CMCTAR2012 30
  31. 31. 04/07/15 CMCTAR2012 31
  32. 32. Expectations (PwC report) 04/07/15 CMCTAR2012 32
  33. 33. Parallel Programming 04/07/15 CMCTAR2012 33
  34. 34. 04/07/15 CMCTAR2012 34
  35. 35. Common Prog Environs 04/07/15 CMCTAR2012 35
  36. 36. Thanks 04/07/15 CMCTAR2012 36

×