Event manager F28x

Chapter 5 : Event Manager
C28x

Digital Signal Controller
TMS320F2812

Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt

Event Manager Block Diagram (EVA)
Reset PIE
2
/ TCLKINA / TDIRA
EV Control Registers / Logic ADC Start

GP Timer 1 Compare Output Logic T1PWM_T1CMP
GP Timer 1
•

Compare Unit 1 PWM1
PWM Circuits Output Logic
Data Bus

PWM2
Compare Unit 2 PWM Circuits Output Logic PWM3
PWM4
PWM6

GP Timer 2
CLK QEP
MUX DIR Circuit

• CAP1/QEP1
Capture Units • CAP2/QEP2
• CAP3/QEPI1


General-Purpose Timers (EVA)
Reset PIE
2
/ TCLKINA / TDIRA

GP Timer 1
•

Compare Unit 1 PWM1
Data Bus

PWM2
PWM4
PWM6

GP Timer 2
CLK QEP
MUX DIR Circuit

• CAP1/QEP1
• CAP3/QEPI1


General-Purpose Timer Block Diagram
(EVA)
Internal
TxCMPR . 15 - 0
(HSPCLK)
TPS 2-0 Shadowed
Clock TxCON . 10 - 8 Compare
Prescaler Register
TxCNT . 15 - 0 GPTCONA
M
U 16 - Bit Timer Compare Output TxPWM_
External
X Counter Logic Logic TxCMP
QEP

TCLKS 1-0
TxCON . 5 - 4 Period
Register
Shadowed

Note: x = 1 or 2 TxPR . 15 - 0


Continuous-Up Counting Mode
(Used for Asymmetric PWM Waveforms)
This example:
TxCON.3-2 = 00 (reload TxCMPR on underflow)
TxPR = 3 ♦ Seamless counting continues
TxCMPR = 1 (initially)
♦ Up count period is TxPR+1
Prescale = 1
CPU writes a 2 to
compare reg. buffer
anytime here TxCMPR=2 is loaded here
3 3 3
2 2 2
1 1 1
TxCNT Reg. 0 0 0 0

TxPWM/TxCMP
(active high)
CPUCLK

Continuous-Up/Down Counting Mode
(Used for Symmetric PWM Waveforms)
This example:
TxCON.3-2 = 01 (reload TxCMPR on underflow or period match)
TxPR = 3 ♦ Seamless up/down repetition
TxCMPR = 1 (initially)
♦ Up/down count period is 2*TxPR
Prescale = 1

TxCMPR loads TxCMPR loads TxCMPR loads
with a 1 with a 2 with a 1
3 3
2 2 2 2
1 1 1 1
TxCNT Reg. 0 0 0

TxPWM/TxCMP
(active high)
CPUCLK

Generated Outputs and Interrupts PWM period #2
New Period is
CPU Changes
Auto-loaded on
Period Reg. Buffer
Underflow here
anytime here

PWM period #1

Comp2
eu a V

Comp1
l
ret nuo Cre m T
i

TxCMP/TxPWM
(active high)

TxCMP/TxPWM
(active low)

Compare Ints

Period Ints

Underflow Ints


GP Address Registers
Register
Timer Description
GPTCONA 0x007400 General Purpose Timer Control Register A
T1CNT 0x007401 Timer 1 Counter Register
T1CMPR 0x007402 Timer 1 Compare Register Buffer
T1PR 0x007403 Timer 1 Period Register Buffer
EVA T1CON 0x007404 Timer 1 Control Register
T2CON 0x007408 Timer 2 Control Register
GPTCONB 0x007500 General Purpose Timer Control Register B
EVB T3CON 0x007504 Timer 3 Control Register
T4CON 0x007508 Timer 4 Control Register
EXTCONA 0x007409 / EXTCONB 0x007509 ;Extension © 2006 Pantech Solutions Pvt
Control Register
Technology beyond the Dreams™ Copyright

GP Timer Control Register A
Upper Byte: (EVA)
GPTCONA @ 0x007400
Timer 2 Compare Trip Enable Timer 1 Compare Trip Enable
T2CTRIPE (if EXTCONA[0]=1) T1CTRIPE (if EXTCONA[0]=1)
0 = disable 0 = disable
1 = enable 1 = enable

15 14 13 12 11 10-9 8-7
reserved T2STAT T1STAT RESERVED RESERVED T2TOADC T1TOADC

GP Timer Status (read-only) ADC start by event of GP Timer x
0 = counting down 00: no event starts ADC
1 = counting up 01: setting of underflow interrupt flag
10: setting of period interrupt flag
11: setting of compare interrupt


GP Timer Control Register A
Lower Byte: (EVA)
GPTCONA @ 0x007400
Timer 2 Compare Output Enable Timer 1 Compare Output Enable
T2CMPOE (if EXTCONA[0]=1) T1CMPOE (if EXTCONA[0]=1)
0 = disable (hi-Z) 0 = disable (hi-Z)

6 5 4 3-2 1-0
TCOMPOE RESERVED RESERVED T2PIN T1PIN

TxPWM/TxCMP Output Pin Conditioning
Compare Output Enable 00: forced low
(reserved when EXTCONA[0]=1) 01: active low
10: active high
0 = all disable (hi-impedance) 11: forced high
1 = all enable


Timer Control Register
Upper Byte: (EVA)
T1CON @ 0x007404 / T2CON @ 0x007408
15 14 13 12 11 10 9 8
FREE SOFT reserved TMODE1 TMODE0 TPS2 TPS1 TPS0

Timer Clock Prescale
Emulation Halt Behavior
00 = stop immediately 000: ÷ 1 100: ÷ 16
01 = stop at end of period 001: ÷ 2 101: ÷ 32
1x = free run (do not stop) 010: ÷ 4 110: ÷ 64
011: ÷ 8 111: ÷ 128

Count Mode Select
00 = stop/hold
01 = continuous-up/down
10 = continuous-up
11 = directional-up/down

Timer Control Register (EVA)
T1CON @ 0x007404 / T2CON @ 0x007408
Timer Compare Operation Enable
Lower Byte:
0 = disable
1 = enable
Timer Clock Source Period Register Select
Timer Enable
00 = internal (HSPCLK) 0 = use own per. reg.
0 = timer disable 01 = external TCLKIN pin 1 = use Timer 1 per. reg
1 = timer enable 10 = reserved (bit reserved in T1CON)
11 = QEP

7 6 5 4 3 2 1 0
T2SWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR

Start with Timer 1 Compare Register Reload Condition
0 = use own TENABLE 00 = when counter equals zero (underflow)
1 = use Timer 1 TENABLE 01 = when counter equals zero or period reg
(bit reserved in T1CON) 10 = immediately
11 = reserved

Extension Control Register A (EVA)
EXTCONA @ 0x007409

Independent Compare
QEP Index Enable Output Enable Mode

15-4 3 2 1 0

reserved EVSOCE QEPIE QEPIQUAL INDCOE

EV Start-of-Conversion CAP3/QEPI Index
Output Enable Qualification Mode
0 = disable 0 = off
1 = enable 1 = on


GP Timer Compare PWM Exercise
Symmetric PWM is to be generated as follows:
• 50 kHz carrier frequency
• Timer counter clocked by 30 MHz external clock
• PLL multiply by 10/2
• HSPCLK : divide by 2
• Use the 1 prescale option
• 25% duty cycle initially
• Use GP Timer Compare 1 with PWM output active high
• T2PWM/T2CMP pins forced low

Determine the initialization values needed in the GPTCONA,
T1CON, T1PR, and T1CMPR registers


GP Timer Compare PWM Exercise Solution

GPTCONA = (xxx0000001000010)b = 0x0042 all x’s assigned
T1CON = (xx00100001000010)b = 0x0842 a value of 0

1 . carrier period 1 . 20 µ s
T1PR = = = 750
2 timer period 2 13.34 ns

T1CMPR = (100% - duty cycle)*T1PR = 0.75*750 = 563

PLLCR = 0x0A

HISPCP = 1


EVAIMRA Register
@ 0x742C
15 14 13 12 11 10 9 8
- - - - - T1OFINT T1UFINT T1CINT

7 6 5 4 3 2 1 0
T1PINT - - - CMP3INT CMP2INT CMP1INT PDPINT

Interrupt Mask Bits Bit Event
0 = disable interrupt 10: Timer 1 Overflow
9: Timer 1 Underflow
1 = enable interrupt
8: Timer 1 Compare match
7: Timer 1 Period match
3: Compare Unit 3, Compare match
0: Power Drive Protect input, EVA


EVAIMRB Register
@ 0x742D

15 14 13 12 11 10 9 8
- - - - - - - -

7 6 5 4 3 2 1 0
- - - - T2OFINT T2UFINT T2CINT T2PINT

0 = disable interrupt 3: Timer 2 Overflow
2: Timer 2 Underflow
1 = enable interrupt
1: Timer 2 Compare match
0: Timer 2 Period match


EVAIMRC Register
@ 0x742E

15 14 13 12 11 10 9 8
- - - - - - - -

7 6 5 4 3 2 1 0
- - - - - CAP3INT CAP2INT CAP1INT

2: Capture Unit 3 input
0 = disable interrupt
1: Capture Unit 2 input
1 = enable interrupt 0: Capture Unit 1 input


15
EVAIFRx Register
14 13 12 11 10 9 8
EVAIFRA - - - - - T1OFINT T1UFINT T1CINT
@ 0x742F
7 6 5 4 3 2 1 0
Read:
T1PINT - - - CMP3INT CMP2INT CMP1INT PDPINT
0 = no event
1 = flag set
15 14 13 12 11 10 9 8
EVAIFRB - - - - - - - -
@ 0x7430
7 6 5 4 3 2 1 0
Write: - - - - T2OFINT T2UFINT T2CINT T2PINT
0 = no effect
1 = reset flag
15 14 13 12 11 10 9 8
EVAIFRA - - - - - - - -
@ 0x7431
7 6 5 4 3 2 1 0
- - - - - CAP3INT CAP2INT CAP1INT


Lab 5: Let’s play a tune !
Aim: with Event Manager A General Purpose Timer 1
• Exercise
• Use Lab 4 as a starting point. In Lab 4 we initialised Core Timer 0 to
request an interrupt every 50 ms. We can use this ISR to load the next
note to T1PWM.
• Timer1 output ‘T1PWM’ is connected to a loudspeaker

Basic Tune Frequencies:
c1 : 264 Hz
d : 297 Hz
e : 330 Hz
f : 352 Hz
g : 396 Hz
a : 440 Hz
h : 495 Hz
c2 : 528 Hz

New Registers involved in Lab 5:

• General Purpose Timer Control A : GPTCONA
• Timer 1 Control Register : T1CON
• Timer 1 Period Register : T1PR
• Timer 1 Compare Register : T1CMPR
• Timer 1 Counter Register : T1CNT
• EV- Manager A Interrupt Flag A : EVAIFRA
• EV- Manager A Interrupt Flag B : EVAIFRB
• EV-Manager A Interrupt Flag C : EVAIFRC
• EV- Manager A Interrupt Mask A : EVAIMRA
• EV- Manager A Interrupt Mask B : EVAIMRB
• EV- Manager A Interrupt Mask C : EVAIMRC
• Interrupt Flag Register : IFR
• Interrupt Enable Register : IER


Compare Units (EVA)
Reset PIE
2
EV Control Registers / Logic / TCLKINA / TDIRA
ADC Start

GP Timer 1
•
Compare Unit 1 Output Logic
PWM Circuits PWM1
Data Bus

PWM2
PWM Circuits PWM3
PWM4
PWM Circuits PWM5
PWM6
GP Timer 2
CLK QEP
MUX DIR Circuit
• CAP1/QEP1
• CAP3/QEPI1

What is Pulse Width Modulation?
• PWM is a scheme to represent a signal as a sequence of pulses
– fixed carrier frequency
– fixed pulse amplitude
– pulse width proportional to instantaneous signal amplitude
– PWM energy  original signal energy

• Differs from PAM (Pulse Amplitude Modulation)
– fixed width, variable amplitude


PWM Signal Representation

t
Original Signal
same areas (energy)

t t
T T
PWM representation PAM representation


Why Use PWM in Digital Motor Control?
• Desired motor phase currents or voltages are known
• Power switching devices are transistors
– Difficult to control in proportional region
– Easy to control in saturated region
• PWM is a digital signal easy for DSP to output

DC Supply DC Supply

? Desired
PWM
PWM approx.
signal to of desired
motor phase signal
Unknown Gate Signal Gate Signal Known with PWM


Asymmetric PWM Waveform
TPWM

Period

Compare

Counter

Tpwm / Tcmp Pin
(active high) Caused by Period match
(toggle output in Asym mode only)
Caused by Compare match


Symmetric PWM Waveform
TPWM

Period

Compare

Counter

TPWM /TCMP Pin
(active high)

Interrupts

General Purpose Timer Full Compare Units
PWM1
Period Compare PWM2
Compare Compare PWM3
TPWM/TCMP Pin PWM4
Counter Compare PWM5
PWM6


Voltage source inverter components
Upper & lower
devices can not
be turned on
simultaneously
PWM signal is (dead band)
applied between
gate and source
+

DC bus
capacitor − Three phase
outputs which
go to the motor
terminals

Power
Switching
Devices


Compare Units Block Diagram (EVA)

ACTRA . 11 - 0

Shadowed
T1CNT . 15 - 0
Compare
GP Timer 1 Action Control
Counter Register
DBTCONA . 11 - 2

Compare Dead Band Output PWMy, y+1
Logic Units Logic
COMCONA . 9
FCOMPOE
Compare
Register
Shadowed
Note: x = 1, 2, 3; y = 1, 3, 5
CMPRx . 15 - 0


Compare Unit Registers
Register Address Description
COMCONA 0x007411 Compare Control Register A
ACTRA 0x007413 Compare Action Control Register A
DBTCONA 0x007415 Dead-Band Timer Control Register A
EVA
CMPR1 0x007417 Compare Register 1
COMCONB 0x007511 Compare Control Register B
ACTRB 0x007513 Compare Action Control Register B
DBTCONB 0x007515 Dead-Band Timer Control Register B
EVB
EXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control Register


Compare Control Register (EVA)
Upper Byte: COMCONA @ 0x007411
Compare Enable Space Vector PWM Full Compare Output Enable
0 = SV disable (reserved when EXTCONA[0]=1)
0 = disable
1 = enable 1 = SV enable 0 = all disable (hi-impedance)
1 = all enable

15 14 13 12 11 10 9 8
CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE PDPINTA

CMPRx reload condition ACTRA reload condition PDPINT Status
00 = when T1CNT = 0 00 = when T1CNT = 0 0 = low
01 = when T1CNT = 0 or T1PR 01 = when T1CNT = 0 or T1PR 1 = high
10 = immediately 10 = immediately
11 = reserved 11 = reserved


Compare Control Register (EVA)
Lower Byte: COMCONA @ 0x007411
Full Compare 2 Full Compare 2
Output Enable Trip Enable
FCMP2OE C2TRIPE
(if EXTCONA[0]=1) (if EXTCONA[0]=1)

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED reserved reserved RESERVED RESERVED RESERVED

Full Compare 3 Full Compare 1 Full Compare 3 Full Compare 1
Output Enable Output Enable Trip Enable Trip Enable
FCMP3OE FCMP1OE C3TRIPE C1TRIPE
(if EXTCONA[0]=1) (if EXTCONA[0]=1) (if EXTCONA[0]=1) (if EXTCONA[0]=1)
0 = disable 0 = disable 0 = disable 0 = disable
1 = enable 1 = enable 1 = enable 1 = enable


Compare Action Control Register (EVA)
ACTRA @ 0x007413
Basic Space Vector Bits
can write as 0 when SV not in use

15 14 13 12 11 10 9 8
SVRDIR D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0

7 6 5 4 3 2 1 0
CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0

Pin Action on Compare: CMPyACT1-0
00 force low
01 active low
SV Rotation Direction 10 active high
can write as 0 when SV not in use
11 forced high


Motivation for Dead-Band
supply rail

Gate Signals are
Complementary PWM to motor phase

♦ Transistor gates turn on faster than they shut off
♦ Short circuit if both gates are on at same time!


Dead-Band Functionality (EVA)
Clock Prescaler
HSPCLK
DBTCONA . 4 - 2

PHx
PHx edge
detect ENA
4-bit
DT Counter
reset

DTPHx
comparator
DT
DTPHx_
4-bit period
DBTCONA . 11 - 8
dead time
DTPHx
Asymmetric PWM Example
DTPHx_


Dead-Band Timer Control Register (EVA)
DBTCONA @ 0x007415
dead time = DB period * DB prescaler * CPUCLK period
DB Timer Period

15 14 13 12 11 10 9 8

reserved reserved reserved reserved DBT3 DBT2 DBT1 DBT0

7 6 5 4 3 2 1 0
EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 reserved reserved

DB Timer Enable DB Timer Prescaler
0 = disable 000 = 1 100 = 16
1 = enable 001 = 2 101 = 32
010 = 4 110 = 32
011 = 8 111 = 32


Reset
Capture Units (EVA)
PIE
2
/ TCLKINA / TDIRA

GP Timer 1
•

Compare Unit 1 PWM1
Data Bus

PWM2
PWM4
PWM6

GP Timer 2
CLK QEP
MUX DIR Circuit

• CAP1/QEP1
• CAP3/QEPI1


Capture Units

Timer
Trigger
.
Timestamp
Values

• Capture units timestamp transitions on capture input
pins
• Three capture units (per event manager) - each
associated with a capture input pin

Some Uses for the Capture Units
♦ Synchronized ADC start with capture event
♦ Measure the time width of a pulse
♦ Low speed velocity estimation from incr. encoder:
Problem: At low speeds, calculation of speed based
xk - xk-1
on a measured position change at fixed time vk ≈
intervals produces large estimate errors ∆t

Alternative: Estimate the speed using a measured time interval at fixed
position intervals
Signal from one
∆x
vk ≈ Quadrature
tk - tk-1 Encoder Channel
∆x


Capture Units Block Diagram (EVA)
T1CNT . 15 - 0 T2CNT . 15 - 0

GP Timer 1 GP Timer 2
Can latch on:
Counter Counter • rising edge
• falling edge
CAPCONA . 14 -12 • both
CAPCONA . 10 - 9 MUX CAP3TOADC
Enable
CAPCONA . 8

Edge
. ADC Start
(CAP 3)
Detect
3

TTL Signal
/ CAP1,2,3

2-Level Deep Edge Select
RS
CAPCONA . 7 - 2
FIFO
CAPxFIFO Status CAPRESET min. valid width:
CAPCONA . 15 2 CPUCLK lo
CAPFIFOA . 13 - 8
2 CPUCLK hi


Capture Units Registers
Register Address Description
CAPCONA 0x007420 Capture Control Register A
CAPFIFOA 0x007422 Capture FIFO Status Register A
CAP1FIFO 0x007423 Two-Level Deep FIFO 1 Stack
EVA CAP3FIFO 0x007425 Two-Level Deep FIFO 3 Stack
CAP1FBOT 0x007427 Bottom Register of FIFO 1
CAPCONB 0x007520 Capture Control Register B
CAPFIFOB 0x007522 Capture FIFO Status Register B
EVB CAP6FIFO 0x007525 Two-Level Deep FIFO 6 Stack
EXTCONA 0x007409 / EXTCONB 0x007509 ;Ext. Cntrl Reg.

Capture Control Register (EVA)
CAPCONA @ 0x007420
Unit 3 Control ADC Start
0 = disable 0 = no action
1 = enable 1 = CAP3INT flag

15 14-13 12 11 10 9 8
CAPRES CAPQEPN CAP3EN reserved CAP3TSEL CAP12TSEL CAP3TOADC

Unit 1 & 2 Control
00 = disable Timer Select
01 = enable for capture 0 = GP Timer 2
10 = reserved 1 = GP Timer 1
11 = enable for QEP
7-6 5-4 3-2 1-0

CAP1EDGE CAP2EDGE CAP3EDGE reserved

Edge Detection Control
00 = no detection 10 = falling edge
01 = rising edge 11 = both edges

Capture FIFO Status Register (EVA)
CAPFIFOA @ 0x007422

15-14 13-12 11-10 9-8 7-0
reserved CAP3FIFO CAP2FIFO CAP1FIFO reserved

FIFOx Status:
CAPxFIFO bits are
00 = empty
automatically adjusted on a
01 = one entry
capture or FIFO read
10 = two entries
11 = three entries attempted,
1st entry lost


What is an Incremental Quadrature
Encoder?
A digital (angular) position sensor

photo sensors spaced /4 deg. apart
slots spaced  deg. apart θ/4
light source (LED)
θ

Ch. A

Ch. B
shaft rotation

Incremental Optical Encoder Quadrature Output from Photo Sensors


Quadrature Encoder Pulse (EVA)
Reset PIE
2
/ TCLKINA / TDIRA

GP Timer 1
•

Compare Unit 1 PWM1
Data Bus

PWM2
PWM4
PWM6

GP Timer 2
CLK QEP
MUX DIR Circuit

• CAP1/QEP1
• CAP3/QEPI1


How is Position Determined from
Quadrature Signals?
Position resolution is θ/4 degrees.

(00) (11) increment decrement
(A,B) =
01
(10) (01) counter counter

11 Quadrature 00
Ch. A Decoder
State Machine
Ch. B
10


Incremental Encoder Connections
(EVA) Ch. A

QEP . CAP1/QEP1
Ch. B

decoder
logic . CAP2/QEP2
Index
CLK DIR

CAP3/QEPI
QEPIQUAL • GP Timer 2 selected as pulse
counter
• Timer Prescaler bypassed (i.e.
QEPIE Prescale always 1)
GP Timer 2


Event manager F28x

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