AVR Microcontroller

ELEKTOR live 2013 – AVR Microcontroller

AVR® Microcontroller
Andreas Riedenauer
Ineltek Mitte GmbH

http://www.atmel.com


Agenda
 Warum gerade die? Die AVR Familie kurz vorgestellt.
 Neue Bausteine. Neue Features.
 Die Spezialisten: AVRs mit Sonderausstattung.
 A-Note für A-Typen
 Randgebiete: Die Peripherie.
 42: die Antwort auf mehr als eine Frage. Hardware Design.
 13 Jahre FAE – und ein bisschen weiser. Tipps und Stolperfallen.

 Gut versteckt im Datenblatt.
 Rechenleistung statt elektrische Leistung.
 Doppelte Sicherheit – Security und Safety
 Touch me – kapazitiv.
 Werkzeugkasten: Was brauche ich für den Start?

 Was jetzt – Assembler oder C?
 Wir fangen an: ein erstes Projekt mit Studio6
 Wieso „Entwanzen“?
 Wie geht´s weiter?
 Quiz mit Preisverleihung
www.atmel.com

October 13


WARUM GERADE DIE?
DIE AVR FAMILIE KURZ VORGESTELLT.

www.atmel.com

October 13


AVR Flash Microcontrollers
32-bit AVR UC3
The highest performance AVR in the world

8/16-bit AVR XMEGA
Peripheral Performance

8-bit megaAVR
The world’s most successful MCU family

8-bit tinyAVR
Small packages, big performance



AVR CPU
 AVR CPU
 Harvard architecture

 True single cycle execution
 Up to 20 MIPS at 20 MHz
 32 General Purpose registers

 Xmega…
 Up to 32 MHz CPU / 128 (256) MHz T/C
 Adds DMA Controller
 Adds flexible Event System
 Adds Programmable Multi level Interrupt Controller



Atmel 10/16/2013


Leading 8-bit Architecture
 RISC architecture with CISC instruction set
 Single cycle execution
 Harvard Architecture
 Simultaneous, fast access to registers
 Separate memories and buses for program and data

 32 Working Registers (8 bit GPR)
 16-bit Stack Pointer
 22-bit Program Counter
 Up to 20MHz System clock (Xmega: 32 MHz)

8


32x8-bit General Purpose Registers
 32 Accumulator Registers with 8 bit
 3 register pairs for16-bit data pointers
 Instructions with auto increment, decrement and displacement of pointers
 Z Pointer suited for look up tables and indirect jump (Flash)
 Direct address of up to 64K
R0
R1
R2

X Pointer
Y Pointer
Z Pointer

R26
R27
R28
R29
R30
R31

XL
XH
YL
YH
ZL
ZH
9


General Purpose IO Registers - GPIOR
 IO mapped variable registers
 Bit variables

 General variables
 Status Flags
 ...

 Up to three registers per device
 Fast access through SBI, CBI, SBIS, and SBIC instructions
 GPIOR within the address range 0x00 - 0x1F only

10


Single Cycle Instruction Execution

Register File

Register operations
take ONE clock pulse
on the EXTERNAL clock
input

ALU

11


Common for all standard AVRs
 Self-programming FLASH program memory
 In-System Programming within the whole voltage range

 Internal calibrated RC Oscillator
 Internal SRAM and EEPROM
 debugWIRE or JTAG OCD support

12


AVR - Designed for C Programming
 Architecture and instruction set co-designed with C-Compiler vendor
 Compiler development project initiated before architecture and instruction set
frozen
 Compiler experts’ advice implemented in hardware
 Potential HLL bottlenecks identified and removed

 The design process resulted in
 Instruction set support for 16-bit arithmetic operations
 32 working registers which eliminate move to and from SRAM
 Single Cycle execution

13


Program Memory and Data Pointers
 Stack Pointer + Three Data pointers
 One or two pointers + SP is common for 8-bit

 Code efficient memory to memory copy

 Pointer handling similar to C- language
 Auto Increment/Decrement
 Indirect with Displacement
- Efficient for accessing arrays and structs
- Efficient when placing local variables on Software Stack

C Source code

unsigned char *var1, *var2;
*var1++ = *--var2;

Assembly code

LD
ST

R16,-X
Z+,R16

14


Interrupt System Features
 All AVR peripherals are handled through IO registers (SFR)
 Automatic interrupt flag clearing

 Automatic disable of other interrupts inside the interrupt routine
 Each interrupt has its own vector and interrupt handler
 Short response time
 4 Clock Cycles + RJMP to interrupt handler
Interrupt Routine 2
Interrupt Routine 1
Normal Mode
INT2 flag
INT1 flag
I flag
15
TIME


NEUE BAUSTEINE.
NEUE FEATURES.

www.atmel.com

October 13


www.atmel.com

October 13


Some New Features
 Modern Attiny Controllers with Features like
 Pico Power Technology
 Hardware USART
 Self Programming
 Precisio n RC Oscillator

 HW Support für Cap. Touch / Proximity Detection

 32 Pin ATxmega E5 Series (see also Xmega chapter)
 ADC with up to16 Bit Oversampling Hardware Support
 Asynchoronous Event System
 Glue Logic

18


DIE SPEZIALISTEN:
AVRS MIT SONDERAUSSTATTUNG.

www.atmel.com

October 13


Application Specific Processors (ASSPs)
 USB
 CAN
 PWM
 Battery Management
 MCU Wireless

20


CAN Introduction
 ISO standard (ISO 11898) for serial communication
 developed 1980 by BOSCH for automotive applications

 Asynchronous Serial Bus
 Absence of node addressing






Message identifier specifies contents and priority
Lowest message identifier has highest priority
Non-destructive arbitration system by CSMA with collision detection
Multi-master / Broadcasting concept
Sophisticated error detection & handling system
*

 CAN has gained widespread use
 Industrial Automation
 Automotive, …etc.

22


Why CAN?
 Mature Standard
 Hardware implementation of the protocol
 Simple Transmission Medium
 Excellent Error Handling (CRC)

 Fault Confinement
 Most used protocol in industrial and automotive world
 Best Performance / Price ratio

23


Motor Control: PWM3 Focus
 3 Phase Brushless DC Motor


HVAC (Heating, Ventilating, Air
Conditioning)



Refrigerators



Fans



Pumps



High tech Industrial, constant speed
applications



Traction elevator



Medical equipment



Hard disk, CD drives



 3 Phase Induction AC Motor

Automotive



HVAC



Washing machine



Blowers



Fans



Pumps



Industrial control

27


AT90PWMx Family
 ATmega AVR with enhanced features for light ballast and motor control
 Power Stage Controller (PSC)
 synchronized PWM channels for 3 phase motors
 Fast emergency shut down of PWM outputs (only few 10 ns)
 Adjustable dead-band control

 Over current protection

 64 MHz PLL, providing 12-bit PWM accuracy up to 16 KHz
 Analog synchronized with PSC

 DALI - Digital Addressable Lighting Interface
 Integrated Power Factor Correction (PFC)
 10 Bit D/A with output driver (impedance < 1KOhm)

 3 comparators for Back EMF for Sensorless motors

28


From PWM Channels

BLDC Motor Application
Hall sensors to INT (sensor)
Back EMF to ADC (sensor-less)

0
1
2
3
4
5

D
R
I
V
E
R
S

0

2

4

C

U

+

C

V

1

3

N S

5

C

W

To amplifier and ADC for regulation
To comparator for emergency stop

29


3 Phases Induction AC Motor Application
Hall sensors to INT

From PWM Channels

Tachometer to ADC

0
1
2
3
4
5

D
R
I
V
E
R
S

0

2

4

C

U

+

C

V

1

3

5

C

W

To amplifier and ADC for regulation
To comparator for emergency stop

30


Requirements for a 3-phase AC Motor Control MCU
PWM cycle
PWM cycle

0

2

4

U

0

+

U
V
W

-

1

V

2

3

1

3

5

W

4

5

Mandatory min. Dead Time

 Up to 6 Synchronous PWM channels (12 bit precision or more)

 PWM Timer Min clock frequency = 64MHz for 12 bit precision, 12KHz
 Minimum dead time controlled by hardware for all 6 channels
 All PWM must be disabled by hardware (Input) when overcurrent
 Capability to support Scalar Algorithm and Space Vector Algorithm
 10 to 16 MIPS for 3 phase AC induction with Space Vector Algorithm

31


Sensorless control of two-phase fan
 AVR440 - sensorless control of two-phase BLDC fan
 Patent filed – method can only be used with AVR microcontrollers

 B-EMF voltage over passive winding used to time commutation.

 Advantage
 Hall-sensor can be eliminated to reduce fan cost

 Disadvantage
 Difficult to run the fan a very low speed

 Requirements
 Up-down PWM counter
 PWM triggered ADC

33


Sensor based control of two-phase fan
 AVR441 - two-phase BLDC fan with two speed references
 E.g. Host and temperature sensor
 Autonomous fan speed
 Temperature sensor in

 AVR442 - two-phase BLDC fan with TWI





Also uses integrated temp sensor
Autonomous fan speed
TWI/SMBus control multiple fans
Advanced fan feedback

34


Sensor based control of 3-phase BLDC motor
 AVR443, AVR448 – Three-phase BLDC motor
 GPIO/PWM controls high side driver
 PWM controls low side driver
 Current sensing

 Requirements
 3/6 PWM channels and PWM triggered ADC

35


Sensor based control of 3-phase BLDC motor
 AVR492 – sensor based control of three-phase BLDC motor





PWM on both high and low side driver
Current control: ADC
Overcurrent detection via on-chip comparator
Adaptive fault detection using DAC possible

 Performance
 CPU: 18% @ 8 MHz, 14K RPM
 Code: 3175 bytes (38%)
 RAM: 285 bytes (55%)

36


Sensorless control of 3-phase BLDC motor
 AVR444 – sensorless control of three-phase BLDC motor



Current control

 Advantage




Low cost microcontroller
Low cost motor without sensors
Automotive qualified (ATmega48 fam)

 Disadvantage



Very low speed not possible
Startup routine requires
known load

 Requirements



6 PWM channels
PWM triggered ADC

37


Sensorless control of 3-phase BLDC motor
 AVR493 – sensorless control of three-phase BLDC motor





Current control using ADC



Zero Crossing Back-EMF using three on-chip comparators

 Advantage


No ADC polling gives faster zero
cross detection for Back-EMF



Hardware emergency shutdown



Communication: UART/SPI/LIN

 Target devices


AT90PWM3

38


Sine wave driving of permanent magnet motor
 AVR447 – Sine wave driving of permanent magnet motor
 Uses three hall sensors for sine wave synchronization / speed control
 No encoder / tacho needed
 Advantages
 Low torque ripple
 Low cost microcontroller
 Speed control
 Full featured solution
- Safe startup w/synchronisation
- Turning
- Reverse rotation detection

 Disadvantages
 More CPU intensive than block
commutation

39


Control of 3-phase AC Induction Motor
 AVR494 / AVR495 – control of three-phase ACIM
 V/f control

 Space vector modulation
 Complex algorithms
 Speed PID control

 Advantage
 Hardware shutdown
 Hardware deadband
 Comm.: UART/SPI/LIN

 Target devices
 AT90PWM3

40


AUTOMOTIVE AVR

www.atmel.com

October 13


AVR für Automotive
CMOS Process for Automotive µC
 35K5 (AVR8)
 0.35µm NVM CMOS
 1.8V to 5V
 Qualified up to 85°C, 105°C, 125°C and now 150°C

 35K7 (AVR8)
 0.35µm NVM CMOS
 40V Breakdown voltage
 18V operation

 58K8/58K85 (ARM & AVR32)





0.18µm NVM CMOS
Core at 1.8V - I/O at 3V – I/O 5V tolerant
Qualification in progress up to 105°C
58K as ROM version
42


Automotive versus Industrial
 Main difference between Automotive parts and Industrial parts is the Quality
Level (EFR in PPM and LFR in FIT) and traceability
 Parts have to be designed for automotive
 Specific libraries
 Specific analog IPs
 Specific NV Memories
 Simulated on the full temperature range
 Guaranteed margin by process corner simulation
 Parts have to be characterized for automotive
 To know the robustness of the design versus process variation
 Parts have to be screened during manufacturing
 To remove any outliers
 To bring PPM level from 100 to Sub-1

 PPAPs on request (Production Part Approval Process)
43


Industrial versus Automotive Screening

 Qualification

Industrial

Automotive

Reference to Standard

ATMEL CPQ-2001

AEC*-Q100 Grade 2

Electrical Distribution

1 Wafer Lot

3 Wafer Lots with
Corner Lots

3 lots of 300 pieces

3 lots of 800 pieces

1 lot of 77 pieces

3 lots of 77 pieces at 3
Temperatures

Wafer Level Data Retention

No

168h at 250oC long
term aging

Post Thermal Cycle Wire Pull

No

Cpk** > 1.33

Industrial

Automotive

> 20PPM

1PPM

85PPM

1PPM

8 FIT

1 FIT***

ELFR: Early Life Failure Rate
NVM Program/Erase Endurance test

 Quality Targets
AOQ: Average Outgoing Quality
ELFR
LFR: Latent Failure Rate (Long Term)
*AEC = Automotive Electronics Council

** Cpk = Critical Parameter Index

*** FIT = Failure In Time (10 -9/Oper. Hours)
44


Automotive Quality Requirement
 AEC-Q100




STRESS TEST QUALIFICATION FOR INTEGRATED CIRCUITS
Defined by the Automotive Electronics Council
5 grades

-

Grade 0: -40°C to +150°C
Grade 1: -40°C to +125°C
Grade 2: -40°C to +105°C
Grade 3: -40°C to +85°C
Grade 4: 0°C to +70°C

ambient operating temperature range

 0 PPM – Zero Defect
 ISO TS16949 certification
 FMEA (Failure Mechanism and Effect Analysis)
 APQP (Advanced Product Quality Planning)

 PPAP/PSW (Production Part Approval Process / Part Submission Warrant )
Specific Methodology, Specific Products, Specific Production Flow (Screening), Specific Qualified plants
and subcontractors

45


Microcontroller - Overview
 AVR-8
 Subset of products qualified according to
- AECQ100-Grade1 from –40°C up to 125°C
- AECQ100-Grade0 from –40°C up to 150°C

 AVR-32
 Preliminary targets
- Vision/Image processing for Safety Application
- Flexray application (Backbone and XbyWire)

 Secondary target: Multimedia & Infotainment

46


High Temperature operating AVRs
 Up to 150°C ambient temperature
 Unique on the Market
 Thanks to very stable Non Volatile Memory cell (E2Prom)
 Qualification according to AEC-Q100 Grade 0
 Many applications in engine management and gear box
 Interface to Sensors or Actuators
 Throttle/Valve management, Torque sensor, Turbo Charger, Injectors, Fan
control

47


A-NOTE FÜR A-TYPEN

www.atmel.com

October 13


Why process migration?
 Atmel used proprietary 35k5 process
 New 35k4 process compatible to manufacturing at foundry
 Improve manufacturing and product sourcing flexibility
 Yield optimization and parameter tuning
 Reduced Active and Idle mode current by optimized routing

October 13

4


Technology of the New Process
 Metal shrink
 Transistors identical to existing process
 Standard cell library redesigned

 Transistors placed closer in new process

 Signal lines takes less space

October 13

5


Part name and ordering codes
 Devices in new process has Suffix ”A” (if old process device in 35k5)
 Migration Notes available

 One speed and voltage range on A-devices
Old:


ATmega128-16xU = 4.5 - 5.5V 0 - 16MHz



ATmega128L-8xU = 2.7 - 5.5V 0 - 8MHz

New:


ATmega128A-xU= 2.7 - 5.5V 0 - 16MHz

 Functionally compatible products has only one new device
Old:


ATmega48-20xU = 4.5 – 5.5V, 0 – 20 MHz



ATmega48P-20xU = 4.5 – 5.5V, 0 – 20 MHz



ATmega48V-10xU = 1.8 – 5.5V, 0 – 10 MHz



ATmega48PV-10xU = 1.8 – 5.5V, 0 – 10 MHz

New:


ATmega48PA-xU = 1.8 – 5.5V, 0 – 20 MHz



ATmega48 A-xU = 1.8 – 5.5V, 0 – 20 MHz
October 13

5


RANDGEBIETE: DIE PERIPHERIE.

www.atmel.com

October 13


AVR –Single Chip Solution
TWI

Temperature
Sensor

USART

SPI

Flash

EEPROM

CPU CORE

SRAM

A/D Converter Register File

I/O pins

Hardware
Multiplier
Analog
Comparator

Brown Out
Detector
Reset
Circuitry
Programmable
Watchdog
On-Chip
Debug

Analog
Reference

JTAG

Boundary
Scan

AVR Integrates Much More!

Pull-Ups
On Demand
High Current
Outputs
Calibrated
Oscillator
In System
Programming
LCD
Interface

Output
Driver

LCD driver

53


I/O Ports
 Push-Pull Drivers with High Current Drive


Sinks/Sources up to 20 mA (40mA)

 Pin-wise Controlled Data Direction and Pull-Up Resistors
 Fully Synchronized Inputs
 Three Control/Status Bits per Bit/Pin
 Real Read-Modify-Write
DDRx
0

Pull-Up

PORTx
0
PINx
?

Physical Pin
?

54


Faster IO PORT toggling
 PINx Register toggles PORTx Register
 Writing a ”1” to bit in PINx Register will toggle that bit in the PORTx Register

 Faster IO toggle access
 Dual cycle toggling
 Toggle multiple pins in one operation

55


Timer/Counter
 Wide range of 8- and 16-bit Timer/Counters
 The AVR Timer/Counters can use various clock sources
 Main CPU clock
 Internal High speed PLL
- High speed, 64MHz

 By external clock source

Relevant Application Notes
AVR130 AVR133

- Max speed XTAL/2

 External 32kHz asynchronous crystal
 All clock sources can be pre-scaled before being fed to the Timer/Counters

 AVR’s Timer/Counters are
interrupt driven and controlled
through the AVR IO registers
 Special T/C versions on PLL/PWM AVR and Xmega
 E.g. dead time generation
56


Analog Comparator
 Compares the input values on pins AIN0 and AIN1
 Dedicated Analog Comparator interrupt
 Selectable trigger on Rise, Fall or Toggle

 Output connectable to Input Capture of Timer/Counter1
 Pulse-width measurement of analog signals
 Easy Implementation of dual slope ADC

 Bandgap reference available
 ADC inputs can be used as AIN1

57


ADC Features
 Almost all AVRs have ADC
 Accuracy:
 10bits ±0.5LSB  65 us conversion time*.
 8bits ± 0.5LSB down to 12 us conversion time.

 Up to 11 single ended channels and up to 7 differential channels
 Programmable Gain Stage (1x, 10x, 100x, 200x)
 Free-run, single conversion and timed modes
 Interrupt on conversion complete
 Internal Voltage reference

*conversion

AVR120 AVR400

time is 6.5µs on AT90PWM Family

58


SPI - Serial Peripheral Interface
 3 pin serial communication interface
 Shift register type serial communication

 Full duplex interface
 AVR enables interrupt driven SPI communication
 Master and Slave mode
 Transmit at bit rates up to XTAL/2
 Receive at bit rates up to XTAL/4

 AVR supports industrial standard SPI interfaces
 Memories
 IO expanders
 Other CPUs in system

 SPI used for In System Programming (ISP)
59


TWI – Two Wire Interface
 2 pin serial communicantion interface
 Master and slave
 Fully interrupt driven
 Fast Mode support

 Wake-up from power down mode on address recognition
 Slave Address
 General Call

 Peripheral device interface
 Philips I2C compatible

60


USI – Universal Serial Interface
 Hardware support for software SPI and TWI drivers
 Still a software driver but less resources required

 Higher transfer rates than pure software interfaces
- fkc/16 as TWI master and slave
- fkc/4 as SPI master or slave

 Polling and Interrupt support for
 Data reception
 Wakeup from sleep
- In TWI mode also from PWD

 TWI start condition detector

61


Memory Overview and Interconnection
 General purpose registers manage all data transfer
 Direct Program memory access

 Direct SRAM access
 EEPROM access via IO registers
 EEAR,EEDR,EECR

 Secure Program memory and

Register
File

EEPROM access
 Timed sequence

SRAM

I/O
Registers

EEPROM

Program
Memory

62


Flash Program Memory
 All AVR uses Flash program memory
 In-system (re-)programmable
 Both by programmer and application
 From 1.8 to 5.5V

 More flexibility compared to ROM, PROM and EPROM
 No external high voltage required
 Internal charge pump

 20 years retention time
 Minimum 10K erase/write cycles, typical 100K

63


Internal EEPROM Data Storage
 All AVRs with internal EEPROM for data storage
 Linear address space

 Size from 64B to 8K

 Byte accessible
 3 – 8ms Write time
 Including erase

 Instant read
 Interrupt controlled
 Handled through dedicated IO registers

 20 years retention time
 Minimum 100K erase/write cycles, typical 1M

64


Enhanced EEPROM Operation
 Split erase & program cycle to save time
 Traditionally erase and write one byte in one operation

 Enables pre-erasing of locations
 Faster interrupt handlers etc.

 Available on ATtiny13 and all newer devices

Exe. Time

Operation

3.4 ms

Erase and Write in one operation

1.8 ms

Erase only

1.8 ms

Write only

65


SRAM Data Memory

32 Registers
IO Registers
64 to 224

 Most AVR MCUs feature internal SRAM for data memory
 Linear address space
 Size from 64B to 16K (new!)

Internal
SRAM
64B to 8K

 Program and parameter stack in SRAM
 Five different addressing modes
 Direct
 Indirect
 Indirect with Displacement, Pre-dec and Post-inc

 Indirect addressing handled X,Y and Z pointer
 Data memory map

External
SRAM
up to 64K

 SRAM
 32x8 General Register File
 IO registers

 External SRAM through XRAM interface
 up to 64K
66


External Memory Interface
 Parallel Interface for external devices or peripherals
 Memory map linear with the internal SRAM

 Parallel bus with 8 data and 16 address lines
 Up to 64K memory map

 Dynamic pin allocation to release unused address pins
 4 Wait-state settings
D7:0

 Flexible timing settings

 Integrated Bus-keeper
 Lower power consumption

AD7:0

D

ALE

Q

A7:0

G

AVR

A15:8

SRAM
A15:8

/RD

/RD

/WR

/WR

67


Flexible Clock Options
 Crystal Oscillator
 Low Power Crystal Oscillator
 Full Swing Crystal Oscillator
 32kHz Low Frequency Crystal Oscillator

 Internal RC Oscillator
 Can be calibrated within ±1% for most devices

 Internal 128 kHz RC Oscillator (WDT)
 External Clock
 System Clock Prescaler (1 to 256)
 Lower system clock frequency while running
 Controlled by application

68


Internal EEPROM Data Storage
 Most AVR MCUs feature internal EEPROM for data storage


Linear address space

 Byte accessible
 3 – 8ms write time


Including erase

 Interrupt controlled
 Handled through dedicated IO registers
 20 years data retention time
 Minimum 100K erase/write cycles, typical 1M
AVR335, AVR104

69


ISP -

In-System Programming

 FLASH, EEPROM, Fuses and Lock Bits programmed in-system
 At all Frequencies

 At all supply voltages
1.8V – 5.5V

MISO

VTG

SCK

GND

SCK

ISP6PIN

GND

RST

GND

VTG

NC

MOSI

RST

 SPI interface used for ISP

MOSI

GND

MISO

 Exc.: ATmega128 !

ISP10PIN

 Only four pins + VCC and Ground required Relevant Application Note
 RESET

AVR109 AVR042

 MISO
 MOSI
 SCK
70

GND


Redefining ISP - Self-Programming
 The CPU can read and write its own program memory
 Enabling reprogramming while running an application
 Critical functions are still operating

 Any communication interface, including software-implemented interfaces

 Parameters can be stored in program memory
 In addition to EEPROM

71


LCD Controller/Driver

 Integrated segment LCD controller/driver


For monochrome passive liquid crystal display



No external LCD driver required

A
F

 100 and 160 segments


COM0

 Interrupt driven
Start Of Frame Interrupt

 Internal contrast voltage generator


SEG1

Unused LCD pins can be used as general IO

External capacitor as power reservoir

 Own AVR LCD family


100Segment : ATmega169P, ATmega329, ATmega649



SEG2

G

SEG0



B

E

C
COM1

D
COM2

AVR064 AVR065

160Segment : ATmega3290, ATmega6490...

72


42:
DIE ANTWORT AUF MEHR ALS EINE FRAGE.
HARDWARE DESIGN.

www.atmel.com

October 13


AppNote AVR042
AVR Hardware Design Considerations
AppNote AVR4100
Selecting and testimg 32 kHz Xtal…

www.atmel.com

October 13


13 JAHRE FAE – UND EIN BISSCHEN WEISER.
TIPPS UND STOLPERFALLEN.

www.atmel.com

October 13


Ports

 Doppelfunktionen bestimmter Pins beachten, zum Programmieren,
zum Debuggen, Analogfunktionen, ext. Interrupts,..

 Programmierung über SPI:
MOSI
MISO
SCK
Achtung: Beim ATmega128 und Pin-kompatiblen Bausteinen liegen die
Programmierpins NICHT an der SPI, sondern an der UART-Schnittstelle !

www.atmel.com

October 13


Manche Ports sind nur teilweise ausgeführt: beim 2313 fehlt
PortD.7, bei Ausführungen im PDIP (DIL) Gehäuse teilweise weniger
IO-Pins.

Konfiguration beim Einschalten ist INPUT. Ausgänge durch „1“ im
DDRx einstellenRS232:
RxD = PD0
TxD = PD1

JTAG-Debug-/Programmierschnittstelle

www.atmel.com

October 13


 Floating Inputs vermeiden: Ausgang oder Pullup (PORTx)

 Ausgabe über PORTx
 Pin Toggeln durch Schreiben einer „1“ nach PINx bei OUTPUT

 RESET Pin nach Bedarf beschalten: HV-Programming?
DebugWire? (siehe AVR042)

 RESET Pin darf während Debugging über DebugWire oder bei
Nutzung des PDI (Xmega) nicht mit Kondensator belastet sein

 Große Streuung bei Pullups (bis 500KOhm)
www.atmel.com

October 13


 Höhere Eingangsspannung als Vcc möglich, wenn Vorwiderstand
zur Begrenzung des Stroms durch die Schutzdioden (Beispiel
Nullspannungsdetektor) vorhanden

 Mehrere Ausgangspins innerhalb desselben Ports können
zusammengeschaltet werden, um Treiberleistung zu erhöhen. Dabei
Maximalbelastung von Port und Chip beachten!

 Nicht alle AVRs haben die 20mA Belastbarkeit der Ausgänge.
Ausnahmen sind einige ATtinys und die Xmegas.

20mA bei Einhaltung der Logikpegel, sonst 40mA
 Maximalbelastbarkeit ist abhängig von Betriebsspannung
www.atmel.com

October 13


 Bei Verwendung desselben Pins als Eingang für Taste und LED
Ausgang: Durchlass-Spannung der LED, Vcc und Logikpegel beachten!

 LEDs haben verschiedene Durchlass-Spannungen je nach Farbe
 Tasten in der Regel gegen Masse schalten und Pullups nutzen
 Bei induktiven Lasten zusätzliche Schutzdiode direkt an der Induktivität
(1N4148 besser als 1N4001, da schneller)

 Externe Interrupts: Ältere AVRs (z.B. ATmega32) haben nur wenige
INTx Pins, neuere (z.B. ATmega324P) haben externe Interrupts an allen
IO-Pins. Unterschiedliche Handhabung beachten.

 Ggf. Analogkomparator-Interrupt nutzen.
www.atmel.com

October 13


 BOD und POR sind unterschiedlich robust, z.B. Mega88P(V) besser als
ATmega88(V). Fußnoten im Datenblatt beachten - Table 28.3 Page 306
(M88) vs. Table 28.5 Page 318 (M88PA).

 Interne RC-Oszillatoren haben unterschiedlich ausgeprägten Jitter.

 Interne RC-Oszillatoren bei älteren Typen stärker temperaturabhängig.
 RC-Kalibrierung gilt nur bei der jeweiligenTemperatur.
 RC Oszillator angeblich durch Metall/Magnet von außen beeinflussbar
 UART braucht 2% genauen Takt, USB noch deutlich genauer
www.atmel.com

October 13


 Keine (unbenutzten) Komponenten an Quarzanschlüssen
 Full Swing nur bei 2.7 Volt und mehr
 „Sägezahn-Effekt“ bei parasitärer Speisung über externe Komponenten
und Schutzdioden.

 Programmierkabel nicht zu lang! Ggf. 10-Pin statt 6-Pin Belegung
 TWI-Kabel (I2C) nicht zu lang!
 Port-Erweiterungen über spezielle I2C-Chips, Schieberegister, ATF15xx
 Treiber für LEDs oder Induktive Lasten über I2C oder SPI mit
Schutzfunktionen bei Unterbrechung Kurzschluss, Übertemperatur.

www.atmel.com

October 13


 Low Cost Alternative zu MAX232: siehe Butterfly

 RC-Oszillator Kalibrierung bei UART Kommunikation: siehe Butterfly

www.atmel.com

October 13


GUT VERSTECKT IM DATENBLATT.
ATMEGA48
ATMEGA48PA

www.atmel.com

October 13


RECHENLEISTUNG
STATT
ELEKTRISCHE LEISTUNG.

www.atmel.com

October 13


AVR Oscillator Types
Cost
External high
frequency crystal
External low
frequency (32kHz)
crystal
External ceramic
resonator
External R/C
oscillator
Calibrated Internal
R/C oscillator
External clock

Accuracy

Startup time

High

High
(10-50 ppm)
High
(10-50 ppm)

Long
(16k cycles)
Long
(16k-32k
cycles)

Medium
(0.5-1%)
Depending on
R and C

Medium (2001k cycles)
Short
(6 cycles)

Medium

Medium
Low

±1% after
calibration
Depending on other
circuits in the system

NONE

Short
(6 cycles)
Short
(6 cycles)

Notes

Additional timer
oscillator on some
devices

May be re-calibrated by
application at any time

Use the internal RC for fast startup time and low power consumption
86


AVR Sleep Modes
 Idle mode


CPU Stopped, but oscillators and most
I/O modules active



Allows fast wakeup (immediate) from
sleep

 ADC Noise Reduction mode


Like Idle mode, but fewer I/O modules
active

 Power Down mode

 Power Save mode


Like Power-down mode, but 32kHz
timer oscillator running

 Standby mode


Like Power-down mode, but main
crystal/resonator oscillator running



Allows fast wakeup (6 cycles) from
sleep

 Extended Standby



Oscillator stopped, CPU stopped, most
functions inactive



Both main crystal/resonator oscillator
and 32kHz timer oscillator running



Slow wakeup from sleep, oscillator must
be restarted



Allows fast wakeup (6 cycles) from
sleep

88


AVR Sleep Modes - Example
 By using sleep modes, power consumption can be reduced by a factor
100
 Ideal for periods of inactivity – waiting for interrupts!
 Power Saving Example: Using the ATmega48


Use sleep modes and wait for wake-up condition



Internal RC @ 1MHz, 1.8 volt @ 25°C
mega48 Internal RC 1Mhz @ 1,8V 25'C

1000
250

ICC (uA)

100

10

Active

40

Idle
7,2

Power Save WDT
4,2

3

Power Save no WDT
Power Down WDT

1

Power Down no WDT
0,1

0,1
89


PicoPowerTM Technology
Key elements:
 (Almost) Zero current 32kHz oscillator

 Sleeping BOD
 Power Reduction Register (PRR)
 Digital Input Disable Register (DIDR)
 Flash sampling

 Low leakage process
 1.8V operation

 Power Save mode now 0.6 uA vs 10uA
 PicoPower AVR is #1 in Power Consumption & Performance

90


Low Current 32kHz Oscillator
 Power Save is the most highlighted ultra low power number
 Time in active is insignificant compared to time in PS for ULP

 The new 32kHz oscillator brings Power Save current almost to Power
Down.....

 0.6uA Power Save mode @ 2.2V
 ATmega165P: Typical 0.6uA
 32kHz running

 PicoPower Power Save mode is industry leading
 Less current consumption than MSP430F2 in PowerSave
91


Sleeping BOD (SBOD)
 SBOD enter sleep together with the AVR
 No need for BOD in sleep

 Wakeup from sleep first starts the SBOD, then the AVR
 Enabled by application
 Secure two step operation

 Automated operation when enabled
 No SBOD power consumption penalty while in sleep, full protection while
in active mode

92


Power Reduction Register - PRR
 Stop clock to individual peripherals
 Peripheral is in PWD sleep while rest of device is running

 Reduces overall power consumption

 PRR accessible by application while running
 When stopping the clock to a peripheral...
 The current state of the peripheral is frozen
 All I/O registers are inaccessible

 When re-starting a module...
 It continues in the same state as before shutdown

93


Digital Input Disable Registers - DIDR
 DIDR decreases overall
power consumption
 Shut off digital input buffers
on individual pins

 Enable DIDR on all ADC
pins
 Not required in Power-save,
Power-Down and Standby

94


PicoPowerTM AVRs
 Existing high volume megaAVRs will be upgraded
to PicoPower megaAVRs
 Special naming by the use of the letter ‘P’
 Example: ATmega169P

95


ATtiny23V/43V
 Operate from a single cell battery (1.4 V)
 Integrated Boost Regulator
 Autonomous analog block that is NOT controlled by the MCU
 Fixed 3.0V Vcc for the MCU from an external supply of 0.9V to 1.7V
 Starts up automatically when the voltage at the BATS pin is greater than 0.6V
(± 0.15V).
 Output voltage rises above POR and BOR levels (if enabled), the MCU will
start up
 Shuts down automatically when the voltage drops below 0.6V avoiding battery
drainage

 Alternatively the device can be operated directly from supply of 1.8 to 5.5
volts (LSW and BATS grounded)

96


DOPPELTE SICHERHEIT
SECURITY UND SAFETY

www.atmel.com

October 13


Internal Brown-Out Detection
 Reset when voltage level is below specification
 Preventing CPU run-away and EEPROM corruption.
 Flexible BOD levels
 Extremely fast detection (7 µs)
 BOD status bit set after reset
 MCUSR IO register
 BOD is optional
 BODEN fuse

98


WDT - WatchDog Timer
 Free running timer used to generate a System Reset allowed to time out
 Time-out period between 16ms and 8s set by prescaler
 Timer is reset by WDR instruction

 Prevents device from being trapped in dead loops
 WDT runs from it’s own clock source (RC Oscillator)

 WDT enabling through IO bits or Fuses
 Timed IO sequence for enabling and changes
 Safe WDT enabling through WDTON fuse

 Watchdog reset detectable by reading the WDRF flag
 Enganced WDT with WDT interrupt
 Interrupt instead of or prior to System Reset
 Suited for timing sequences, wake up from sleep etc.

Relevant Application Note
AVR132

99


Fuses and Lock Bits
 Fuses
 Programmable bits not accessible by application software for device settings
- Clock settings, BOD settings, Boot-Loader settings, etc.

 Not affected by chip erase

 Lock Bits
 Programmable security bits to secure IP stored in Flash and EEPROM
 Disables read and write access to Flash and EEPROM
 Only removed by chip erase
- Chip erase will also clear Flash and EEPROM

 Flexible settings for level of security and area to secure
- Own set of lock bits for self-programming

100


TOUCH ME – KAPAZITIV.

www.atmel.com

October 13


Atmel Touch Solutions

Buttons, Sliders, Wheels

Touch Software

Touchscreens

Application Specific
(“ready-to-use”)

Add touch functionality to your
general purpose Atmel MCU

Revolutionary Unlimited
Touchscreen Technology

1 – 48 Channels
Buttons, Proximity & Sliders
Self- & Mutual- Capacitance
No programming required
Limited Flexibility

1 – 64 Channels
Buttons, Proximity & Sliders
Self- & Mutual- Capacitance
Fully programmable
Excellent Flexibility
Excellent Integration

Single-Touch & Dual-Touch
devices also offered


QTouch

QMatrix

 Self-Capacitance

 Mutual-Capacitance



Robust and simple electrode design



Well defined key area for detection



Ideal for low node count



Ideal for high note count (>10 nodes)



Good proximity, providing better
sensing distance



Very resilient to moisture & environment



Passive tracking – longer tracks possible



Very resilient to noise and ground loading



Virtually any electrode shape possible



Easy to tune sensitivity

- Flooded X design

Vdd
SENSE
ELECTRODE

MCU
Xn

Cx
Ykn
Cs
Yn

GND


Evaluation and Development Kit
Ordering Code: ATQT600

3 Sensor boards
• 8 channel QTouch board
• 16 channel QTouch board
• 64 channel QMatrix board

3 MCU boards
• ATtiny88 (QTouch)
• ATmega324PA (QMatrix)
• ATxmega128A1 (QTouch)

Interface board
• 2-way debug data
• ISP Programmer
• Supports AVR / AVR32


WERKZEUGKASTEN:
WAS BRAUCHE ICH FÜR DEN START?

www.atmel.com

October 13


WAS JETZT – ASSEMBLER ODER C?

www.atmel.com

October 13


WIR FANGEN AN:
EIN ERSTES PROJEKT MIT STUDIO6

www.atmel.com

October 13

Atmel Studio 6
Integrating ARM and AVR Design

Copyright 2012 Atmel Corporation

Atmel Studio 6/SAM3 Press Presentation

2/28/12


Atmel Studio 6 – IDE
 Intelligent editor
 New Project Wizard with over 1,000 project examples
 Integrated GNU C/C++ Compiler
 Seamless connection to all
in-system debuggers
 Cycle accurate chip and peripheral simulator


Atmel Studio 6 – Atmel Software Framework
 Software Library
 Peripheral drivers

 Hardware abstraction
 Communication
 Graphics

 Standard APIs
 Easy code migration
 Support for ARM + AVR MCUs
 Common 8/32-bit platform

 ASF Explorer
 Manage ASF components
 Trace driver dependencies
 Easy access to documentation


Atmel Studio 6 – QTouch Composer
 QTouch Project Wizard
 Configure QTouch project

 Optimized QTouch library code
 Automatic power management

 Touch Wizard
 Automatic performance tests
 Optimal design recommendations

 Power Analyzer
 Real-time monitoring of MCU power
consumption
 Profiling and visualization


JTAGICE3

www.atmel.com

October 13


AVR Dragon
 Low cost development tool
 High performance

 Easy to use
 USB Connection
 USB Powered

 Combination of
 JTAGICE mkII ( $299)
 AVRISP mkII ($34)
 STK500 ($79)

 Programs all devices
 Debug support for devices <=32K

 Price: €49!

115


XPLAINED KIT

www.atmel.com

October 13


STK600

117


WIESO „ENTWANZEN“?

www.atmel.com

October 13


AVR JTAG interface
 The AVR JTAG interface is a integrated hardware module for:




In-System Programming
On-Chip Debugging
PCB test through Boundary-Scan

 Dedicated hardware module


All AVR resources present while debugging

- Except 4 pins for JTAG communication

 Supports all Vcc levels and Frequencies
 Complies to IEEE std 1149.1 (JTAG)


Joint Test Action Group (JTAG)

 JTAG interface in all AVRs with
16K program memory or more

119


AVR debugWIRE interface
 On-Chip Debugging via single wire interface
 Program flow control
 EEPROM and Flash memory access
 Peripheral access

 debugWIRE is a hardware module

1.8 - 5.5V
Vcc
JTAGICE MKII

dW(/RESET)

 Not a ROM monitor!
 All AVR resources present while debugging

AVR

 Supports all Vcc levels and Frequencies
GND

120


Enabling debugWIRE
 debugWIRE functionality is enabled by DWEN fuse
 Set by ISP or HV programming

 Cleared by debugWIRE or HV programming

 debugWIRE is disabled by default from Atmel
 debugWIRE require system clock in all sleep modes
 No PowerSave/PowerDown mode current consumption possible as long as
the DWEN fuse is set

121


WIE GEHT´S WEITER?

www.atmel.com

October 13


AVR XMEGA Technical Walk-Through



AVR XMEGA
 Extraordinary Low Power
 2nd generation picoPower ®

 True 1.6 V operation

 Exceptional Performance
 Up to 32 MIPS
 DMA Controller
 Event System

 Extreme Peripherals
 Leading Analog Integration
 Fast Crypto engine
 Rich feature set



XMEGA AVR core
 Code compatible with existing tinyAVR and megaAVR
 True RISC architecture

 True single cycle execution
 32 MIPS at 32 MHz
- 32 MHz 2.7V – 3.6V
- 12 MHz 1.8V – 2.7V

 32 GPR
 Harvard architecture

 DMA Controller
 Flexible Event System
 Programmable Multi level Interrupt Controller – PMIC
125


EBI- External Bus Interface
 2-port, 3-port or 4-port interface selectable in SW
 All external memories are directly mapped in AVR
 No banking

 Stack and variables anywhere

 Simultaneous support of SRAM and SDRAM possible
 Ex: memory mapped devices

 Up to 128 Mbit SDRAM

126


XMEGA Interrupt Controller
 4 interrupt levels
 NMI - Non Maskable Interrupts

 High, Medium and Low level

 Round robin priority possible for low level interrupts
 Ensures all interrupts are serviced

 All peripherals can also be controlled by polling



XMEGA Event system
 CPU and DMA independent Inter-peripheral communication

www.atmel.com

October 13


Event System
AVR CPU



XMEGA Event System
 8 Event Routing Channels
 Peripherals specify how to generate events
 Everything that can generate an interrupt
 Ex: Pin change, Timer overflow, ADC complete, Comparator toggle

 Peripherals specify how to use events
 Ex: Increment Timer, Output signal, Start ADC conversion

 Reduce the use of interrupts
 Event system ensures control of critical function
 Predictable reaction time of 2 chip clock cycles
 Safe fault protection

 Reduces power consumption – no CPU needed
 Works in Active and Idle mode


XMEGA DMA Controller
 Allows high-speed data transfer
 From memory to peripheral

 From memory to memory
 From peripheral to memory
 From peripheral to peripheral

 Main features
 4 channels
 From 1 byte to 16 Mbyte transfers
 Optional interrupt at end of transaction
 Multiple addressing modes
- Static, Increment, Decrement

 1, 2, 4 or 8 byte bursts
 Programmable priority between channels

CPU Load, SPI Communication
Data rate With DMA No DMA
250 kbps
0%
8%
500 kbps
0%
16 %
1 Mbps
1%
30 %
2 Mbps
1%
57 %
4 Mbps
2%
98 %


XMEGA Memories
 Flash

 Memory setup

 Application area for main program

Flash
16K + 4K
32K + 4K
64K + 4K
128K + 8K
256K + 8K

 Boot area for bootloader
 Application Table area for fail safe
EEPROM emulation

 EEPROM

SRAM
2K
4K
4K
8K
16K

EEPROM
1K
1K
1K
2K
4K

 EEPROM on all devices
 Byte and page accessible
 Optional memory mapped

 SDRAM

 SRAM
 Internal on all devices
 Optional external on some devices
- Up to 16 MB directly addressable
- Optional multiplexed address and data


 Optional external on some
devices
- Up to 128 Mbit directly
addressable
- 4-bit and 8-bit supported


XMEGA Analog to Digital Converter
 Features
 12 bit resolution

 2 MSPS ADC in XMEGA A
 200 kSPS ADC in XMEGA D
 Single or continuous conversion modes
 Connected to Event System

 Connected to DMA Controller
 Internal and External reference voltages

 Interrupt/event on compare result
 Interrupt if lower or equal
 Interrupt if higher or equal

 Interrupt/event on conversion complete


XMEGA ADC – Pipelined Conversion Channels





4 ADC conversion channels
8 – 16 external single-ended inputs per ADC
8 x 4 external differential inputs per ADC
4 internal inputs
 VCC, Bandgap, Temperature, DAC output

 1x, 2x, 4x, 8x, 16x, 32x or 64x gain
 Synchronous sampling in dual ADC devices



XMEGA Digital to Analog Converter
 Features:
 12 bit resolution

 Up to 1 MSPS conversion rate, 1 µs settling time
 Connected to Event System
 Connected to DMA Controller
 Two independent output channels per DAC



XMEGA Analog Comparators
 Selectable hysteresis
 0, 20mV, 50mV selectable

 Flexible input selections
 Any analog input pin
 Output from DAC
 Bandgap voltage reference
 64-level VCC scaler

 Flexible interrupts and events generation
 Window compare function by combining 2 comparators
 Possible to have comparator output on a pin



XMEGA Timer/Counter
 Multiple 16-bit Timer/Counters in each device








Counts chip clock (Timer) or events (Counter)
4 or 2 Output Compare on each Timer/Counter
4 or 2 Input Capture on each Timer/Counter
Programmable Top Value
Direction control
Flexible interrupts and events generation
Split option: 2 x 8 instead of 1 x 16 Bit

 High-Resolution Extension
 4x of chip clock = up to 128 MHz (256 MHz) operation

 Advanced Waveform Extension





Inverted and Non-inverted PWM Outputs
Dead Time Insertion
Fault protection mechanism
Available in all devices, but on 1-2 timer/counters only



XMEGA Real Time Counter
 Separate Timer for Asynchronous Clock
 Independent of other Timer/Counters

 Works in Power Save, Idle and Active mode

 16-bit timer with Programmable Prescaler
 Prescaler provides 1 Hz – 32 kHz input
 Programmable top value
 Compare register
 Max timeout 65 536 seconds (= more than 18 hours)

 Can generate Events and Interrupts
 Both overflow and compare match



XMEGA Clock Options
 32- and 2 MHz internal RC osc.
 +/- 1% accuracy over temp and
voltage with automatic run-time
calibration

 32.768 kHz internal RC osc.
 +/- 2% accuracy over temp and
voltage

 400 kHz – 16 MHz Crystal osc.
 For accurate timing in application

 32.768 kHz Crystal oscillator
 for 32 kHz watch crystal

 500 nA current consumption

 32 kHz ULP RC oscillator
 For WDT and BOD
 1A power consumption

 Internal PLL for high-freq clock
generation
 400 kHz – 32 MHz input

 8 – 128 MHz output
 Max 32 MHz output to main
system clock



XMEGA Serial Communication Modules
 USART
 Full duplex asynchronous or synchronous operation
 Can also be SPI master
 Baud Rate Generator with fractional divider
- UART frequency crystals not needed

 SPI – Serial Peripheral Interface
 Full duplex, three-wire synchronous data transfer

 TWI – Two Wire Interface
 I2C compatible
 SMbus compatible
 Fast data rate on slow chip clock
- Clock / 10 for master operation
- Asynchronous slave operation


XMEGA A USB Device
 USB added to all XMEGA A products
 New ordering codes for all XMEGA A with USB
 ATxmega128A1-AU -> ATxmega128A1U-AU

 USB 2.0 Compliant Device
 Low and Full speed operation
 32 configurable endpoints

 High throughput with minimim CPU load
 Support DMA and large transactions without interrupt

 Free device class software library
 CDC, DFU, HID, Mass Storage, Audio, ...

141


XMEGA Crypto engine
 AES
 128-bit key length

 Encryption of 16 bytes in 375 clock cycles
 Decryption of 16 bytes in 375 clock cycles

 DES
 56-bit key length
 Encryption of 8 bytes in 16 clock cycles
 Decryption of 8 bytes in 16 clock cycles

 Supports up to 4 Mbps AES encrypted communication
 Supports up to 3.2 Mbps Tripple-DES encrypted communication


Crypto Performance
 AES an DES crypto for high speed encrypted communication
 Offload CPU and reduce power
Max encrypted
communication rate

UART

SPI

Vs. Software

128-bit AES

4 Mbps

3.2 Mbps

10x faster

Tripple-DES

3.2 Mbps

2.3 Mbps

100x faster

 XMEGA with crypto is authorized for export to all contries
 ECCN 5A002A.1

 XMEGA enables crypto communication for low power applications



XMEGA I/O Pins
 IN, OUT and DIR registers for safe read modify write operations
 Virtual registers for easy pin manipulation



Move IN, OUT and DIR control to bit addressable memory area
Port Toggle, Clear and Set registers for easy and glitch free pin manipulation

 Advanced pin configurations
Push-pull

Push-pull w/ buskeeper


Push-pull w/pull-up

Wired AND w/ optional pull-up

Push-pull w/pull-down

Wired OR w/ optional pull-down

October 13


2nd generation picoPower
 All picoPower features included
 New sampled BOD

 New low power Watchdog Timer
 New Event system controls peripherals in Idle mode
 New DMA moves data in Idle mode

 Lowest power consumption
 100 nA Power Down (RAM retention)

 550 nA Power Save (Real Time Counter)
 5 µs wake-up from sleep



2nd generation picoPower
 Industry leading in low power applications

 True 1.6V operation
 Flash, Analog, EEPROM, Oscillators down to 1.6V
 Enable 1.8V +/-10% power supply

 Lowest power 32 kHz Crystal Oscillator
 550nA RTC

 Low leakage Process Technology
 100nA for all devices

 1 µA Watchdog and Brown-Out

146
146



XMEGA Special Features
 Calibration memory

 Oscillator failure detection

 Readable from application

 Memory lock bits

 Factory calibration

 Brown-Out Detector

 User calibration
- Can be modified by customer

 Not affected by Chip Erase or
SPM

 Serial numbers
 Unique identifier
 Random number seed

 Dynamic Clock Switching

 Very fast
 Low power
 Off, 1 kHz sampled or On

 Watchdog Timer
 Separate oscillator

 Clock generation
 Clock output

 CRC checksums
 Available on locked devices



XMEGA B Family Overview
 Adds LCD to XMEGA family
 Reuse modules from XMEGA A
and XMEGA D
 XMEGA B family:






64 – 100 pins
64 – 256 KB Flash
6 – 32 KB SRAM
LCD driver
1.6 – 3.6V operation
- 12 MHz from 1.6V
- 32 MHz from 2.7V

 XMEGA B Features









Segment LCD driver
USB Device + Host
Up to 3 16-bit Timer/Counter
Up to 2 USART, 1 SPI, 1 TWI
12-bit 200 ksps ADC w/gain
2 Analog Comparators
Event System
CRC-16/32 support

150
150

Mar 2009

1


XMEGA C Family Overview
 Adds USB Host to XMEGA family
 Compatible to XMEGA D, but adds
USB Device and Host
 XMEGA C family:

 XMEGA C Features

 64 pins

 USB Device + Host

 64 – 256 KB Flash

 5 16-bit Timer/Counter

 4 – 16 KB SRAM

 3 USART, 2 SPI, 1 TWI

 1.6 – 3.6V operation

 12-bit 200 ksps ADC w/gain

- 12 MHz from 1.6V

 2 Analog Comparators

- 32 MHz from 2.7V

 Event System

- USB from 2.7 to 3.3V

 CRC-16/32 support

153
153

Mar 2009

1


XMEGA C USB Module
 USB 2.0 Compliant Device and Host
 Low and Full speed operation, up to 12 Mbps

 32 Endpoints - maximum number in USB specification
 Easy to use
 High throughput
 Ping-pong mode to increase bandwidth
 Multi-packet feature to reduce number of interrupts

 Data buffers and endpoint configuration in SRAM
 Low cost with maximum flexibility

 Only the amount of SRAM needed will be allocated

 USB pins multiplexed with I/O pins, no dedicated pins
 3.0 to 3.6V VCC during USB communication
Mar 2009

1


XMEGA D Family Overview
 Lowest cost XMEGA family
 Compatible to XMEGA A with
reduced feature set
 XMEGA D family:

 XMEGA D Features

 44 – 64 pins

 Up to 5 16-bit Timer/Counter

 16 – 256 KB Flash

 Up to 3 USART, 2 SPI, 1 TWI

 2 – 16 KB SRAM

 12-bit 200 ksps ADC w/gain

 1.6 – 3.6V operation

 2 Analog Comparators

- 12 MHz from 1.6V

 Event System

- 32 MHz from 2.7V

155
155

Mar 2009

1


AVR XMEGA E target specification






Sixteen-channel 12-bit 300 ksps ADC
Two-channel 12-bit 300ksps DAC
Two Analog Comparators
Two standard 16-bit Timer/Counters
One high-end 16-bit Timer/Counter









Optimized for ballast, LED, induction control, DC/DC supply/converter, motors,
buck/boost converter, wireless charger, battery charger

RTC with digital calibration and correction for XTAL error
Two USARTs with master SPI
I2C master and slave, up to 1MHz support
One SPI
4-channel peripheral DMA controller
Device
Flash
8-channel event system


Asynchronius event routing

RAM

EEPOM



26 I/O pins

32KB

4KB

1KB

ATxmega16E5

 32-pin packages

ATxmega32E5

16KB

2KB

1KB

ATxmega8E5

8KB

1KB

512b


AVR XMEGA E Analog to Digital Converter
 300 ksps
 12 bit resolution
 Single or continuous conversion modes
 Connected to Event System
 Connected to DMA Controller
 Internal and External voltage references


AVR XMEGA E Digital to Analog Converter
 12 bit resolution
 Up to 300 ksps conversion rate
 Connected to Event System
 Connected to DMA Controller
 Two independent output channels


AVR XMEGA E Analog Comparators
 Selectable hysteresis
 0, ~20mV, ~50mV selectable
 Flexible input selections
 Any analog input pin
 Bandgap voltage reference
 64-level VCC scaler
 Interrupts and events generation
 Window compare function by combining 2 comparators
 Detect level inside or outside window
 Possible to have comparator output on a pin


AVR XMEGA E Timer/Counter
 One 16-bit timer/counter type 4 (high end)
 4 Output Compare Channels with 8 outputs
- 4 non-inverted output (High Side)
- 4 inverted output (Low Side)

 Dead-time insertion between high- and low-side

 Fault protection with asynchronous PWM shut-down
- Multiple and selectable triggers and restart conditions

 High-resolution extension
- Increase PWM resolution up to eight times (4 nS period)

 Two 16-bit timer/counters type 5 (standard)
 2 Output Compare or Input Capture Channels
 High-resolution extension


Serial Communication Modules
 USART
 Full duplex asynchronous or synchronous operation

 SPI master mode
 Baud Rate Generator with fractional divider
- UART frequency crystals not needed
 SPI – Slave Serial Peripheral Interface
 Full duplex, three-wire synchronous data transfer
 Double buffered receive and transmit
 TWI – Two Wire Interface
 One master operation interface
 One slave operation interface
 100kHz, 400Khz and 1MHz operation
 I2C and SMbus compatible


AVR XMEGA E Real Time Counter
 Separate Timer for Asynchronous Clock
 Independent of other Timer/Counters
 Works in Power Save, Idle and Active mode

 16-bit timer with Programmable Prescaler





Prescaler provides 1 Hz – 32 kHz input
Programmable top value
Compare register
Max timeout 65 536 seconds (= more than 18 hours)

 Can generate Events and Interrupts
 Overflow and compare match

 Digital calibration and correction for 32-768kHz XTAL error
 Correction of mount error down to +/- 1 ppm accuracy


XMEGA Custom Logic Overview (XCL)
 Two independent units including:
 8-bit timer/counter
 Glue logic with programmable look up table (LUT)
- Defines a truth table of logical condition between inputs
- Delay elements for filter and synchronistaion

 Can be cascaded for more powerful features
 16-bit timer/counter, larger LUT
CPLD
CPLD0
Timer/Counter

Control Logic
Timer Period
Counter
Delay
Glue Logic

I
N
T
E
R
C
O
N
N
E
C
T

CPLD1
Timer/Counter

Control Logic
Timer Period
Counter
Delay
Glue Logic

Prescaler
I/O Pins
Event System
USARTs
Interrupts
Events

CLKPER


AVR XMEGA E XCL - 8-bit Timer/Counters
 Two 8-bit timer/counter, with 16-bit cascade otion





Normal operation
Single-slope PWM
Input capture and frequency capture
LUT input

 Peripheral configuration:
 Receive events from selectable USART
- For count and restart actions,

 Provide event to USART

 Applications:
 UART, USART, master SPI with variable data length in
- 1 – 256-bit data lenght wthout software and I/O pin overhead

 Enables LIN and DALI communication
 Sensor applications: no IO pin need to signalize slot where data is
valid


AVR® XMEGATM – Basics

XMEGA Training: Basics


Introduction (1/2)
 AVR XMEGA datasheet information is divided in two parts:
Family Manual

Device datasheets

ATxmega A manual

ATxmega64A1 / 128A1 / ...


Introduction (2/2)
 AVR XMEGA has more advanced header files for C programming than
previous AVRs.

 Slightly different syntax
 More advanced, not more complicated
 Better use of the features in the C language


The header file differences
 What is different?
 structs are used for registers of a peripheral

 Bit masks, bit positions, group masks, group configurations for configuring
bits in each register

 Why the change?
 Easier to configure registers correctly
 Much easier to write generic drivers


Register Names
 Longer descriptive names preferred over complex short forms
 DDRA is now PORTA.DIR

 PINA is now PORTA.IN
 UCSR0A is now USARTC0.CTRLA (This is USART 0 on port C)

 Try to avoid control-and-status registers
 Easier to read, write, and remember
 Application Note AVR1000


Register configuration

 Bit position
 PORT_SLREN_bp = 7

 Bit mask
 PORT_SLREN_bm = 0b1000 0000 = 0x80

 Group mask
 PORT_OPC_gm = 0b0011 1000 = 0x38

 Group configuration
 PORT_OPC_PULLUP_gc = 0b0001 0000 = ( 0x02 << 3)


Bit mask/bit position
 Use bit mask directly for setting a bit:
 PORTD.PIN0CTRL |= PORT_SRLEN_bm

 Or alternatively use bit position (like Mega/Tiny AVR):
 PORTD.PIN0CTRL |= ( 1 << PORT_SRLEN_bp )

 XMEGA header file definition:
#define PORT_SRLEN_bm 0x80 // Slew Rate Enable bit mask
#define PORT_SRLEN_bp 7 // Slew Rate Enable bit position


Register Bits usage
 Single control and status bits
 Mask PORT_INVEN_bm and position PORT_INVEN_bp

 Set bit:
- PORTA.PIN0CTRL |= PORT_INVEN_bm;
PORTA.PIN0CTRL |= (1 << PORT_INVEN_bp);

 Clear bit:
- PORTA.PIN0CTRL &= ~PORT_INVEN_bm;
PORTA.PIN0CTRL &= ~(1 << PORT_INVEN_bp);


Group mask
 Useful for clearing all bits of a specific configuration in a register
 Example:
 PORT_OPC_gm

 XMEGA header file definition:
 #define PORT_OPC_gm 0x38 // Output/Pull Configuration
group mask

 #define PORT_OPC_bp 3 // Output/Pull Configuration group
position


Group configuration
 Group configuration
 One specific configuration of a group of bits

 Group configurations defined as enum in header file
 typedef enum PORT_OPC_enum { … } PORT_OPC_t;
 Value something defined as PORT_OPC_something_gc
 Enumerator types useful as function parameters – automatic checking


Group configuration
 Example:
 PORT_OPC_PULLDOWN_gc
 All available configurations are shown in the XMEGA manual


Group mask and group configuration usage
 Changing configuration – compact and efficient

 Clear all bits of previous configuration and set new configuration:
 PORTA.PIN0CTRL = ( PORTA.PIN0CTRL &
~PORT_OPC_gm ) |
PORT_OPC_PULLDOWN_gc;


XMEGA header files
 If the definitions on the previous slides do not make sence to you:

 Don’t need to know how the peripherals are defined, but how to use it:
 PORTA.OUT = 0xff
 unsigned char value = PORTB.IN


XMEGA I/O Ports
 Direction control
 PORTx.DIR

 Input and output
 PORTx.IN and PORTx.OUT

 Manipulation of direction register bits
 PORTx.DIRSET, PORTx.DIRCLR, and PORTx.DIRTGL

 Manipulation of output register bits
 PORTx.OUTSET, PORTx.OUTCLR, and PORTx.OUTTGL



XMEGA I/O Ports


Output and Pull Configuration
 Individual pin control
 Pull-up or pull-down
 PORT_OPC_PULLUP_gc or PORT_OPC_PULLDOWN_gc

 Wired-AND or wired-OR
 PORT_OPC_WIREDAND_gc or PORT_OPC_WIREDOR_gc

 Bus keeper support
 PORT_OPC_BUSKEEPER



Configuring multiple pins
 Several pins can be configured at the same time

 MPCMASK register sets which pins are affected
 The following configuration of a pin is applied to all pins set in
MPCMASK
 Example:
 PORTA.MPCMASK = 0x0F;
 PORTA.PIN0CTRL =
( PORTA.PIN0CTRL & ~PORT_OPC_gm ) |
PORT_OPC_PULLUP_gc ;
→ All pins configured as pullup


Pointers to Peripheral Modules
 Allows for generic code and drivers
 Access modules through pointers

 Some overhead when dereferencing pointers
 Great flexibility, saves code space

 Module struct allows for pointer referencing
 PORT_t * ledPort = &PORTD;
 void SetLEDs( PORT_t * port, unsigned char value );


Timer/Counter
 Wide range of 8- and 16-bit Timer/Counters (TCNT)
 The AVR Timer/Counters can use various clock sources
 Main CPU clock
 Internal High speed PLL
- High speed, 64MHz

 By external clock source
- Max speed XTAL/2

 External 32kHz asynchronous crystal
 All clock sources can be pre-scaled before being fed to the Timer/Counters

 T/C are interrupt driven and controlled through the AVR IO memory

184


Timer/Counter Features
 Overflow detection with interrupt
 Compare match detection with Interrupt




Own compare value registers
Pin change on compare match
TCNT clear on compare match

 Input Capture with Interrupt and Noise Canceller



Own capture counter value register
Input capture by the Analog comparator

 Real Time Counter with 32 kHz oscillator


Asynchronous to the main clock; separate 32kHz Crystal

 Pulse width Modulation (PWM) functionality





Selectable 2-Bit to 16-Bit Resolution on devices with 16-Bit Timer
High speed, up to 250kHz
Phase and Frequency Correct
PWM mode
Variable TOP value

AVR134 AVR304
185


ERGÄNZUNGEN ZU UC3A3 (AUDIO) & UC3L

www.atmel.com

October 13

AVR and AVR32 TMM Call 4. May 2009

EVK1105 Digital Audio Gateway


Reference Design
 EVK1105 demonstrates the full potential of AVR32 AT32UC3A0512 in
digital audio applications
 Software audio decoders


Be prepared for changes in digital audio formats

 Complete HW and SW Reference Design






Play MP3 and WMA from a USB Mass Storage device
Control your iPod
Prepared for Internet radio
Prepared for Bluetooth®
Prepared for IEEE 802.15.4 / Zigbee PRO

Mar 2009

1


Target Applications
 USB Docking Station
 MP3 Player / iPod
 Mobile Phone / PDA
 Camera

 SD Card Player
 Car Radio
 Home Stereo
 Internet Radio
 Speaking appliances

Mar 2009

1


AT32UC3A3


Introducing the new AVR32 AT32U3A3
 Audio playback


Single chip solution



Software audio decoding



High quality playback



iPod docking

 High speed communication


Hi-Speed USB



Dual SD card



NAND w/MLC ECC



Distributed SRAM

 Target Markets


Audio Playback



USB to SD Card Bridges



USB Dongles



USB Tokens
Mar 2009

1


AVR32 UC3A3 – It is all about true performance

Instr.

MemIF
SRAM
64 KB

Data

 Improved DMA transfer speed
 Peripheral DMA

6-layer High Speed Bus Matrix

 Memory to Memory DMA
Peripheral Bridge

Peripheral DMA
Controller: 18 channels

USB
On-The-Go

 Eliminate on-chip
communication bottleneck
 Avoid DMA collision
 Remove delay and latency

PDC

PDC

PDC

PDC

USART

SPI
x2

TWI
x2

SSC
x1

x4

PDC

Timer PWM
3 ch 3 ch

PDC

ADC
8 ch

Audio
DAC

User Peripherals

Mar 2009

1

EBI / ECC

MPU

SRAM 32 KB

 2 x 32 KB BUS SRAM

AVR32 CPU
66 MHz

Flash

 64 KB dual port CPU RAM

JTAG/
Nexus
OCD

SRAM 32 KB

 128 KB SRAM on-chip SRAM
split into 3 regions


EVK1104 – AVR32 UC3A3 Evaluation Kit

Mar 2009

1


AT32UC3L - picoPower


UC3L
 picoPower™ Technology


Industry’s lowest power consumption



Down to 0.5 mW/MHz



1.6µA with RTC running



100nA in Shutdown mode



SleepWalking™



1.62 – 3.6V operation

 Integrated Hardware QTouch


Use QTouch as any other peripheral



Wake up from sleep with a touch button

 FlashVault™ code protection


Partially program and lock the flash



Protect your software IP

Mar 2009

1


UC3L – Further Cutting Edge Innovations
Improved Reliability and Reduced Cost

 Peripheral Event System
 PWM on all GPIO pins
 High precision clock system








Digital frequency lock loop
Crystal osc. precision tuner
Clock failure protection
Ultra low power oscillators
Frequency meter
RTC with calendar mode
Windowed watchdog timer

 9 channel 12 bits ADC
 8 channel Analog Comparator
 Advanced Debug Functionality
 Advanced Trace

Mar 2009

1


QUIZ MIT PREISVERLEIHUNG

www.atmel.com

October 13

AVR Microcontroller

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