The document describes the design of a two-stage RC coupled common emitter (CE) amplifier with an overall gain of 1000. It provides the specifications and components required. The design methodology uses a top-down approach, first determining the two-port parameters of each stage and then selecting component values to meet the specifications. Resistors and capacitors are selected to achieve the desired gains of 25 for the first stage and 40 for the second stage, while meeting the bandwidth and input/output impedance requirements.

1. EC 204: ANLOG CIRCUITS LABORATORY
Experiment 2
Two Stage CE Amplifier
Sachin Rajoria 08010826
Payoj Kissan 08010823
Manzil Zaheer 08010252
To design a two-stage RC coupled CE amplifier with the given specifications.

2. Objective:
To design a two-stage RC coupled CE amplifier with the following specifications:
 Overall Gain: 𝐴𝐴𝑣𝑣𝑠𝑠
= 1000
o Gain of first stage: |𝐴𝐴1| = 25
o Gain of second stage: |𝐴𝐴2| = 40
 Signal Source Resistance: 𝑅𝑅𝑠𝑠 = 50 Ω
 Load resistance: 𝑅𝑅𝐿𝐿 = 1 𝑘𝑘Ω
 Bandwidth (-3 dB) = 20 Hz – 20 kHz
 Assume range of β = 100 – 200
Instruments/Materials Required:
1. Supply Voltage: 12V x 1
2. Transistors:
i. NPN transistor 2N2222 x 2
3. Capacitors
i. 1 mF x 2
4. Resistors:
i. 100 Ω x 2
ii. 200 kΩ x 2
iii. 330 Ω x 1
5. Signal Source (Function Generator with 𝑅𝑅𝑠𝑠 = 50 Ω) x 1
6. Breadboard x 1
7. Connecting wires
Design Methodology:
The design is simplified to a large extent, if we use top-down approach to solve the problem. Consider
the two-port equivalent of each amplifier stage first and determine the parameters defining the
amplifier. Then we design the internals of each stage of amplifier to match the parameters obtained in
the previous step. Finally, we consider the frequency response of the amplifier.
Two Port Equivalent of a single stage CE amplifier
A general CE amplifier has the circuit as shown in fig. 2 and its small signal two port equivalent as shown
in fig. 1.
𝑉𝑉𝑖𝑖
+
-
𝑍𝑍𝑖𝑖
𝑍𝑍𝑜𝑜
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁
Amplifier
𝑉𝑉𝑜𝑜
+
-

3. Input Impedance 𝒁𝒁𝒊𝒊:
𝑍𝑍𝑖𝑖 = 𝑅𝑅𝑎𝑎 ∥ 𝑅𝑅𝑏𝑏 ∥ 𝛽𝛽(𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒)
Output Impedance 𝒁𝒁𝒐𝒐:
𝑍𝑍𝑜𝑜 = 𝑟𝑟𝑜𝑜 ∥ 𝑅𝑅𝐶𝐶
For 𝑟𝑟𝑜𝑜 ≥ 10𝑅𝑅𝐶𝐶,
𝑍𝑍𝑜𝑜 ≅ 𝑅𝑅𝐶𝐶 𝑟𝑟𝑜𝑜 ≥10𝑅𝑅𝐶𝐶
No Load Voltage gain 𝑨𝑨𝒗𝒗 𝑵𝑵𝑵𝑵
:
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁
=
𝑉𝑉𝑜𝑜
𝑉𝑉𝑖𝑖
= −
𝑟𝑟𝑜𝑜 ∥ 𝑅𝑅𝐶𝐶
𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒
Or
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁
=
𝑉𝑉𝑜𝑜
𝑉𝑉𝑖𝑖
≅ −
𝑅𝑅𝐶𝐶
𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒 𝑟𝑟𝑜𝑜 ≥10𝑅𝑅𝐶𝐶
Rb
Ra
Rc
Re2
Cc
Cc
Ce
Re1
Q1
𝑉𝑉𝑜𝑜
+
-
𝑉𝑉𝑖𝑖
+
-

4. Obtaining the two port parameters of second stage amplifier
Basically the required amplifier has the following form:
For maximum power transfer from second stage of amplifier to the load, we need
𝑍𝑍𝑜𝑜2
= 𝑅𝑅𝐿𝐿 = 1 𝑘𝑘Ω
So, gain of second stage becomes,
𝐴𝐴𝑣𝑣2
=
𝑅𝑅𝐿𝐿
𝑍𝑍𝑜𝑜2
+ 𝑅𝑅𝐿𝐿
𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿2
𝐴𝐴𝑣𝑣2
=
1
2
𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿2
We are already been given �𝐴𝐴𝑣𝑣2
� = 40, therefore we need to have,
�𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿2
� = 2�𝐴𝐴𝑣𝑣2
� = 80
Complete Design of second stage amplifier
For faithful amplification (i.e. maximum undistorted output voltage swing), the quiescent point should
be near the middle of the load line,
𝑉𝑉𝐶𝐶 = 0.5𝑉𝑉𝐶𝐶𝐶𝐶 = 6𝑉𝑉
𝑉𝑉𝐸𝐸 = 0.1𝑉𝑉𝐶𝐶𝐶𝐶 = 1.2𝑉𝑉
We know from two-port analysis, 𝑍𝑍𝑜𝑜2
= 1 𝑘𝑘Ω, therefore
𝑅𝑅𝐶𝐶 = 𝑍𝑍𝑜𝑜 = 1 𝑘𝑘Ω
So, we have a collector current of
𝐼𝐼𝐶𝐶 =
𝑉𝑉𝐶𝐶𝐶𝐶 − 𝑉𝑉𝐶𝐶
𝑅𝑅𝐶𝐶
=
(12 − 6) 𝑉𝑉
1 × 103 Ω
= 6 𝑚𝑚𝑚𝑚
𝑉𝑉𝑖𝑖2
+
-
𝑉𝑉𝑜𝑜2
+
-
𝑉𝑉𝑖𝑖1
+
-
𝑍𝑍𝑖𝑖1
𝑍𝑍𝑜𝑜1
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁 1
Amplifier I
𝑉𝑉𝑜𝑜1
+
-
𝑍𝑍𝑖𝑖2
𝑍𝑍𝑜𝑜2
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁 2
Amplifier II
𝑅𝑅𝑠𝑠
𝑅𝑅𝐿𝐿𝑉𝑉𝑠𝑠

5. We can safely assume 𝐼𝐼𝐶𝐶 ≅ 𝐼𝐼𝐸𝐸, therefore 𝐼𝐼𝐸𝐸 = 6𝑚𝑚𝑚𝑚
𝑅𝑅𝐸𝐸 = 𝑅𝑅𝐸𝐸1
+ 𝑅𝑅𝐸𝐸2
=
𝑉𝑉𝐸𝐸
𝐼𝐼𝐸𝐸
=
1.2
6 × 10−3
= 200 Ω
Under these conditions,
𝑟𝑟𝑒𝑒 =
𝑉𝑉𝑡𝑡
𝐼𝐼𝐸𝐸
=
26 × 10−3
𝑉𝑉
6 × 10−3 𝐴𝐴
= 4.333 Ω
Finally from gain expression we can evaluate 𝑅𝑅𝐸𝐸1
as,
�𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁
� = 80 =
𝑅𝑅𝐶𝐶
𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒
80 =
1000
𝑅𝑅𝐸𝐸1
+ 4.333
𝑅𝑅𝐸𝐸1
= 8.167 Ω
And so,
𝑅𝑅𝐸𝐸2
= 191.8333 Ω
Now, for finding voltage divider resistances 𝑅𝑅𝑎𝑎 and 𝑅𝑅𝑏𝑏 , we need that the current flowing through the
potential divider circuit has to be large as compared to the actual base current, 𝐼𝐼𝐵𝐵, so assume a value of
atleast 10 times 𝐼𝐼𝐵𝐵 flowing through the resistor 𝑅𝑅𝑏𝑏.
Approximately the base current is at the most,
𝐼𝐼𝐵𝐵 =
𝐼𝐼𝐶𝐶
𝛽𝛽
=
6𝑚𝑚𝑚𝑚
100
= 60𝜇𝜇𝜇𝜇
∴ 𝑅𝑅𝑏𝑏 ≤
𝑉𝑉𝐸𝐸 + 𝑉𝑉𝐵𝐵𝐵𝐵
10 × 𝐼𝐼𝐵𝐵
=
(1.2 + 0.7) 𝑉𝑉
600 × 10−6 𝐴𝐴
= 3.167 𝑘𝑘Ω
Also from the voltage divider constraint,
𝑅𝑅𝑏𝑏
𝑅𝑅𝑏𝑏 + 𝑅𝑅𝑎𝑎
× 𝑉𝑉𝐶𝐶𝐶𝐶 = 𝑉𝑉𝐸𝐸 + 𝑉𝑉𝐵𝐵𝐵𝐵
𝑅𝑅𝑏𝑏
𝑅𝑅𝑏𝑏 + 𝑅𝑅𝑎𝑎
× 12 = 1.9
𝑅𝑅𝑎𝑎 ≈ 5.3 𝑅𝑅𝑏𝑏
So, input impedance turns out to be,
𝑍𝑍𝑖𝑖 = 𝑅𝑅𝑎𝑎 ∥ 𝑅𝑅𝑏𝑏 ∥ 𝛽𝛽(𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒)

6. This evaluates to (after taking into account the fact that standard values have to be used),
𝑍𝑍𝑖𝑖 = (10||2||1.25) 𝑘𝑘Ω = 697Ω
Emitter-bypass capacitor for lower frequency response of 20Hz at -3 dB,
𝐶𝐶𝐸𝐸 =
1
2𝜋𝜋𝑅𝑅𝑒𝑒𝑒𝑒 𝑓𝑓𝐿𝐿
In this case 𝑅𝑅𝑒𝑒𝑒𝑒 = 𝑅𝑅𝐸𝐸2
∥ (𝑟𝑟𝑒𝑒 + 𝑅𝑅𝐸𝐸1
+
𝑍𝑍𝑜𝑜1∥𝑅𝑅𝑎𝑎 ∥𝑅𝑅𝑏𝑏
𝛽𝛽
) ≈ 16.05 Ω,
∴ 𝐶𝐶𝐸𝐸 ≈ 496 𝜇𝜇𝜇𝜇
Upon use of standard Components
Component Theoretical Desired Value Nearest standard value
𝑅𝑅𝐶𝐶 1 𝑘𝑘Ω 1 𝑘𝑘Ω
𝑅𝑅𝐸𝐸1 8.167 Ω 8.2 Ω
𝑅𝑅𝐸𝐸2 191.833 Ω 200 Ω
𝑅𝑅𝑏𝑏 3.167 𝑘𝑘Ω 2 𝑘𝑘Ω
𝑅𝑅𝑎𝑎 𝑅𝑅𝑎𝑎 ≈ 5.3 𝑅𝑅𝑏𝑏 = 10.6 𝑘𝑘Ω 10 kΩ
𝐶𝐶𝑐𝑐 496 𝜇𝜇𝜇𝜇 1 𝑚𝑚𝑚𝑚

7. Obtaining the two port parameters of first stage amplifier
Basically the required amplifier has the following form:
For maximum power transfer from first stage of amplifier to the second stage, we need
𝑍𝑍𝑜𝑜1
= 𝑍𝑍𝑖𝑖2
= 697 Ω
But we choose nearest standard value, 𝑍𝑍𝑜𝑜1
= 500 Ω
We assume that the input impedance of this stage will be near to the input impedance of the second
stage, i.e.
𝑍𝑍𝑖𝑖1
≈ 𝑍𝑍𝑖𝑖2
≈ 600 Ω
So, gain of first stage becomes,
𝐴𝐴𝑣𝑣𝑠𝑠1
= �
𝑍𝑍𝑖𝑖1
𝑍𝑍𝑖𝑖1
+ 𝑅𝑅𝑠𝑠
� �
𝑍𝑍𝑖𝑖2
𝑍𝑍𝑖𝑖2
+ 𝑍𝑍𝑜𝑜1
� 𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿1
= �
600
600 + 50
� �
697
500 + 697
� 𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿1
𝐴𝐴𝑣𝑣𝑠𝑠1
= 0.5375𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿1
We are already been given �𝐴𝐴𝑣𝑣1
� = 25, therefore we need to have,
�𝐴𝐴𝑣𝑣 𝑁𝑁 𝐿𝐿1
� = 1.86�𝐴𝐴𝑣𝑣1
� = 46.5
Complete Design of second stage amplifier
For faithful amplification (i.e. maximum undistorted output voltage swing) , the quiescent point should
be near the middle of the load line,
𝑉𝑉𝐶𝐶 = 0.5𝑉𝑉𝐶𝐶𝐶𝐶 = 6𝑉𝑉
𝑉𝑉𝐸𝐸 = 0.1𝑉𝑉𝐶𝐶𝐶𝐶 = 1.2𝑉𝑉
We know from two-port analysis, 𝑍𝑍𝑜𝑜1
= 500 Ω, therefore
𝑅𝑅𝐶𝐶 = 𝑍𝑍𝑜𝑜 = 500 Ω
𝑉𝑉𝑖𝑖2
+
-
𝑉𝑉𝑜𝑜2
+
-
𝑉𝑉𝑖𝑖1
+
-
𝑍𝑍𝑖𝑖1
𝑍𝑍𝑜𝑜1
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁 1
Amplifier I
𝑉𝑉𝑜𝑜1
+
-
𝑍𝑍𝑖𝑖2
𝑍𝑍𝑜𝑜2
𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁 2
Amplifier II
𝑅𝑅𝑠𝑠
𝑅𝑅𝐿𝐿𝑉𝑉𝑠𝑠

8. So, we have a collector current of
𝐼𝐼𝐶𝐶 =
𝑉𝑉𝐶𝐶𝐶𝐶 − 𝑉𝑉𝐶𝐶
𝑅𝑅𝐶𝐶
=
(12 − 6) 𝑉𝑉
500 Ω
= 12 𝑚𝑚𝑚𝑚
We can safely assume 𝐼𝐼𝐶𝐶 ≅ 𝐼𝐼𝐸𝐸, therefore 𝐼𝐼𝐸𝐸 = 12 𝑚𝑚𝑚𝑚
𝑅𝑅𝐸𝐸 = 𝑅𝑅𝐸𝐸1
+ 𝑅𝑅𝐸𝐸2
=
𝑉𝑉𝐸𝐸
𝐼𝐼𝐸𝐸
=
1.2
12 × 10−3
= 100 Ω
Under these conditions,
𝑟𝑟𝑒𝑒 =
𝑉𝑉𝑡𝑡
𝐼𝐼𝐸𝐸
=
26 × 10−3
𝑉𝑉
12 × 10−3 𝐴𝐴
= 2.1667 Ω
Finally from gain expression we can evaluate 𝑅𝑅𝐸𝐸1
as,
�𝐴𝐴𝑣𝑣 𝑁𝑁𝑁𝑁
� = 46.5 =
𝑅𝑅𝐶𝐶
𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒
46.5 =
500
𝑅𝑅𝐸𝐸1
+ 2.1667
𝑅𝑅𝐸𝐸1
= 8.58 Ω
And so,
𝑅𝑅𝐸𝐸2
= 91.42 Ω
Now, for finding voltage divider resistances 𝑅𝑅𝑎𝑎 and 𝑅𝑅𝑏𝑏 , we need that the current flowing through the
potential divider circuit has to be large as compared to the actual base current, 𝐼𝐼𝐵𝐵, so assume a value of
atleast 10 times 𝐼𝐼𝐵𝐵 flowing through the resistor 𝑅𝑅𝑏𝑏.
Approximately the base current is at the most,
𝐼𝐼𝐵𝐵 =
𝐼𝐼𝐶𝐶
𝛽𝛽
=
12 𝑚𝑚𝑚𝑚
100
= 120𝜇𝜇𝜇𝜇
∴ 𝑅𝑅𝑏𝑏 ≤
𝑉𝑉𝐸𝐸 + 𝑉𝑉𝐵𝐵𝐵𝐵
10 × 𝐼𝐼𝐵𝐵
=
(1.2 + 0.7) 𝑉𝑉
1200 × 10−6 𝐴𝐴
= 1.67 𝑘𝑘Ω
Also from the voltage divider constraint,
𝑅𝑅𝑏𝑏
𝑅𝑅𝑏𝑏 + 𝑅𝑅𝑎𝑎
× 𝑉𝑉𝐶𝐶𝐶𝐶 = 𝑉𝑉𝐸𝐸 + 𝑉𝑉𝐵𝐵𝐵𝐵
𝑅𝑅𝑏𝑏
𝑅𝑅𝑏𝑏 + 𝑅𝑅𝑎𝑎
× 12 = 1.9
𝑅𝑅𝑎𝑎 ≈ 5.3 𝑅𝑅𝑏𝑏

9. So, input impedance turns out to be,
𝑍𝑍𝑖𝑖 = 𝑅𝑅𝑎𝑎 ∥ 𝑅𝑅𝑏𝑏 ∥ 𝛽𝛽(𝑅𝑅𝐸𝐸1
+ 𝑟𝑟𝑒𝑒)
This evaluates to (after taking into account the fact that standard values have to be used),
𝑍𝑍𝑖𝑖 = (10||2||1) 𝑘𝑘Ω = 653Ω
Emitter bypass capacitor for lower frequency response of 20Hz at -3 dB,
𝐶𝐶𝐸𝐸 =
1
2𝜋𝜋𝑅𝑅𝑒𝑒𝑒𝑒 𝑓𝑓𝐿𝐿
In this case 𝑅𝑅𝑒𝑒𝑒𝑒 = 𝑅𝑅𝐸𝐸2
∥ (𝑟𝑟𝑒𝑒 + 𝑅𝑅𝐸𝐸1
+
𝑅𝑅𝑠𝑠∥𝑅𝑅𝑎𝑎 ∥𝑅𝑅𝑏𝑏
𝛽𝛽
) ≈ 14.5833 Ω,
∴ 𝐶𝐶𝑐𝑐 ≈ 720 𝜇𝜇𝜇𝜇
Upon use of standard Components
Component Theoretical Desired Value Nearest standard value
𝑅𝑅𝐶𝐶 697 Ω 500 Ω
𝑅𝑅𝐸𝐸1 8.58 Ω 8.2 Ω
𝑅𝑅𝐸𝐸2 91.42 Ω 100 Ω
𝑅𝑅𝑏𝑏 1.67 𝑘𝑘Ω 2 𝑘𝑘Ω
𝑅𝑅𝑎𝑎 𝑅𝑅𝑎𝑎 ≈ 5.3 𝑅𝑅𝑏𝑏 = 8.35 𝑘𝑘Ω 10 kΩ
𝐶𝐶𝑐𝑐 720 𝜇𝜇𝜇𝜇 1 𝑚𝑚𝑚𝑚

10. Coupling Capacitors:
1. Coupling Capacitor between signal source and first stage amplifier:
The resistance as seen by this coupling capacitor,
𝑅𝑅𝑒𝑒𝑒𝑒 = 𝑅𝑅𝑠𝑠 + 𝑍𝑍𝑖𝑖1
= 703 Ω
So, for lower frequency response at 20Hz (-3 dB)
𝐶𝐶𝑐𝑐 =
1
2𝜋𝜋𝑅𝑅𝑒𝑒𝑒𝑒 𝑓𝑓𝐿𝐿
= 11.32 𝜇𝜇𝜇𝜇
2. Coupling Capacitor between first and second stage amplifier:
The resistance as seen by this coupling capacitor,
𝑅𝑅𝑒𝑒𝑒𝑒 = 𝑍𝑍𝑜𝑜1
+ 𝑍𝑍𝑖𝑖2
= 1197 Ω
So, for lower frequency response at 20Hz (-3 dB)
𝐶𝐶𝑐𝑐 =
1
2𝜋𝜋𝑅𝑅𝑒𝑒𝑒𝑒 𝑓𝑓𝐿𝐿
= 6.67 𝜇𝜇𝜇𝜇
But this capacitor should have at least 10 times more capacitance so as to maintain good interaction
between first and second stage of amplifier even at lower frequencies.
∴ 𝐶𝐶𝑐𝑐 = 66.7𝜇𝜇𝜇𝜇
3. Coupling Capacitor between second stage amplifier and load:
The resistance as seen by this coupling capacitor,
𝑅𝑅𝑒𝑒𝑒𝑒 = 𝑅𝑅𝐿𝐿 + 𝑍𝑍𝑜𝑜2
= 2 𝑘𝑘Ω
So, for lower frequency response at 20Hz (-3 dB)
𝐶𝐶𝑐𝑐 =
1
2𝜋𝜋𝑅𝑅𝑒𝑒𝑒𝑒 𝑓𝑓𝐿𝐿
= 4 𝜇𝜇𝜇𝜇
50Ω
Rb
Cc
653Ω
Zi1
500Ω
Zo1
Cc
697Ω
Zi2
1kΩ
Zo2
Cc
1kΩ
RL

11. High Frequency Cutoff
The amplifier has higher cutoff frequency in the range of MHz. But we need an upper cutoff near 20kHz.
So we apply a RC lowpass filter at the output.
The resistance seen by this capacitor,
𝑅𝑅𝑒𝑒𝑒𝑒 = 𝑅𝑅𝐿𝐿 ∥ 𝑍𝑍𝑜𝑜2
= 500 Ω
So, for higher frequency response at 20kHz (-3 dB)
𝐶𝐶 =
1
2𝜋𝜋𝑅𝑅𝑒𝑒𝑒𝑒 𝑓𝑓𝐻𝐻
= 16 𝑛𝑛𝑛𝑛
So, we choose a capacitor of capacitance 𝐶𝐶 = 10 𝑛𝑛𝑛𝑛
1kΩ
Zo2
C
1kΩ
RL

12. Fig
ur
e:
Co
m
pl
et
e
β-
m
1mVpk
1kHz
0°
Vin
Vcc
50Ω
Rs
2kΩ
R1
10kΩ
R2
1kΩ
Rc
200Ω
Re
1kΩ
Rl
100µF
C1
1mF
Ce
6.5Ω
Re
2kΩ
R1
10kΩ
R2
500Ω
Rc
100Ω
Re
100µF
C2
1mF
Ce
2N2222
Q1
2N2222
Q1
8.2Ω
Re
100µF
C2
10nF
Ce

13. Observations:
Keeping the input amplitude (𝑉𝑉𝑠𝑠) small enough to get undistorted output amplitude (𝑉𝑉𝑜𝑜 ) up to ± 1 V, i.e.
operating in small signal mode.
Sr. No. Frequency 𝑨𝑨𝒗𝒗 𝟏𝟏 𝑨𝑨𝒗𝒗𝒔𝒔
1. 1 Hz 1.940338 5.648164
2. 2 Hz 3.852225 22.23175
3. 4 Hz 7.118051 79.7995
4. 8 Hz 12.465 253.5564
5. 10 Hz 14.5787 350.3958
6. 20 Hz 20.32947 695.9518
7. 40 Hz 23.49171 933.8613
8. 80 Hz 24.59059 1023.351
9. 100 Hz 24.7394 1035.71
10. 200 Hz 24.93458 1051.992
11. 400 Hz 24.98449 1056.122
12. 800 Hz 24.99721 1056.983
13. 1 kHz 24.99887 1056.961
14. 2 kHz 25.00171 1055.901
15. 4 kHz 25.0055 1051.1
16. 8 kHz 25.01816 1032.469
17. 10 kHz 25.02737 1018.579
18. 20 kHz 25.08669 923.7349
19. 40 kHz 25.19986 707.0369
20. 80 kHz 25.29784 434.4106
21. 100 kHz 25.3163 356.3207
22. 1 MHz 25.02633 37.32845
 Midband Amplification: 1018.579
o First Stage: 25.02737
o Second stage: 40.69860
 Cutoff frequency
o Lower: 20Hz
o Higher: 40kHz

15. Result:
The two stage CE amplifier was successfully built and demonstrated to possess the given amplification
and bandwidth.
Comments:
A recommended output swing of ±1 𝑉𝑉 is needed. Since our amplifier has a source to output gain of
1000, the signal source swing should be ±1 𝑚𝑚𝑚𝑚. But the function generator available could not generate
signal of such low swing. So, we were forced to use a voltage divider at the input.
Since the signal source was believed to have a resistance of 50 Ω, we must design the voltage divider in
such a way, so that source resistance still appears to be 50 Ω to the amplifier.
We choose
𝑅𝑅𝑏𝑏 = 50 Ω
Now, voltage divider constraint gives
𝑅𝑅𝑏𝑏
𝑅𝑅𝑎𝑎 + 𝑅𝑅𝑠𝑠𝑠𝑠 𝑠𝑠 + 𝑅𝑅𝑏𝑏
× 𝑉𝑉𝑠𝑠 = 1 𝑚𝑚𝑚𝑚
Choose 𝑅𝑅𝑎𝑎 = 4.7 𝑘𝑘Ω, this gives,
50
50 + 50 + 4700
× 𝑉𝑉𝑠𝑠 = 1 𝑚𝑚𝑚𝑚
𝑉𝑉𝑠𝑠 = 96 𝑚𝑚𝑚𝑚
The available function generator can easily give signals with a swing of ±96 𝑚𝑚𝑚𝑚. The source impedance
as seen by the amplifier is then
𝑅𝑅𝑠𝑠 = 𝑅𝑅𝑏𝑏 ∥ �𝑅𝑅𝑎𝑎 + 𝑅𝑅𝑠𝑠𝑠𝑠 𝑠𝑠 � = 49.5 Ω
as required.
96mVpk
1kHz
0°
Vs
50Ω
Rs
50Ω
Rb
4.7kΩ
Ra