This document summarizes the thesis work of Mehul C. Raval from IIT Bombay on characterization of nickel silicide formation and optimization of background plating for silicon solar cells based on Ni-Cu-Sn metallization. The work included studying nickel silicide formation from nickel seed layers, characterizing background plating losses using a 3-diode model, minimizing background plating through N2O plasma treatment, and optimizing annealing temperature. Key results were improved fill factor of 77.5% after post-treatment plasma and 16% efficiency for cells annealed at 375°C. The work also demonstrated promising results for low-temperature processed cells with rear-side passivation.

1. CHARACTERIZATION OF NICKEL SILICIDE
FORMATION
AND BACKGROUND PLATING WITH
ASSOCIATED
PROCESS OPTIMIZATION FOR SILICON
SOLAR CELLS
BASED ON NI-CU-SN METALLIZATION
MEHUL C. RAVAL (10417605),
DEPARTMENT OF ENERGY SCIENCE AND
ENGINEERING, IITB.
Guides- Prof. Chetan Solanki & Prof. Sagar
Mitra

2. Outline
 Motivation for Ni-Cu based metallization.
 Nickel silicide formation studies for the seed layer.
 Characterization of background plating.
 Minimization of background plating by N2O plasma
treatment.
 Optimization of annealing temperature for Ni-Cu-Sn
based metallization.
 Low-temperature process for solar cells with SiNx:H
based rear-side passivation.
 Conclusions.
2

3. Motivation of thesis work
3
 Study impact of background plating on solar cell:
- Detailed cell-level characterization for the same not
reported till date.
 Optimization of nickel seed layer parameters:
- Bath parameters and interface conditions influence
silicidation and adhesion and hence it should be
studied in more detail.
 Development of complete solar cell with
improved process parameters:
-How can background plating be minimized?
-What are the optimum annealing conditions for
silicide formation?

4. Silicide formation studies for nickel
seed layer
4
Figure Silicide morphology for Ni deposition from alkaline bath with temperature=
90-95°C and plating interval of 120 s for annealing at a) 375°C for 30s and b) 425°C
for 30 s.
 Annealing at 375°C results in a fairly homogeneous silicide interface.
 While annealing at 425°C leads to non-uniform silicide growth and
increased
- surface roughness.

5. Characterization of nickel silicide
formation
 Silicide coverage is not complete for the 100 nm Ni seed layer
annealed at 550°C for 30 s.
 Silicide thickness of 50 nm as against expected thickness of 200
5
Figure. (a) Silicide morphology after etching the unreacted Ni for a 100 nm Ni seed
layer annealed at 550°C for 30 s, (b) Corresponding Ni silicide thickness for annealing
at 550°C for 90 s.
a)
b)

6. Characterization of nickel silicide
phase evolution6
Figure. Proportion of various silicide phases
for 100 nm Ni seed layer annealed at 550°C for
30 s, 60 s and 90 s.
Figure. Proportion of various silicide phases
for annealing a 100 nm Ni seed layer in the
range of 350-550°C for 60 s.
 Ni phosphides (NiP, Ni2P, Ni3P) also present as the seed
layer annealed above 400°C.
 Presence of metal-rich silicide phases is observed for
annealing temperatures down to 350°C.

7. Characterization of background
plating losses with complete solar
cells
Figure. Local ideality factor variation for
presentative cells and reference curve for
creen-printed silver based metallization.
7
Figure. Equivalent circuit of the 3-diode mod
with RLR. Rs, RP, Jph and the diodes D1 and D
defined as in the regular 2-diode model, whe
diode D3 is connected via the additional seri
resistance Rrec.*
*- Keith Reid McIntosh, Lumps, Humps and Bumps: Three Detrimental Effects in
the Current- Voltage Curve of Silicon Solar Cells, Ph. D Thesis, Centre for
Photovoltaic Engineering, University of New South Wales, 2001.
Resistance Limited Recombina
Fitted m(V) curve
based on 2-diode
model has no
physical meaning.

8. Characterization of background
plating losses with complete solar
cells8
igure. Dark I-V and m(V) curves of cell 1 in
evious slide with its corresponding 3-diode
fits.
 2-diode fitting software developed by
Stephan Suckow, IHT extended to 3-
diode model.
 Software takes into account I-V data
& m(V) curve for fitting.
 Relative residuals mode used, so
errors are not normally distributed &
hence confidence levels could not be
estimated.
 Rise in the m(V) curve between 0.2 V
to 0.3 V due to flattening of J3 current.
 J2 becomes significant after 0.45 V &
hence m(V) value decreases.
 Rise & fall leads to formation of 2nd
hump.

9. Minimization of background plating
by N2O plasma treatment
Figure. Background plating area coverage analysis for
different treatment cases. (□) corresponds to the
measurement data points and (■) to the mean value.
The lower, middle and upper limits of the boxes
correspond to the 25th percentile, median and 75th
9
 N2O plasma treatment carried
out
before or after the bilayer ARC
deposition.
 Background plating area
coverage decreases from 2.25%
to 1.25% after N2O plasma
treatment.
 The area coverage is normally
distributed for the post-treatment
case.

10. Minimization of background plating
by N2O plasma treatment.
Table. Average electrical parameters of 6 solar cells with bilayer ARC
and different N2O plasma treatment measured under STC. The quoted
Jsc is the active area Jsc.
10
Treatment VOC
(mV)
JSC
(mA/cm2)
FF
(%)
Ƞ
(%)
RS
(Ωcm2)
RSH
(Ωcm2)
None 608.7 ± 2.6 37.5 ± 0.2 73.5 ± 0.7 16.8 ± 0.3 0.58 ± 0.03 > 40,00
Pre-treated 606.6 ± 4.0 37.7 ± 0.3 75.0 ± 1.2 17.1 ± 0.2 0.55 ± 0.06 > 30,000
Post-
treated
611.7 ± 0.8 37.6 ± 0.4 77.5 ± 0.4 17.8 ± 0.2 0.52 ± 0.06 > 50,000
Treatment FF0
(%)
pFF
(%)
FF
(%)
Absolute ΔFF
(%) due to RS
Absolute ΔFF (%)
due to
recombination
None 82.9 ± 0.1 75.5 ± 0.3 73.5 ± 0.7 -2.0 ± 0.32 -7.4 ± 0.30
Pre-treated 82.8 ± 0.1 78.0 ± 0.2 75.0 ± 1.2 -3.0 ± 1.30 -4.8 ± 0.17
Post- 83.0 ± 0.0 80.4 ± 0.3 77.5 ± 0.4 -2.9 ± 0.70 -2.6 ± 0.33

11. Minimization of background plating
by N2O plasma treatment
 N2O plasma pre-treatment results in growth of a
thin silicon oxy-nitride film (SiOxNy) on silicon with
an improved thermal stability compared to the
regular SiNx:H layer based passivation.*
 Inferred that the presence of plasma grown
SiOxNy reduces the exposure of silicon after the
1% HF dip in pin-hole regions and areas with
reduced SiNx:H coverage.
*- Sandeep S. S., Anil Kottantharayil, Plasma Grown Oxy-nitride Films
for Silicon Surface Passivation, IEEE Electron Device Lett. 34(7)(2013)
918 – 920.
11

12. Minimization of background plating
by N2O plasma treatment
 Impact of N2O plasma post-treatment on
SiNx:H and emitter passivation:
Figure. Si2p XPS spectrum for SiNx:H deposited on
polished p-type
Si(100) wafer with and without N2O plasma post-treatment
12
Peak at 102.3 eV
corresponds to SiOxNy
Peak at 100.5 eV indicate
presence of Si-O bonds

13. Minimization of background plating
by N2O plasma treatment
Figure. O1s XPS spectrum of SiNx:H
deposited on polished p-type Si(100) wafer
with and without N2O plasma post-treatment.
13
Increase in oxygen
content
 Change in surface checked by etc
the film in 1% HF.
 6.1 nm etched for untreated film,
while only 3.6 nm is etched for the
post-treated case.

14. Minimization of background plating
by N2O plasma treatment
Figure. Local ideality factor variation from dark I-V measurements of
representative solar cells with different treatments.
14
Shift to lower voltage by around 40 mV
2nd hump not presen

15. Minimization of background plating
by N2O plasma treatment
Table. Fit parameters of 2nd and 3rd diode for representative solar
cells obtained according to the 3-diode model with RLR. n1 was fixed
at 1 and Rs did not show any significant difference.
15
J01
(A/cm2)
n2 J02
(A/cm2)
n3 J03
(A/cm2)
Rrec
(Ωcm2)
FF
(%)
RMSE
(%)
None 5.9 × 10-
13
1.75 1.67 × 10-8 1.55 1.18 × 10-7 76.6 73.2 5.7
None 3.3 × 10-
12
1.74 1.14 × 10-8 1.57 1.21 × 10-7 89.0 74.3 5.0
None 7.7 × 10-
13
2.0 5.68 × 10-8 1.75 2.81 × 10-7 106 73.1 1.3
Pre-
treated
8.2 × 10-
13
1.93 2.97 × 10-8 1.83 1.45 × 10-7 216 75.5 2.3
Pre-
treated
6.4 × 10-
13
1.87 3.7 × 10-8 1.58 1.36 × 10-7 193 75.9 7.0
 Two-fold increase in Rrec after pre-treatment improves the FF.
 Close to zero value of Rrec after post-treatment implies absence
of RLR.

16. Optimization of annealing
temperature
Table. Average electrical parameters of 5 solar cells with different
annealing conditions measured under standard test conditions. The
error range represents the standard deviation from the average
values.
16
Annealing
temperature
(°C)
VOC (mV) JSC
(mA/cm2)
FF (%) ƞ (%) RS (Ωcm2)
350 608.6 ± 3.1 32.5 ± 0.85 79.0 ± 0.6 15.6 ± 0.6 0.46 ± 0.06
375 609.4 ± 1.4 33.1 ± 0.4 79.3 ± 0.3 16.0 ± 0.2 0.49 ± 0.10
400 610.1 ± 3.5 32.7 ± 0.4 78.6 ± 0.2 15.8 ± 0.1 0.48 ± 0.20
425 607.8 ± 5.0 31.5 ± 0.9 77.5 ± 1.4 14.7 ± 0.9 0.41 ± 0.25
 Annealing duration was 30 s.
 Best FF of greater than 79% obtained for annealing the range of 350-375°C.
 Decrease of up to 1.5% when the annealing temperature is increased to 425°C.

17. Optimization of annealing
temperature
Table. Average fill-factor parameters based on illuminated I-V data for
solar cells annealed at different temperatures. Each batch consists of
5 cells.
17
Annealing
temperature
(°C)
FF0 (%) pFF (%)
from Suns-
VOC
Measured
FF (%)
Absolute ∆FF (%)
due to RS
Absolute
∆FF (%) due to
recombination
350 83.0 ± 0.11 81.3 ± 0.32 79.0 ± 0.6 -2.3 ± 0.35 -1.7 ± 0.21
375 83.0 ± 0.04 81.1 ± 0.13 79.3 ± 0.3 -1.8 ± 0.29 -1.9 ± 0.11
400 83.0 ± 0.05 80.4 ± 0.39 78.6 ± 0.2 -1.8 ± 0.35 -2.6 ± 0.34
425 82.8 ± 0.20 79.5 ± 1.8 77.5 ± 1.4 -2.0 ± 0.46 -3.3 ± 1.62
 Increased FF loss attributed to increasing recombination losses for higher
annealing
temperature.
 J2 current component found to be increasing for higher annealing temperature.


18. Low-temperature processing with
rear-side passivation18
Evaporated Al
Contact
ARC
p-type Substrate
SiNx passivation
stack
Ni-Cu Contacts
Laser-
fired
contacts
Figure. Cell-structure with rear-side
passivation
and Ni-Cu-Sn based front-side
metallization.
- Beneficial impact of N2O plasma
treatment can be retained on both sides
due to elimination of firing step.
-Parasitic shunting reported rear-side
SiNx:H passivation with LFC.*
- High value of ideality factor at MPP
and OC can be observed from m(V)
plot.
Illuminated
I-V curve
m(V) curve from dark I-V
*- S. Gatz, et.al, Sol. Energy Mat. Sol. Cells, 96, pp 180-185, 2012.

19. Conclusions
19
 Nickel seed layer deposition characterized with ρc of
around 6 mΩ-cm2 obtained for alkaline bath.
 Presence of SiO2 along with high resistivity nickel
silicide phases confirmed from surface analysis.
 Growth of silicide formation retarded till 550°C due to
presence of impurities and (111) orientation of exposed
Si surface.
 Presence of metal-rich nickel silicide phases detected
for annealing temperatures down to 350°C.
 Background plating is modeled well by adding a 3rd
diode connected via an additional series resistance to
the standard

20. Conclusions
20
 N2O plasma pre-treatment improves the average FF by
1.5% absolute by shifting the 2nd hump in m(V) towards
lower voltage.
 N2O plasma post-treatment eliminates the impact of RLR &
improves the average FF to 77.5%.
 Optimization of annealing temperature to 375°C resulted in
average FF and η of 79.3% and 16.0%, respectively.
 Promising result of > 14% obtained for low-temperature
processed solar cells with SiNx:H based passivation on
both sides of solar cell.

21. Publications
Journal Publications:
1) Mehul C. Raval, Sandeep S. Saseendran, Stephan Suckow, S. Saravanan, Chetan S. Solanki
and Anil Kottantharayil, “N2O plasma treatment for minimization of background plating in silicon
solar cells with Ni-Cu front side metallization”, Solar Energy Materials and Solar Cells, 144
(2016), pp 671-677, Elsevier Publications.
2) Mehul C. Raval, Amruta Joshi, Sandeep S. Saseendran, Stephan Suckow, S. Saravanan, Chetan
S. Solanki and Anil Kottantharayil, “Study of nickel silicide formation and associated fill-factor loss
analysis for silicon solar cells with plated Ni-Cu based metallization”, IEEE Journal of
Photovoltaics, 5(6), 2015, pp. 1554-1562.
3) Mehul C. Raval and Chetan Singh Solanki, “Characterization of electroless nickel as a seed layer
for silicon solar cell metallization”, Bull. Mater. Sci., vol. 38, no. 10, pp. 197-201, 2015.
4) Sandeep S Saseendran, Mehul C. Raval, S Saravanan and Anil Kottantharayil, “Impact of post
deposition plasma treatment on surface passivation quality of silicon nitride films”, IEEE Journal
of Photovoltaics, 6(1), 2016, pp. 74-78.
5) Sandeep S Saseendran, S Saravanan, Mehul C. Raval and Anil Kottantharayil, “Impact of
interstitial oxygen trapped in silicon during plasma growth of silicon oxy-nitride films for silicon
solar cell passivation”, J. Appl. Phys. 119, 095307 (2016), DOI: 10.1063/1.4943177. 5)
6) Mehul C. Raval and Chetan Singh Solanki, “Review of Ni-Cu based front side metallization for c-
Si solar cells”, J. Sol. Energy, vol. 2013, Article ID 183812, 2013.
21

22. Publications
Patents:
1) Post-treatment of silicon nitride used in a solar cell (2015), Sandeep S. S., Mehul Raval,
Anil Kottantharayil, Indian patent filed, Application number 636/MUM/2015.
Conference Publications:
1) Mehul C. Raval, Sandeep S. Saseendran, Som Mondal, Balraj Arunachalam, Sandeep
Kumbhar, Nilesh Kusher, Aldrin Antony, Chetan S. Solanki, Anil Kottantharayil, “Low
temperature fabrication process for silicon solar cells based on front-side Ni-Cu
metallization and rear-side silicon-nitride based passivation”, in Proc. 18th IWPSD,
Bangalore, 2015.
2) Mehul C. Raval, Stephan Suckow and Chetan Singh Solanki, “Analysis of background
plating for Ni-Cu based metallization by observing local ideality factor variation,” in Proc.
29th EU PVSEC, 2014, pp. 1143-1146.
3) Mehul C. Raval, Amruta Joshi, and Chetan Singh Solanki, “Analyzing Impact of
Background Plating from Alkaline Ni bath for Ni-Cu metallization,” in Proc. 39th IEEE
PVSC, 2013, pp. 2254-2256.
4) Mehul C. Raval, Amruta Joshi and Chetan Singh Solanki, “Surface and Lifetime Studies
for Unintended Deposition on Solar Cells during Ni-Cu Plating,” in Proc. 27th EU PVSEC,
2012, pp. 1234-1237.
5) Mehul C. Raval and Chetan Singh Solanki, "Characterization of unintended deposition on
22