1. IEEE Wireless Communications And Networking Conference (WCNC), 13 - 17 March 2005, Vol. 1, pp. 596 – 600,
2005.
0-7803-8966-2/05/$20.00 (C) 2005 IEEE 596
Abstract— This paper compares and contrasts the
performance of a Root Raised Cosine matched filter
implemented using hybrid-logarithmic arithmetic with that of
standard binary and floating point implementations. Hybrid-
logarithmic arithmetic is advantageous for FIR digital filters
since it removes the necessity for the use of high speed array
multipliers. These can be replaced by simple look up table
structures for the conversion to and from the logarithmic
domain. Matlab simulations of the hybrid logarithmic
structure have shown that its performance is superior to that
of recently published fixed point solutions, while offering a
significantly reduced complexity when compared to floating
point equivalents proposed for the WCDMA downlink in
receiver applications. The use of hybrid logarithmic
arithmetic also has the potential to reduce the power
consumption, latency and hardware complexity for mobile
handset applications.
I. INTRODUCTION
he efficient implementation of a matched Root Raised
Cosine (RRC) filter for 3G mobile communication
applications should ideally combine low cost, low power
and ease of integration [1]. The use of a digital FIR
structure to implement the RRC filter will usually have an
arithmetic requirement involving high speed computational
blocks with power hungry array multipliers. In [2], the
sign-logarithm number system (SLNS) was proposed to
replace multipliers with addition so as to decrease the
latency and power consumption involved with the multiply
and accumulate process. Reduction in the hardware
requirements for the prototype RRC filter would allow
greater integration for the WCDMA downlink receiver
with more compact, cheaper devices with reduced power
consumption. This paper presents an evaluation of the
performance of a RRC matched filter using hybrid-
logarithmic arithmetic when implemented as an integral
part of the UMTS downlink receiver.
The RRC matched filters for the UMTS downlink receiver
were designed to conform to the 3GPP technical
specifications [3], where the filter coefficient values were
generated using non-canonical FIR techniques [1] to yield
the lowest cost digital hardware implementation. The
RRC filter was modeled with Matlab for three cases where
the filter coefficients were represented as floating point
binary, fixed point binary, and fixed-point logarithmic
values when simulated as part of the UMTS downlink
receiver chain [4]. The evaluation for the three cases were
presented in terms of the signal power spectral density
(PSD) derived from the cross correlation of the received
data. The performance is also assessed in terms of the
overall system BER for a fixed physical data channel of
64kbps when the multiplierless RRC matched filter is
integrated as part of a low complexity rake receiver. The
use of hybrid-logarithmic arithmetic is shown to produce a
lower cost filter with improved performance compared to
fixed point two’s complement arithmetic.
II. ROOT-RAISED COSINE MATCHED FILTERS
The Root Raised Cosine matched filter is an area of
great interest and development in digital communications
[5]. The filter alters the transmitted pulse spectra such that
the intersymbol interference (ISI) is reduced when passed
through a low pass frequency dispersive channel. The
filters other purpose is to limit the bandwidth required for
transmission and to ensure the Co-Channel interference is
low when passed through a sufficiently linear power
amplifier.
The Root Raised Cosine Filter can be generically
defined by its frequency response H(f) [6]. If t is the time
variable, T the length of the baseband chip and α the excess
bandwidth where α = 0.22 for the UMTS, then,









⋅
+
>
⋅
+
≤≤
⋅
−












⋅
−
−⋅
⋅
⋅
⋅
−
≤≤
=
T2
1
f0
T2
1
f
T2
1
T2
1
f
2
T
cos
T2
1
f01
)f(H
α
ααα
α
π
α
(1)
Applying the inverse Fourier transform yields the Root-
Raised Cosine impulse response,
















⋅⋅−⋅





⋅






⋅⋅⋅





⋅
=
2
2
2
T
t
41
T
t
T
t
cos
T
t
sin
)t(h
απ
αππ
(2)
THE USE OF HYBRID LOGARITHMIC ARITHMETIC FOR ROOT
RAISED COSINE MATCHED FILTERS IN WCDMA DOWNLINK
RECEIVERS.
C. Litchfield, P. Lee, R. Langley, J. Batchelor.
T

2. IEEE Wireless Communications And Networking Conference (WCNC), 13 - 17 March 2005, Vol. 1, pp. 596 – 600,
2005.
0-7803-8966-2/05/$20.00 (C) 2005 IEEE 597
In the downlink case shown in Fig. 1 [4], the scrambled
and spreaded chips from the user physical channels are
multiplexed onto in phase (I) and quadrature components
(Q). The transmitter filter block is therefore a pair of
parallel RRC filters, one for the I channel, and one for the
Q channel. After modulation onto orthogonal carriers, the
QPSK mobile signal is transmitted through a frequency
selective multipath channel, where noise with Gaussian
PDF and double sided PSD is added at the receiver prior to
demodulation. After demodulation and anti-alias filtering,
the receiver base-band pulses are sampled and applied, as
in the transmitter case, to a pair of RRC filters prior to
diversity combining. The UMTS downlink mobile
receiver consists of several physical layer receiver
components [4]. One such component is a decentralized
sub-optimum Rake Receiver [7] for multipath combining
and multiple access interference (MAI) suppression when
descrambing and despreading of the physical code
channels.
The receiver RRC structure was implemented as a 129
tap symmetrical FIR filter with wordlength outlined in
Table 1. The technical specifications were chosen
according to the 3GPP [3] as being the minimum
requirement for fixed point coefficient and data resolution.
The values shown in Table 1 indicate that coefficient and
data sample contain 1 integer bit. The number of taps was
chosen to fulfill the spectral specifications, and the
coefficient values were generated via sampling the RRC
impulse response (2) at a factor eight times greater than the
Nyquist rate. The data samples were oversampled by a
factor 8, which thus yielded a total data rate of 30.72×106
samples per second input to each filter. Hence the
maximum multiply-accumulate period in this case is given
as 2.52×10-10
s.
The Correlation property of RRC matched filter
receivers is analogous to the FIR structure (Fig. 2). The
output y[n] is calculated as the accumulation of inner
products between the predetermined set of coefficients ψk,
and integer data χ(n), where:
∑
−
=
−⋅=
1N
0k
k ]kn[]n[y χψ (3)
N = 129,
s
s
f
i
nT = , i = n ∀Ζ , n ≥ 0, and fs = 30.72MHz.
Fig. 1: Downlink WCDMA Receiver chain.
TABLE 1. Sample and Coefficient Resolution.
Format Fractional
Range
Integer
Equivalent
Samples 1<f ≤2-11
-212
< I ≤ 212
-1
Coefficients 1<f ≤2-9
-210
< I ≤ 210
-1
Application of such a structure would require high speed
multiplication which is costly in terms of hardware
resources, due to this process being executed using large
VLSI array multipliers [8]. For lower precision
applications such as required for the RRC filter, it is
proposed that implementing a multiplierless structure
based on logarithmic arithmetic could be advantageous in
terms of hardware complexity, accuracy, latency, and
power consumption.
III. HYBRID LOGARITHMIC ARITHMETIC FOR
DIGITAL RRC FILTERS
The SLNS [2] was introduced to overcome the
computational difficulties of multiplication in DSP
arithmetic. The Sign/Logarithm number representation
consists of a sign flag bit immediately followed by the
logarithm of the absolute number (since the logarithm of a
negative number is imaginary).
This system can be extended to consider a zero flag bit,
due to the log(0) = −∞. Consider a number χ with
arbitrary base λ, χ > 0, where Lx
λχ = ,
and )(log
2
1
L 2
x χλ= . To avoid the logarithm of zero,
let ))((log
2
1
L 2
x χχλ ∂+= , where )( χ∂ = 1 for χ = 0, and
)( χ∂ = 0, for all other real positive values of χ. Hence any
real number can be realized by:
( ) ( )






∂+⋅
−
⋅∂−⋅−=
))((log
2
1
)(1
2
)(11
χχ
χµ λ
λχχ (4)
where .0,0)(0,1)( and <=≥= χχµχχµ
A conventional approach to logarithms would be for
binary numbers, i.e. base 2 number systems. Using λ = 2
as the radix for the LNS, consider the arbitrary number χ
represented by the triple {Z(χ), S(χ), and L(χ) }. Z(χ), S(χ),
and L(χ) represent the zero flag bit, sign flag bit, and the
absolute base 2 logarithm respectively.

3. IEEE Wireless Communications And Networking Conference (WCNC), 13 - 17 March 2005, Vol. 1, pp. 596 – 600,
2005.
0-7803-8966-2/05/$20.00 (C) 2005 IEEE 598
Fig. 2: Transversal Tap structure of the RRC matched filter.
Hence, based on the provision that )()( χχΖ ∂= and
)(1)(S χµχ −= , then
( ))(log)(L 2 χΖχχ += . (5)
Substituting λ = 2 and equating for L(χ) gives the sign-
logarithm number system (SLNS) [3]:
( ) .2))(1(1 )(L)(S χχ
χΖχ ⋅−⋅−= (6)
Multiplication becomes addition in the SLNS domain.
If c = a × b, then cL
cc 2SZC ⋅⋅= , where:
bac LLL += ,
( ))a(ZalogL 2a += ( ))(log2 bZbLb += ,
)b(Z|)a(Z))b(Z1())a(Z1(Zc =−•−= ,
)b(S)a(SSc ⊕= .
The ⊕ operator is the logical XOR. Addition is more
complicated to perform with logarithmic arithmetic, where
if c=a+b, then ( ).21logLL ab LL
2ac
−
++=
Hybrid Linear-Logarithmic arithmetic can be used to
overcome difficulties of linear addition with logarithms
[9]. Implementing such a system requires that the input
samples χ[n] be converted to SLNS format (Linear to
Logarithmic conversion) via a look up table (LUT). The
predetermined set of coefficients ψk are stored in memory
also as SLNS values. After logarithmic addition, the
resultant must be exponentially converted (Logarithmic to
Linear conversion) via a LUT into a 2’s complement
binary number prior to accumulation. Adapting (3) for
hybrid logarithmic values, where
])kn[(L)(LL kk −+= χψ , the output y[n] is given by:
∑
−
=
⋅−⋅=
1N
0k
LS
k .2)1(Z]n[y kk (7)
where ]))kn[(Z1())(Z1(Z kk −−•−= χψ and
])kn[(S)(SS kk −⊕= χψ .
This yields a direct FIR structure (Fig. 3), and like the
standard implementation in Fig. 2, consists of 129 taps
with coefficient resolution of 9 bits, and data sample
resolution of 11 bits. No integer bits were required for the
coefficient values or the output of the Lin/Log conversion
due to the logarithm of numbers < 2 being fractional
quantities.
IV. FILTER SIMULATION
Matlab was used to conduct an evaluation of the RRC
Matched filter performance in a downlink simulation
model based on Fig. 1 [4]. The simulation was run for
three different cases where the RRC filter was
implemented with hybrid logarithmic arithmetic, standard
fixed point binary and floating point arithmetic. The
transmitted complex antipodal pulse shaped RRC chips
after demodulation were applied to the input of the RRC
matched filter for the aforementioned structural cases. The
PSD was then calculated via the Fourier transform of the
output cross-correlation signal from the receiver matched
filter. The results shown in Fig. 4 and Fig.5 clearly present
that for fixed point hybrid logarithmic arithmetic and fixed
point binary arithmetic, the matched filter response is
superior for the logarithmic case when compared to the
ideal floating point implementation. This is due to the
dynamic range of the logarithm being greater than fixed-
point number systems for equal coefficient and sample
resolutions for both cases [9]. From Fig. 1, where p(t) is
the impulse response of the Transmitter RRC filter and a(t)
the antipodal baseband chips, a generic expression for the
complex filter output is given by:
∑ ⋅−⋅=
i
)Tit(p)t(a)t(S (8)
The effect of the frequency selective multipath channel,
G(f), and Noise on (8) is such that the received signal will
be somewhat uncorrelated with S(t) and the complex
receiver generated PN and OVSF sequences. The
Multipath interference was simulated using a modified
version of Clarke’s model [10], where the mobile signal
was subject to fading caused by the short term flat fading
Rayleigh distribution and the long term Log-Normal
distribution with delay spread typical of urban
environments.
Fig. 3: Transversal Tap structure of the receiver RRC matched filter
implemented with Logarithms.

4. IEEE Wireless Communications And Networking Conference (WCNC), 13 - 17 March 2005, Vol. 1, pp. 596 – 600,
2005.
0-7803-8966-2/05/$20.00 (C) 2005 IEEE 599
Fig. 4: RRC Frequency response for 9 bits coefficient and 11 bits data
resolution fixed point binary arithmetic.
Fig. 5: RRC Frequency response for 9 bits coefficient and 11 bits data
resolution fixed point hybrid log arithmetic.
This simulation was run with the floating point binary
FIR filter and the fixed point hybrid logarithmic FIR filter
with 11 bits sample data and 9 bits coefficient resolution.
The Fig. 6 shows the result of the SNR Vs BER plot where
it can be seen that a highly favorable comparison between
the hybrid logarithmic RRC matched FIR filter and the
floating point binary implementation ensues, hence
validating the use of logarithm base 2 arithmetic in
Matched filters for the UMTS Downlink.
V. CONCLUSION
The advantages of using the Hybrid LNS over linear
number systems are that no multiplication or division is
required in the filter computations. Comparing the results
for the fixed point binary and hybrid – Logarithmic
Fig. 6: BER Vs SNR for floating point data and 11 bit Hybrid
Logarithmic resolution for WCDMA downlink signals.
arithmetic for the RRC filter, it is apparent that using the
SLNS yields a superior response for the minimum
specifications depicted with the coefficient resolution of 9
bits, and data sample resolution of 11 bits. From the
simulation, it was also found that use of floating point
number systems is not necessary due to very similar results
obtained for the floating point FIR and hybrid-log FIR in
terms of the BER. Work is proceeding on the use of
Hybrid Logarithmic arithmetic for LMMSE Rake receivers
on mobile handsets. This is particularly useful due to
greater number of multiplications than additions being
required for the diversity algorithms. Work is also
proceeding on techniques to reduce the number of
addressable memory locations in the LUT.
ACKNOWLEGMENT
I would like to thank Harada Industries for their support
and expertise throughout this project.
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5. IEEE Wireless Communications And Networking Conference (WCNC), 13 - 17 March 2005, Vol. 1, pp. 596 – 600,
2005.
0-7803-8966-2/05/$20.00 (C) 2005 IEEE 600
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