In a recent article, a technique was proposed to step up the majority logic decoding of variation set low density parity check codes. This is helpful as majority logic decoding can be implemented serially with trouble-free hardware but requires a huge decoding time. The method detect whether a word has errors in the initial iterations of majority logic decoding, and at what time there are no errors the decoding split ends without completing the rest of the iterations. While the majority words in a memory will be error-free, the average decoding time is significantly reduced. The outcome obtained proves that the technique is also effective for EG-LDPC codes. General simulation results are given to precisely estimate the prospect of error detection for different code sizes and numbers of errors.

1. Integrated Intelligent Research (IIR) International Journal of Business Intelligents
Volume: 05 Issue: 01 June 2016 Page No.101-103
ISSN: 2278-2400
101
An Efficient Majority Error Detection in Logic
Decoding with Euclidean Geometry Low Density
Parity Check (Eg-Ldpc) Codes
M .Vengadapathiraj, U.Maheswaran A.Karunakaran
Assistant Professor,Department of Electronics & Communication Engineering,Rajalakshmi Institute of Technology, Chennai
Abstract—In a recent article, a technique was proposed to step
up the majority logic decoding of variation set low density
parity check codes. This is helpful as majority logic decoding
can be implemented serially with trouble-free hardware but
requires a huge decoding time. The method detect whether a
word has errors in the initial iterations of majority logic
decoding, and at what time there are no errors the decoding
split ends without completing the rest of the iterations. While
the majority words in a memory will be error-free, the average
decoding time is significantly reduced. The outcome obtained
proves that the technique is also effective for EG-LDPC codes.
General simulation results are given to precisely estimate the
prospect of error detection for different code sizes and numbers
of errors.
Keywords— Euclidean geometry low-density parity check
(EG-LDPC), Error correction codes, codes, majority logic
decoding.
I. INTRODUCTION
Low-density parity-check (LDPC) codes form a different class
of Shannon limit (or channel capacity)-approaching codes.
Regrettably, Tanner's work was also unnoticed by coding
theorists for another 14 years, until the late 1990s when some
coding researchers began to examine codes on graphs and
iterative decoding.Error correction codes are usually used to
protect memories as of so-called elastic errors, which change
the logical value of memory cells without harmful the circuit
[1]. As expertise scales, memory devices turn out to be better
and more powerful error correction codes are wanted [2], [3].
To this end, the use of more superior codes has been recently
proposed [4]–[8]. These codes can correct a superior number of
errors, but normally require complex decoders.To keep away
from a high decoding difficulty, the use of one step majority
logic Decodable codes be the first proposed in [4] for memory
applications. Additional work on this topic was then accessible
in [5], [6], [8]. One step majority logic decoding can be
implemented in sequence with very simple circuitry [9], except
require long decoding times. In a memory, this would increase
the entrée time which is an significant system parameter [12,
18, 19]. Only a small amount of classes of codes can be
decoded using one step majority logic decoding [9]. Among
those is some Euclidean geometry low density parity check
(EG-LDPC) codes which were used in [4], and disparity set low
density parity check (DS-LDPC) codes [9].The large classes of
finite-geometry LDPC codes have comparatively good
minimum distances, and their Tanner graphs do not have short
cycles [15]. These codes can be decoded in a range of ways
ranging from low to high decoding difficulty and from sensibly
good error performance to very good error performance. In
addition [7], these codes are either cyclic or quasi-cyclic.
Therefore, their encoding is easy and can be implemented by
linear shift registers [23]. Some long finite-geometry LDPC
codes contain error performance just a few tenths of a decibel
away from the Shannon limit.A method was lately proposed in
[10] to go faster a serial implementation of majority logic
decoding of DS-LDPC codes. The design is rear the process is
to use the first iterations of majority logic decoding to sense if
the word being decoded contains errors. If there are no errors,
then decoding can be congested without finishing the remaining
iterations, so greatly dipping the decoding time.
N K J tML
15 7 4 2
63 37 8 4
123 62 16 8
255 167 32 16
1023 765 64 32
Table 1: one step MLD EG-LDPC CODE
Another benefit of the proposed technique is that it requires very
little additional circuitry as the decoding circuitry is too used for
error detection. For illustration, it was shown in [10] that the
extra area required to implement the system was only around 1%
for large word sizes.The method proposed in [10] relies on the
properties of DS-LDPC codes and so it is not directly related to
other code classes. In the following, a related approach for EG-
LDPC codes is obtainable. The rest of this concise is divided
into the following sections. Section II provide preliminary on
EG-LDPC codes, majority logic decoding and the method
proposed in [10]. Section III presents the results of Applying the
scheme to EG-LDPC codes, include simulation results and a
hypothesis based on those results [23]. This is complemented by
a theoretical proof used for the cases of one and two errors that
is provided in an Appendix.

2. Integrated Intelligent Research (IIR) International Journal of Business Intelligents
Volume: 05 Issue: 01 June 2016 Page No.101-103
ISSN: 2278-2400
102
II. EG-LDPC CODES
This geometry consists of 2"'s point, and each point is
representing by an m-tuple over GF (2'). The point represented
with the all-zero in-tuple, 0 = (0, 0…. 0), is called the origin.
There are lines in EG (in, 2s), and each line consists of 2' points.
every point in EG (in, 2') is intersected bylines. Two lines in EG
(in, 2s) are either disjointed or they cross at one and only
point.To build a type-1 EG-LDPC code based on EG form the
parity-check matrix whose rows are the incidence vectors of all
the lines in EG and whose columns correspond to all the points
in EG. Therefore, E• G consists of rows and o = 2"'s columns.
Since every line in EG consists of 2' points, each row of FI (L)
has weight p = 2s. Since each point in EG (in, 2') is intersect by
(2"" – 1)/ (2" – 1) lines, every column of SEC have weight y =
(2"'s – 1)/ (2" – 1).
Fig. 1. Serial one-step majority logic decoder for the (15, 7) EG-
LPDC code.
The null space of 1 (E1G) therefore gives an LDPC code of
length n = 2"'", which is call an in-dimensional type-1 (0, s) th-
order EG-LDPC code, denoted by (m, 0, s). The least distance of
this code is lesser bounded as follows: Because (2"1" – 1)/ (2" –
1) orthogonal check-sums can be shaped for each code hit, this
code is proficient of correcting t Ai L = L (2"' -1)/2(2' -1)] or
less arbitrary errors with one-step majority-logic decoding.
N 1 error 2 error 3error 4 error
15 0 0 0 0
63 0 0 0 0
123 0 0 0 0
255 0 0 0 0
1023 0 0 0 0
Table 2: Undetected Errors in Exhaustive Checking
If errors can be detected in the first some iterations of MLD,
then when no errors are detected in those iterations, the decoding
can be stopped without completing the respite of the iterations.
In the first it- eration, errors will be detected when at least one of
the check equations is precious by an odd number of bits in
error[5,12,19]. In the second iteration, as bits are regularly
shifted by one position, errors will involve other equations such
that some errors undetected in the first iteration will be detected.
As iterations go forward, all detectable errors will eventually be
detected.Then the proposed system was implemented in VHDL
and synthesized, showing that for codes with large block sizes
the overhead is low. This is since the existing majority logic
decoding circuitry is reused to do error detection and only a
number of additional control logic is required.
III. SIMULATION RESULTS
The method proposed in [10] has been functional to the class of
one step MLD EG-LDPC codes. To present the results, the
conclusion is obtainable first in terms of a suggestion that is then
validate by simulation and also partly by a theoretical study
presented in the addendum. The results obtain can be
summarized in the following hypothesis. “Given a word read as
of a memory sheltered with one step MLD EG-LDPC codes, and
affected by up to four bit-flips, all errors can be detected in only
three decoding cycles”.Note that this theory is diverse from
the one made for DS-LDPCs codes in [10] as in that case
errors upsetting up to five bits were forever detected. This is
owed to structural differences between DS-LDPC and EG-LDPC
codes, [14 and 20] which will be detailed in the Appendix. To
validate the over hypothesis, the EG-LDPC codes measured
have been implemented and experienced.The results for the
comprehensive checks are shown in Table 2. These results show
the hypothesis for the codes with slighter word size (15 and 63).
For up to three errors have been thoroughly tested while for only
single and double error combination have been exhaustively
testedThe simulation outcome presented proposes that all errors
affecting three and four bits would be detected in the first three
iterations. For errors affecting a better number of bits, there is a
small likelihood of not being detected in those iterations [23].
For large word sizes, the probabilities are sufficiently small to be
acceptable in many applications.In summary, the first three
iterations will detect all errors moving four or less bits, and
approximately every further detectable error affecting more bits.
N 5
error
6
error
7error 8
error
9error 10
error
15 0 0 0 0
63 0 0 0 0
123 0 0 0 0
255 0 0 0 0
1023 0 0 0 0

3. Integrated Intelligent Research (IIR) International Journal of Business Intelligents
Volume: 05 Issue: 01 June 2016 Page No.101-103
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Table3: Undetected Errors with one Billion random Error
combinations
This is a slightly inferior performance than in the case of DS-
LDPC codes [10] where errors affecting five bits be adding- ally
always detected. Though, the majority logic circuitry is simpler
for EG-LDPC codes, as the amount of equations is a power of
two and an approach base on sorting networks proposed in [8]
can be used to decrease the rate of the majority logic voting.
IV. CONCLUSION AND FUTURE WORK
The detection of errors through the first iterations of sequential
one step Majority Logic Decoding of EG-LDPC codes has been
considered. The objective was to shrink the decoding time by
stopping the decoding process when no errors are detected. The
simulation outcome shows that all experienced combinations of
errors upsetting up to four bits are detected in the first three
iterations of decoding. These outcomes extend the ones lately
accessible for DS-LDPC codes, making the modified one step
popular logic decoding more attractive for memory applications.
Future work includes extending the academic analysis to the
cases of three and four errors. More normally, decisive the
necessary number of iterations to detect errors affecting a given
number of bits seems to be an interesting problem. A universal
solution to that trouble would enable a fine-grained tradeoff
between decoding time and error detection ability.
REFERENCES
[1] R. C. Baumann, “Radiation-induced soft errors in advanced semicon-
ductor technologies,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 3,
pp. 301–316, Sep. 2005.
[2] M. A. Bajura, Y. Boulghassoul, R. Naseer, S. DasGupta, A. F. Witulski,
J. Sondeen, S. D. Stansberry, J. Draper, L. W. Massengill, and J.
N.Damoulakis, “Models and algorithmic limits for an ECC-based ap-
proach to hardening sub-100-nm SRAMs,” IEEE Trans. Nucl. Sci.,
vol.54, no. 4, pp.
[3] R. Naseer and J. Draper, “DEC ECC design to improve memory reli-
ability in sub-100 nm technologies,” Proc. IEEE ICECS, pp. 586–
589,2008.
[4] S. Ghosh and P. D. Lincoln, “Dynamic low-density parity check codes
for fault-tolerant nano-scale memory,” presented at the Foundations
Nanosci. (FNANO), Snowbird, Utah, 2007.
[5] S. Ghosh and P. D. Lincoln, “Low-density parity check codes for error
correction in nanoscale memory,” SRI Computer Science Lab.,
MenloPark, CA, Tech. Rep. CSL-0703, 2007.
[6] H. Naeimi and A. DeHon, “Fault secures encoder and decoder for
memory applications,” in Proc. IEEE Int. Symp. Defect Fault
Toler.VLSI Syst., 2007, pp. 409–417.
[7] B. Vasic and S. K. Chilappagari, “An information theoretical frame-
work for analysis and design of nanoscale fault-tolerant memories based
on low-density parity-check codes,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 54, no. 11, pp. 2438–2446, Nov. 2007.
[8] H. Naeimi and A. DeHon, “Fault secure encoder and decoder for
nanomemory applications,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 17, no. 4, pp. 473–486, Apr. 2009.
[9] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood
Cliffs, NJ: Prentice-Hall, 2004.
[10] S. Liu, P. Reviriego, and J. Maestro, “Efficient majority logic fault
detection with difference-set codes for memory applications,”
IEEETrans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 1, pp.
148–156, Jan. 2012.
[11] H. Tang, J. Xu, S. Lin, and K. A. S. Abdel-Ghaffar, “Codes on finite
geometries,” IEEE Trans. Inf. Theory, vol. 51, no. 2, pp. 572–596,
Feb.2005.
[12] Pedro Reviriego, Juan A. Maestro, and Mark F.Flanagan,” Error
Detection in Majority Logic Decoding of Euclidean Geometry Low
Density Parity Check (EG-LDPC) Codes” IEEE Trans. Very Large
Scale Integration (VLSI) Systems,Vol. 21, No. 1, January 2013.
[13] R. C. Baumann, “Radiation-induced soft errors in advanced
semiconductor technologies,” IEEE Trans. Device Mater.Reliab., vol. 5,
no. 3, pp. 301–316, Sep. 2005.
[14] M. A. Bajura, Y. Boulghassoul, R. Naseer, S.DasGupta, A. F.Witulski,
J. Sondeen, S. D. Stansberry, J. Draper, L. W.Massengill, and J.
N.Damoulakis, “Models and algorithmic limits for an ECC-based
approach to hardening sub-100-nm
[15] SRAMs,” IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 935–945, Aug.
2007.
[16] R. Naseer and J. Draper, “DEC ECC design to improve memory
reliability in sub-100 nm Technologies,” Proc. IEEE ICECS, pp. 586–
589, 2008.
[17] S. Ghosh and P. D. Lincoln, “Dynamic low-density parity check codes
for fault-tolerant nano-scale memory,” presented at the Foundations
Nonsocial. (FNANO), Snowbird, Utah, 2007.
[18] S. Ghosh and P. D. Lincoln, “Low-density parity check codes for error
correction in nanoscale memory,” SRI Computer Science Lab., Menlo
Park, CA, Tech. Rep. CSL-0703, 2007.
[19] H. Naeimi and A. DeHon, “Fault secures encoder and decoder for
memory applications,” in Proc. IEEE Int. Symp.Defect Fault Toler.
VLSI Syst., 2007, pp. 409–417.
[20] Pedro Reviriego, Juan A. Maestro, and Mark F. Flanagan “Error
Detection in Majority Logic Decoding of Euclidean Geometry Low
Density Parity Check (EG-LDPC) Codes” IEEE transactions on very
large scale integration (vlsi) systems, vol. 21, no. 1, January 2013.
[21] H. Naeimi and A. DeHon, “Fault secure encoder and decoder for
nanomemory applications,” IEEE Trans. Very LargeScale Integr.
(VLSI) Syst., vol. 17, no. 4, pp. 473–486, Apr. 2009.
[22] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood
Cliffs, NJ: Prentice-Hall, 2004.
[23] Pedro Reviriego, Juan A. Maestro, and Mark F. Flanagan “Error
Detection in Majority Logic Decoding of Euclidean Geometry Low
Density Parity Check (EG-LDPC) Codes” IEEE transactions on very
large scale integration (vlsi) systems, vol. 21, no. 1, January 2013.

4. Integrated Intelligent Research (IIR) International Journal of Business Intelligents
Volume: 05 Issue: 01 June 2016 Page No.101-103
ISSN: 2278-2400
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