Data transmission with gbits speed using cmos based integrated circu

International Journal of Computer Engineering and Technology (IJCET), ISSN 0976-
6367(Print), ISSN 0976 – 6375(Online) Volume 4, Issue 3, May – June (2013), © IAEME
188
DATA TRANSMISSION WITH GBITS SPEED USING CMOS BASED
INTEGRATED CIRCUITS FOR OPTO-ELECTRONIC INTERFACES
AND APPLICATIONS
R. K. Singh, Ashish Dixit
Department of Electronics & Comm. Engineering,
Kumaon Engineering College (KEC),
Dawarahat (Almora), Uttarakhand
ABSTRACT
The performance of the data transmission using the principle of the optical
communication can be enhanced further simply by increasing both the wavelength count and
bit rate per channel, so as to improve the utilization of the optical fiber bandwidth. This
approach in turn requires the most suitable device structures and the technologies for both
opto-electronic transducers and the associated driving electronics circuitry. The number
of transistor stages required between the power and ground rails is only two so that the
minimum supply voltage required is one threshold voltage plus one pinch-off voltage. The
pre-amplifier is a balanced two-stage configuration such that the effect of bias-dependent
mismatches is minimized. A new inductive series-peaking technique has been introduced so
as to enhance the bandwidth by utilizing the resonance characteristics of LC networks. In
addition to this arrangement, a new negative differential current feedback technique has been
put forward for the discussion so as to boost the bandwidth of the system and to reduce the
value of peaking inductors. This pre-amplifier circuit has been implemented in TSMC 0.18
µm, 1.8 V, 6-metal mixed mode CMOS technology and is analyzed using Spectre from
Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3
pF photodiode capacitance, simulation results demonstrate that the pre-amplifier has
bandwidth of 3.5 GHz and provides a trans-impedance gain of 66 dB. The total chip area is
approximately 1 mm2
and the DC power consumption is about 85 mW
INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING
& TECHNOLOGY (IJCET)
ISSN 0976 – 6367(Print)
ISSN 0976 – 6375(Online)
Volume 4, Issue 3, May-June (2013), pp. 188-203
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189
Keywords: Optical fiber transmission, Optoelectronic device, Integrated circuit, High
rate, State of the art, Two-dimensional electron gas transistor, Gallium arsenide, Indium
phosphide current-mode circuits, preamplifier, inductive peaking, current feedback
I. INTRODUCTION
The Optical communications is one of the corner stones of today’s revolution in the
information technology. The vast distances of optical fiber span the globe, connecting the
world together in an intricate communications infrastructure. With the drive towards portable
and multimedia communications, the system has increasingly faced with the challenge of
bringing the capacity of our communications infrastructure directly to the user, providing
seamless access to vast quantities of information, any where and anytime. Whether it is the
transfer of an image from a digital camera to a laptop computer or the communication of data
within a massively parallel computer, there is an urgent need to develop new methods of high
speed data communications. Light offers many advantages as a medium for communication.
Whether travelling through free space or through optical fiber, light enjoys unequalled channel
bandwidth, and is capable of data rates in the terabits per second. This immense capacity is
due to the nature of the photons that constitute an optical signal. As such, the optical signals
neither generate nor are sensitive to electromagnetic interference (EMI), parasitic coupling,
and other problems faced by electrical. Given their advantages, optical links are rapidly
expanding into application areas beyond traditional fiber-optic links. Three simple applications
of so-called “carrier” applications that are concerned with transporting information across the
greatest possible distance are free-space inter satellite links, fiber-to-the-home (FTTH) and
terrestrial free-space links for inter-building [01-03]. The shorter distance applications include
the optical-based local area networks (LANs) as represented by Asynchronous Transfer Mode
Passive Optical Networks (ATMPON and Gigabit Ethernet standards based applications that
involve the optical communications within digital systems or in large computers i.e. generally
referred to as optical interconnect that include smart pixel arrays, opto-coupler arrays and
optical backplanes [06]. In particular, the short-range “point-and-shoot” systems in accordance
to the Infrared Data Association (IrDA) provide a simple solution for transferring information
to and from portable devices, offering high data rates at low cost and with a small form factor
that is not prone to mechanical wear. The success of such short-range systems is particularly
telling of how optical communication systems are likely to proliferate in the future: as of 1998,
over 100 million laptops, digital cameras, and other devices were shipped equipped with
IrDA-compatible serial ports, and currently over 40 million new devices are being produced
yearly. The IrDA wireless link has overshadowed both the Universal Serial Bus (USB) and
IEEE 1394 FireWire to become the leading serial-port alternative for connectivity [04-07].
Figure 1.1 shows the basic elements of an optical link. On the transmit side, an information
source produces a data stream that is encoded and sent to the appropriate drive circuitry used
to modulate the optical signal generated by either a light emitting diode (LED) or laser. The
signal propagates through free space or through a waveguide such as optical fiber until it
reaches the photo detector on the receiver end. The photo detector converts the optical signal
into an electric current that is sensed by the optical pre-amplifier and regenerated to a
sufficiently strong voltage signal from which the original data can be recovered by the
demodulator.

190
Figure 1 Block diagram of a typical optical link.
The expansion of optical communications into new applications has created exciting
opportunities for the research and innovation of optical receivers. While the growth of fiber-
optic networks in the last few decades has refined our understanding of optical receivers, its
primary focus has been on speed and sensitivity. With the expansion of optical
communications come new requirements on receiver designs. Probably the most widespread
trend has been that of increased system integration and the drive to reduce system
components, cost, and size. Traditionally, optical receivers have not been subject to many
system level constraints since optical receivers for long-haul fiber-optic networks are
principally designed for performance rather than cost. As such, they have typically used
advanced high-speed semiconductor technologies such as GaAs and Si bipolar processes.
Increasingly, the new optical receiver designs are being implemented in low-cost, high-
integration technologies such as CMOS. However, the desire to implement in CMOS implies a
need to design receivers that keep pace with developments in CMOS technology. One of the
dominant trends is the continuous reduction of the system supply voltage as shown in Figure
1.2. The upper and lower boundary lines are drawn to highlight the fact that the ‘industry
standard’ voltage is disappearing, being replaced instead by a range of voltages encompassing
different applications. Increasingly, the supply voltage is seen as an adaptable design
parameter used to optimize performance and minimize power. The logic circuits that operate
with supply voltages near or even below the threshold voltage are being reported alongside
analog circuits that do the same. The low-voltage operation is partly driven by the desire for
low power in portable applications and in applications that require battery back-up such as
fiber-to-the-home (FTTH). In the end, low-voltage operation will be crucial to the long-term
viability of integrated optical receivers [08-10].
Figure 2 Projected trends in system supply voltages.
The recent advance in CMOS technology, mainly driven by the low-power
applications, has significantly lowered supply voltage. The reduction in threshold voltages,
however, is rather moderate in order to minimize the static power consumption arising from

191
sub-threshold conduction. As a result, the performance of voltage mode circuits, such as
dynamic range, is affected greatly. CMOS current-mode circuits offer many attractive
advantages over their voltage-mode counterparts. The key performance feature of current-
mode circuits is their inherent wide bandwidth. The other advantages include low supply
voltage requirement, large dynamic range, and tunable input impedance. These characteristics
make current-mode circuits particularly attractive for high-speed interface circuitry. The
analog amplifiers are susceptible to power and ground fluctuations caused by the switching of
digital portion of mixed-signal circuits, such as clock and data recovery circuits in optical
transceivers. The accuracy of current-mode circuits is severely affected by the errors due to
device mismatches. Low-voltage current-mode circuits that are insensitive to device
mismatches and switching noise are highly desirable. In addition, a main drawback of current-
mode circuits is their low current gain. To increase the current gain, the size of the transistor in
the output branch can be made large, how-ever, at the cost of reduced bandwidth. The
technique introduced increases the bandwidth of current-mirror amplifiers by cancelling out
the dominant pole with a compensating zero obtained by inserting a resistor between the gates
of the input and output transistors of the amplifiers. In this system, an adjustable gain optical
amplifier is used in front of the photo receiver, so as to reduce both the requirement in
receiver sensitivity and the amount of gain required from the electronic amplifier. A flip-flop
is then used so as to perform the decision making part. In the present scenario, the decision is
usually not performed at the Gbit/s signal level because of the very limited availability
of circuits clocked at GHz range. The signal transmission over the fiber suffers from a number
of impairments such as chromatic dispersion enhanced by the chirp characteristics of the
source, polarization mode dispersion, nonlinear channel interaction. Such impairments are
getting more and more detrimental as the bit rate increases, most often they can be
compensated at the optical signal power level or electronically at the receiver level [10-12].
The detailed schematic of the transmitter and receiver has been shown in figures 3 and 4
respectively.
Figure 3 Schematic diagram of a Transmitter
Figure 4 Schematic diagram of a Receiver
II. REQUIREMENTS FOR THE GBIT/S OPTOELECTRONIC INTERFACE ICS
As discussed in the introduction of the problem, both the analog (e.g. amplifiers) and
digital ICs (e.g. MUXES) are needed for assembling the design of the optoelectronic
transmitters and receivers, calling for specific requirements in terms of microelectronic

192
technology characteristics. For the analog parts, what matters first is the gain available over
the required bandwidth from a given technology; much attention is then paid to the
power gain cut-off frequency FMAX, known as the maximum oscillation frequency i.e.
higher the FMA X, higher the available gain over a given, large, bandwidth. For the
bandwidths required at a specific data transmission rate in Gbit/s range depending on the
application requirements, only the technologies offering FMAX can be envisioned. For
example, For a given technology, the distributed amplifier structures help getting the better in
terms of gain-bandwidth product: actually, assuming identical impedance for both input and
output lines and loss-less lines, the total voltage gain (Gv) is set by both the stage
(transistor) gain (Gs) with Gs = gm Z, where gm is the transistor trans-impedance, and the
number of stages (N); a situation to be contrasted with conventional lumped amplifiers [13]:
Gv ≈ Gs × N/2 (distributed amplifier) (1)
Gv ≈ GsN (lumped amplifier) (2)
These above mathematical expressions indicate that even with a stage gain close
to one, that is with a stage bandwidth close to FT, a large total gain can be obtained
with distributed amplification (although limited by the line losses which set a limit to the
bandwidth as well as to the number of stages), while the lumped amplifier requires the stage
gain to be sensitively larger than one to provide a large total gain.
Figure 5 Gain vs. bandwidth characteristics of single chip amplifiers.
Thus, based on the discussion to a larger extent, the performance of the
interconnection depends on the receiver’s gain, bandwidth, power consumption, and area
requirements. These four parameters can be traded off against each other. By adjusting the
number of amplifying stages, the transistor sizes, and the bias voltages, the receiver circuit
can be designed to optimize the link performance i.e.
1) Bit Rate: The location of the poles in the receiver transfer function determines the 10–
90% rise time in response o a step input. The bit rate of the overall receiver can be
determined from the rise times of each of the components BR [14]
(3)
where ζ determines what percentage of the bit period makes up he rise time. The rise times for
the receiver components are given in Table I. The TIA is designed to have a response that
closely approximates a maximally ﬂat magnitude (MFM) response, i.e. the two poles closest to

193
the origin are at 45. This is achieved with an appropriate value feedback resistor. It can be seen
from Table I that receivers with a three-stage TIA are significantly slower than ones with a
one-stage TIA, when both are constructed from identical amplifying stages. In general, it can
be shown that when the number of stages in a feedback loop increases, the bandwidth
decreases. However, in order to determine when three-stage TIA based receivers are
competitive, the trans-impedance gain must be examined as well [15].
Table 1 10–90% rise time formulas
2) Transimpedance Gain: The trans-impedance of the receiver determines its sensitivity. In
order to ensure stability and eliminate resonance peaking in the receiver transfer function, the
trans-impedance of the amplifier is adjusted to approximate a maximally flat magnitude
response. The trans-impedance can then be calculated based on the gain, bandwidth, input
capacitance and transconductance of the amplifying stages, the total number of stages, and the
photodiode capacitance. For the one-stage TIA to have a maximally flat magnitude response,
the input open-loop pole must be smaller than the second open-loop pole by a ratio of [16]
(4)
Cpd is the photodiode capacitance plus any parasitic capacitance, and is taken as 100 fF in the
analysis. This corresponds to a flip-chip bonded 400 m MQW detector. Since optical
alignment and spot sizes are not expected to scale as the gate length of the technology, this
value is constant for all three technologies considered in this paper. The value of Rf obtained
by solving (2) is used to determine the trans-impedance of the one-stage TIA, which is given
by [17]
(5)
The three-stage TIA has four open-loop poles, one at fin and three overlapping poles at fout. In
order for the three-stage TIA to approximate a maximally-flat magnitude transfer function, the
input open-loop pole must be related to the other three open-loop poles by [18]
(6)

194
The trans-impedance of the three-stage TIA is given by equation 6, with 1+ Av
-1
replaced with 1+ Av
-3
, since there are now 3 stages providing gain in the TIA. The overall
trans-impedance gain, TZ, is the receiver’s output voltage divided by the input current, and is
given by the voltage gain of the -stage post ampliﬁer times the trans-impedance of the TIA
[19]
(7)
3) Noise: The circuit noise introduced by the receiver and detector is referred to the receiver
input for signal to noise ratio determination.
4) Power: The electrical power dissipation of the (N+P) stage receiver is determined from the
bias current Ids, and the power supply voltage Vdd, and can be written:
(8)
There is additional power dissipation due to the switching of the node capacitances in
the receiver, but this component is orders of magnitude less than the power dissipation due to
the bias current [20]. The low frequency noise is another feature of importance, as it
impacts the spectral purity of oscillators and multipliers (the jitter tolerances are quite
stringent for the various circuits, as the peak to peak jitter should be lower than 2 ps).
Digital lCs operating in the range of Gbit/s are often thought of as mixed-signal lCs as their
microwave/analog features have a major impact on their digital operation. When
considering a basic assembly of logic gates, the operating speed is often quoted through the
gate propagation delay time (xr, o), which depends on both the switching transistor intrinsic
speed and the response time of the surrounding circuit, as shown in the following expression:
TpD = (2riFT)-1 + n(Cp +CI) AV/I (9)
where n is the gate fan-out (usually small in very high-speed ICs), C~ and Cp
stand for the input capacitance of a gate and the parasitic (wiring) capacitance respectively;
AV and I are the voltage swing and the active load current respectively. To keep with
general statements, one could point out the following requirements [21-25]:
• high current density, so as to reduce CIfI: this obviously implies small
dimension transistors in order to avoid thermal problems, as well as a high
current density;
• low wiring capacitance: this calls for a compact layout, and thick enough
dielectric layers to reduce interconnection capacitance. This is especially
important for FET technologies as they are usually characterized by lower C I
(and lower currents) than bipolar processes as shown in figure 6.

195
Figure 6 Digital circuits speed vs. device performance,
III. CURRENT STATUS OF III-V ELECTRONIC TECHNOLOGIES FOR 40
GBIT/S ICS
The semiconductor technologies considered presently for the fabrication of 40 Gbit/s
ICs include SiGe bipolars, GaAs pseudomorphic and metamorphic HEMTS and HBTS
(Heterojunction Bipolar Transistors), InP HEMTS and HBTS. Together these technologies
have already produced los able to allow the demonstration of first generation 40 Gbit/s
systems, even though further developments are obviously needed to obtain chip sets able to fit
the requirements of commercial optical systems. These various technologies keep evolving
and make continuous progress in terms of high-speed performance, consumption and/or
cost. As an example, during the last 10 years, the speed of static frequency dividers has been
improved by a factor of 2.5 to 5 for the InP and SiGe bipolar technologies respectively [26].
With this evolution in mind, one can also envision Si CMOS to be finding applications in a
40 Gbit/s chip set, in particular as transmission impairments mitigation will require rather
complex circuits. Shrinking the gate length below 100 nm, introduction of SiGe p-MOSFET
structure and other developments presently in progress may bring new openings for CMOS
in 40 Gbit/s applications [27]. The main factors that will decide which technologies will be
chosen are probably the following, their respective weight depending on the application:
• Performance i.e. the key factor even though the specifications are not yet
fully defined and some margin will be appreciated to overcome dispersion,
aging, characteristics degradation after packaging,
• Target specifications i.e. as the optoelectronic components or even the
transmission fiber characteristics evolve, specifications may change, making it
more appropriate to use another technology for a given function.
• DC power consumption i.e. as the wavelength-multiplexing capability is a
system requirement, low consumption is an important factor to reduce footprint
of terminal equipments. A total power consumption of 10-12 W is presently
targeted for a transmitter-receiver pair.
• Gate count is another important aspect, since signal processing is becoming
most useful (FEE, impairment mitigation) as bit rate increases.
• Cost is obviously an issue and this applies to the complete transponder.

196
TABLE 2: Figure of merit for various materials [28]
III.1. GaAs ICs for 40 Gbit/s applications:
The GaAs microelectronics device has long been a choice of the technology for the
design of high-speed circuits for optical transmission, in particular with MESFETS used as
photo receiver preamplifiers and in digital ICs. As bit rates kept increasing, the MESFET
technology ran out of performance, leaving the field to hetero-junction technologies that
are now exclusively used in 40 Gbit/s high-speed interfaces [29].
IILI.1. GaAs HEMTS and 40 Gbit/s analog circuits:
Since the GaAs HEMT was invented in 1980, many improvements have been
brought to the structure, in particular with the introduction of the so-called k-doping of the
barrier layer and the pseudomorphic strained InxGal_xAS channel, with an In content of x
= 0.25. This pseudomorphic channel is characterized by a smaller band gap than GaAs,
which increases the conduction band discontinuity with the barrier (hence a higher electron
sheet density in the channel), and higher electron mobility than GaAs as shown in figure 7.
These characteristics translate into a higher current density, hence larger FT and FMAX, while
retaining very attractive break- down behavior [30]. However, this is not possible since the
critical strained channel thickness beyond which dislocations appear would become too small
to accommodate a large enough carriers density. To overcome this limit, a new concept was
introduced with the metamorphic HEMT (M-HEMT) characterized by an InGaAs channel
with a much higher In content (usually 0.3 <x< 0.5). The InGaAs channel and its lattice-
matched AllnAs barrier are grown on a strain-relaxed thick buffer that accommodates the
lattice mismatch and absorbs dislocations originating from the GaAs substrate.
Figure 7 GaAs P-HEMT and InP composite channel HEMT structures [31]

197
IIl.l.2. GaAs HBTS and mixed signal circuits:
The potential of GaAs HBTS for the fabrication of optical telecommunications ICS has
also been explored. Worth noting is the successful development of a 10 Gbit/s chip set by
Nortel some years ago [32]. Pushing further this technology towards 40 Gbit/s applications has
been an objective for a few research domains, and 20 Gbit/s-class digital circuits have been
also produced to some extent [34-35]. More recently, using a highly doped re-grown extrinsic
base structure, which helps reducing the access base resistance and allows high FMA X (close
to 200 GHz for an F T above 100 GHz), the research demonstrated a 43 Gbit/s receiver chip
set including a decision circuit [36]. However, the most developments in GaAs HBT
technology are focused on microwaves applications, such as power amplifiers for hand
sets, with little development effort left for adjusting to the requirements of very high bit rate
circuits i.e. reducing the emitter width and the base-collector junction area to improve cut-off
frequencies, demonstrating a new base material to lower the turn-on voltage and reduce the
power consumption [37].
III.2. 40 Gbit/s ICs on InP substrates:
InP and its related compounds, AlInAs and InGaAs, have produced transistors
with record high frequency performances for quite a few years; with the projected
development of optical transmission at 40 Gbit/s, first commercial microelectronics
applications have been envisioned for those materials, in spite of both the brittle substrates
making processing more difficult than with GaAs wafers and the limited substrate size (3
to 4 inch semi-insulating wafers are presently used; but one should notice that some 3-4
inches GaAs foundries are still profitable) [38]. However, the broad variety of available
hetero structures in the InP family offers the device designer a full range of combinations to
optimize HEMTS and HBTS, in terms of high-speed and high-output voltage [39].
III.2.1. InP-based HEMT circuits:
A record cut-off frequencies have been reported since the early 90s for InGaAs-
channel InP-based HEMTS, with values of 350 GHz for F T and 600 GHz for FMA x for
0.1 lain gate length, recently increasing to 560 GHz for F T at 25 nm gate length [40].
These figures actually translate the high electron saturation velocity in InGaAs and the high
confinement energy of the InA1As/InGaAs hetero junction (about 0.5 eV). Such high
frequency performances have led to record high bit rate operation of digital ICs, such as
MUXes, DMUXeS and decision circuits, and a complete 40 Gbit/s AllnAs/GaInAs HEMT
chip set a few years ago [41]. The first and foremost circuits have been fabricated,
including arrays of monolithically integrated photodiode/preamplifiers (designed for 10
Gbit/s applications and wide-band (90 GHz) distributed amplifiers as shown in figure 8,
characterized by a state of the art 410 GHz gain-bandwidth product and a promising
output swing of 2 V [42-45].

198
Figure 8 InP composite channel HEMT 10 stage distributed amplifier [46]
III.2.2. InP-based HBT circuits:
An InP-based HBT static frequency divider operating at 39 GHz has been discussed
quite earlier. However, it is only in recent years that the InP-based HST technology was
identified as a choice technology for assembling a 40 Gbit/s digital chip set. The HST
technology can be considered as a maturing technology and different InP structures and
processes are still investigated worldwide: single or double hetero structure (D-HBT), AlInAs
or InP emitter, InGaAs or GaAsSb base, Zn, Be or C doping of the base, now taking
advantage of both of the selective etching properties of the emitter-base and base-
collector hetero junctions, and the low recombination velocity of InGaAs (or GaAsSb)
surface, small dimension HBTS (emitter width below 1 lam) can be processed, as needed
for high frequency / low power consumption performances [47].
Figure 9 Schematic band diagrams of lnP D-HBT structures
In the InP HBT technology, this is competing with the SiGe one i.e. MUX and
DMUX ICs have also been developed in the later technology, as well as wide band
amplifiers, and further improvements with the performances are likely to result from
continuous progress in cut-off frequencies (an F T > 200 GHz has recently been
reported at an emitter width of 0.12 ~tm. The static frequency dividers operating above
80 GHz have been discussed, at a frequency close to the best InP. However, very thin
collectors are required to produce such fast devices, which sets a limit to the output voltage
they can sustain. The InP D-HBT process developed at or, to+ is based on a structure
with a graded base grown by using the chemical beam epitaxial approach [48-52].

199
Figure 10 Evolution of InP HBTS cut-off frequencies with emitter width [53]
A mixed dry and wet chemical etching allows for an undercut collector, which is
instrumental in reducing the base-collector capacitance and reaching high cut-off
frequencies (F T = 180 GHz; FMA x = 220 GHz), suitable for designing 40 Gbit/s ICS.
A number of 40 GbitJs-class circuits, such as a 2.2 V selector-driver and more recently a
family of D Flip-Flops aimed at 3R regeneration or Decision characterized by a high
sensitivity, a large phase margin and a low jitter well below 1 ps as shown in figure 11
[54].
Figure 11 Eye diagrams illustrating the regenerating characteristics of InP D-HBT flip-flops
[55]
CONCLUSION
With the first 10 Gbit/s WDM systems now in full operation, the focus of the
research laboratories has now shifting towards more efficient systems with denser
wavelength multiplex or higher bit rate. The transmission of the data at a rate of 40 Gbit/s
per channel has motivated the development of new components for dispersion
management, faster optoelectronic devices and lCs enable to operate at such high bit
rate. In the last few years, ICs were reported in various technologies, able to operate at the
proper speed, then offering the required functionality with the possible further improvement
needed in terms of power consumption, most circuits needed for the fabrication of
transmitters and receivers operating at 40 (or 43 Gbit/s). Large signal models able to
describe accurately the operation of active devices and specific circuit design tools and
methodologies which have been purposely developed also contributed largely to the
demonstration of circuits suitable to 40 Gbit/s transmission, that is offering some speed
margin with respect to system specifications. Now in order to make 40 Gbit/s transmission
a reality, it is mandatory to demonstrate its cost effectiveness, which applies to the cost
of both transmission and terminal equipments. For that reason, it is still questionable to
identify short reach or long haul transmission as the first market for 40 Gbit/s transmissions.

200
ACKNOWLEDGEMENTS
The authors are thankful to Prof. D. S. Chauhan (Vice Chancellor, UTU) for providing
the environment for this work, Mr. Aseem Chauhan (Additional President, RBEF), Major
General K. K. Ohri, AVSM, Retd. (Pro VC, AUUP, Lucknow Campus), Prof. S. T. H. Abidi
(Director, ASET) and Brig. Umesh K. Chopra, Retd. (Dy. Director, ASET) for their kind
cooperation, motivation, kind and most valuable suggestions.
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