Introduction to fpga synthesis tools
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Introduction to fpga synthesis tools
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Introduction to fpga synthesis tools
- 1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved Introduction to FPGA Synthesis Tools Prepared by: Eng. Hossam Fadeel National Telecommunication Institute 2011
- 2. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 2 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 2 © 2009 Xilinx, Inc. All Rights Reserved Design Languages Flow for FPGA Implementation Overview of an FPGA Design Tools for synthesis and implementation of FPGAs Agenda
- 3. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 3 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 3 © 2009 Xilinx, Inc. All Rights Reserved FPGAadvantage VHDL Entry ModelSim VHDL Simulation Leonardo Spectrum FPGA/ASIC Synthesis SDF File for Timing Simulation FPGA Implementation Software Download Design to FPGA EDF FPGA Vendor Flow for FPGA Implementation
- 4. FPGA and ASIC Technology Comparison - 4 © 2009 Xilinx, Inc. All Rights Reserved Design Languages
- 5. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Design languages provide the means by which to describe the operation of both software programs and hardware. These descriptions, usually text based, are Developed within the computer on which the descriptions are being Developed. Over the years, a large number of languages have been developed. Some are still in use today, while others have become obsolete. Design Languages
- 6. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Software Programming Languages Software programming languages (SPLs) allow a software designer to create executable software applications that will operate on a suitable processor. The target processor will be one of three types: microprocessor (mP), microcontroller (mC), or digital signal processor (DSP). Hardware Description Languages Hardware description language (HDL) design is based on the creation and use of textural based descriptions of a digital logic circuit or system. By using a particular HDL, the description of the circuit can be created at different levels of abstraction from the basic logic gate description according to the language syntax and semantics. Design languages are of two types, software programming languages (SPL) and hardware description languages (HDL). Design Languages
- 7. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Design Languages Flow Software flow Hardware flow
- 8. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved Software Programming Languages Common Software Programming LanguagesCommon Software Programming LanguagesCommon Software Programming LanguagesCommon Software Programming Languages CC C++C++ Visual Basic TM Visual Basic TM JAVAJAVA Scripting Language Scripting Language System C System C JavaScrip t JavaScrip t PERLPERL PythonPython PHPPHP VBScriptVBScript
- 9. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Hardware Description Languages Common Hardware Description LanguagesCommon Hardware Description LanguagesCommon Hardware Description LanguagesCommon Hardware Description Languages VHDLVHDL System C System C Verilog- HDL Verilog- HDL
- 10. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved When designing with HDLs, the designer chooses what language to use and at what level of design abstraction to work. When choosing language, the following aspects must be considered: the availability of suitable electronic design automation (EDA) tools to support the use of the language. previous knowledge personal preferences availability of simulation models synthesis capabilities commercial issues design re-use Hardware Description Languages
- 11. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Hardware Description Languages Two-input AND gate description in VHDL
- 12. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved Hardware Description Languages Full-adder description in Verilog-HDL
- 13. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Hardware Description Languages Analogue voltage amplifier design with a voltage gain of +2.0 Verilog-A amplifier description
- 14. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved Hardware Description Languages Two modeling languages are emerging for mixed-signal (analogue and digital) electronic and mixed-technology system modeling, these being Verilog-AMS and VHDL-AMS. VHDL-AMS is the AMS extension to VHDL. This was adopted as a standard in 1999 as IEEE Standard 1076.1-1999. As with VHDL, designs are modeled using entities and architectures. Considering the analogue connections and signals, analogue ports are declared with a simple nature (e.g., electrical) and with any associated quantities (e.g., voltage across the port to a reference point and currents through the port).
- 15. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Hardware Description Languages Verilog-AMS is the AMS extension to Verilog-HDL. It provides the extensions to Verilog-HDL to model mixed-signal (mixed analogue and digital) electronics and mixed-technology (electrical/electronic and nonelectrical/electronic) systems. It encompasses the features of Verilog-D and Verilog-A.
- 16. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved Government Developed Commercially Developed Ada based C based Strongly Type Cast Mildly Type Cast Case-insensitive Case-sensitive Difficult to learn Easier to Learn More Powerful Less Powerful VHDL vs. Verilog
- 17. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved VHDL vs. Verilog Verilog VHDL module gates(a, b, q, r); input a, b; output q, r; assign q = a & b; assign r = a | b; end module library ieee; use ieee.std_logic_1164.all; entity gates is port( a,b: in std_logic; q,r: out std_logic); end; architecture implement of gates is begin q <= a and b; r <= a or b; end;
- 18. FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved Overview of an FPGA Design
- 19. Digital Circuit Requirements Digital Circuit Requirements Fixed Functionality Fixed Functionality ProcessorProcessor PLDPLD MemoryMemory Standard Product IC Standard Product IC ASICASIC Fixed Functionality Fixed Functionality ProcessorProcessor PLDPLD MemoryMemory MicroprocessorMicroprocessor MicrocontrollerMicrocontroller Digital Signal Processor Digital Signal Processor Simple PLDSimple PLD Complex PLDComplex PLD Field Programmable Gate Array Field Programmable Gate Array ROMROM RAMRAM Technology choices for digital circuit design
- 20. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved To enter a design into an EDA tool, a suitable design entry method is required. Typically, tools will allow the following design entry methods: Circuit schematics present a graphical view of the design using logic gate symbols and interconnect wiring. Boolean expressions can be entered as a text-based description in combinational logic designs. HDL design entry allows a description of the digital logic circuit or system operation to be entered in text form using a suitable language. State transition diagrams present a graphical view of state machines that identifies the design states and the transitions between states. Design Entry Methods
- 21. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Once the design has been entered, it must be synthesized. The process of synthesis involves converting the VHDL source files into a netlist. A netlist is simply a list of logical elements (things that combine, change, or store digital signals) and a list of connections describing how these elements are wired together. A netlist can be platform independent, that is, it can target any architecture from any vendor. (e.g. Mentor LS tool). Many development environments provide additional support tools such as Register Transfer Level (RTL) viewers (graphical representations of the source code) and/or netlist viewers (graphical representation of how the source code will be implemented in fabric). The Electronic Design Interchange Format (EDIF) is a more widely accepted format. Synthesis
- 22. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Basic synthesis process Initial HDL description (technology independent) RTL level Logic level Gate level Final HDL description (technology dependent netlist) Optimization Optimization Optimization ASIC PLD Synthesis directives
- 23. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 23 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 23 © 2009 Xilinx, Inc. All Rights Reserved Available Synthesis Tools FPGA Express: Advantages: None, Our rst LEON synthesized only with it -:) Disadvantaegs: Buggy, slow, runs only on Windows Vendor: Synopsys Status: Synopsys has discontinued it, no longer bundled with Xilinx tools Xilinx Synthesis Tool (XST): Advantages: Bundled with Xilinx ISE, Can automatically infer Xilinx FPGA components, runs on UNIX (Solaris and GNU/Linux) Disadvantaegs: Still buggy, Only supports Xilinx devices Vendor: Xilinx Status: Active support from Xilinx
- 24. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 24 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 24 © 2009 Xilinx, Inc. All Rights Reserved Available Synthesis Tools Leonardo Spectrum: Advantages: Supports large family of FPGA devices, Reliable, Can automatically infer FPGA components Disadvantages: Runs on Solaris, Replaced by Precision-RTL Vendor: Mentor Graphics Status: To be replaced soon Synplify: Advantages: Most trusted in industry, Support large family of FPGA devices, Can automatically infer FPGA components Disadvantages: Some optimizers are still buggy (FPGA Compiler) Vendor: Synplicity Status: Active support from Synplicity
- 25. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 25 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 25 © 2009 Xilinx, Inc. All Rights Reserved Once the hardware design entry is completed (either using a schematic or HDL), you may want to simulate your design on a computer to gain confidence that it works correctly. Simulation requires a form of stimulus to provide to the inputs of the FPGA design, and then an FPGA simulator software can determine the corresponding FPGA outputs. There are 2 ways you can create the simulation stimulus: Using an interactive waveform editor. Using a testbench. A test bench is one or more modules that connect your design, the Unit-Under- Test (UUT), with internally generated stimulus or stimulus from a file to drive the inputs of the UUT and may collect and process the outputs of the UUT. Simulation
- 26. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 26 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 26 © 2009 Xilinx, Inc. All Rights Reserved Simulation After each module is written, it should be simulated. Usually the low-level modes are relatively simple and the test benches quick and easy to write. Once simulated the designer has confidence to move to the next module so that when the lower-level modules are combined. As a general rule, design performance should NOT be determined using simulation. There are four primary locations for running simulation: A. Behavioral Simulation – prior to synthesis B. Netlist Simulation – post-synthesis C. Post-Map Simulation D. Post-Implementation or Post-Place-and-Route Simulation
- 27. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 27 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 27 © 2009 Xilinx, Inc. All Rights Reserved Simulation
- 28. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 28 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 28 © 2009 Xilinx, Inc. All Rights Reserved Implementation is the process of converting one or more netlists into an FPGA- specific pattern. This process is broken down into three basic sub-steps: translation, mapping, and place-and-route. Translate: The job of the translator is to collect all of the netlists into one large netlist and verify that the constraints map to signals. Map: The traditional role of the mapper is to compare the resources specified in the single grand netlist produced by the translate stage against the resources in the targeted FPGA. Place and Route: Place-and-route (P&R) describes several processes where the netlist elements are physically places and mapped to the FPGA physical resources, to create a file that can be downloaded in the FPGA chip. Implementation
- 29. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 29 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 29 © 2009 Xilinx, Inc. All Rights Reserved Available Place and Route Tools Xilinx ISE: Advantages: Vendor provided Place and Route tool, there is no other choice Disadvantages: No point of comparison Vendor: Xilinx Status: Active support from Xilinx Altera Quartus II: Advantages: Vendor provided Place and Route tool, there is no other choice Disadvantages: No point of comparison Vendor: Altera Status: Active support from Altera
- 30. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 30 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 30 © 2009 Xilinx, Inc. All Rights Reserved Bitstream Generation The final step is converting the placed and routed design into a format that the FPGA will understand. Bit-streams can be generated so that they can be directly loaded into an FPGA (usually via JTAG8), or formatted for parallel or serial PROMs (Programmable Read-Only Memory).
- 31. FPGA and ASIC Technology Comparison - 31 © 2009 Xilinx, Inc. All Rights Reserved Tools for synthesis and implementation of FPGAs
- 32. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 32 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 32 © 2009 Xilinx, Inc. All Rights Reserved Synthesis Tool flow HDL DesignerHDL Designer Synplify ProSynplify Pro Leonardo SpectrumLeonardo Spectrum Design Synthesis Implementation ISE Project Navigator ISE Project Navigator VHDL code Netlist Bitstream XSTXST
- 33. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 33 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 33 © 2009 Xilinx, Inc. All Rights Reserved Synthesis stages High level synthesis TechnologyTechnology independentindependent TechnologyTechnology dependentdependent Low level synthesis CompileCompile MapMap Place & RoutePlace & Route ImplementImplement - Code analysis - Derivation of main logic constructions - Technology independent optimization - Creation of “RTL View” - Mapping of extracted logic structures to device primitives - Technology dependent optimization - Application of “synthesis constraints” -Netlist generation - Creation of “Technology View” - Placement of generated netlist onto the device -Choosing best interconnect structure for the placed design -Application of “physical constraints” - Bitstream generation - Burning device
- 34. © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 34 © 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 34 © 2009 Xilinx, Inc. All Rights Reserved Synthesis stages High level synthesisHigh level synthesis Low level synthesisLow level synthesis CompileCompile MapMap Place & RoutePlace & Route ImplementImplement Synplify ProSynplify Pro Leonardo SpectrumLeonardo Spectrum Xilinx Synthesis Tools Xilinx Synthesis Tools TechnologyTechnology independentindependent TechnologyTechnology dependentdependent
Hinweis der Redaktion
- Design languages are of two types, software programming languages (SPL) and hardware description languages (HDL). At one time, designers were either software or hardware designers, and design teams were clearly distinguished by these separate roles. Today, however, designers are involved in both software and hardware design and need skills in both areas, although they may be specialized. By using a particular HDL, the description of the circuit can be created at different levels of abstraction from the basic logic gate description according to the language syntax and semantics.
- Scripting languages provide a high-level application programming interface that enables applications to be created and tested quickly. Unlike languages such as C and C that are compiled before an executable image of the program is run, programs written in a scripting language are interpreted as they run, thereby removing the step of having to compile a program whenever a change is made. Programs using scripting languages can be found in many workstation or PC applications, as well as Internet-based applications. For example, scripting language applications are commonly used to glue together other applications to form a single user interface for a range of existing applications.
- Scripting languages provide a high-level application programming interface that enables applications to be created and tested quickly. Unlike languages such as C and C that are compiled before an executable image of the program is run, programs written in a scripting language are interpreted as they run, thereby removing the step of having to compile a program whenever a change is made. Programs using scripting languages can be found in many workstation or PC applications, as well as Internet-based applications. For example, scripting language applications are commonly used to glue together other applications to form a single user interface for a range of existing applications.
- VHDL vs. Verilog – Which One Is Better? Years ago when HDLs were a very new concept, there were two camps – one backed by Department of Defense (DoD) (VHDL) and the other by the ASIC developers (Verilog). VHDL was originally designed as a means of documenting hardware and simulation – bear in mind that the only programmable logic available at this time were small PLDs (Programmable Logic Device) such as the 22V10 and these were usually programmed in an existing language – ABEL (Advanced Boolean Expression Language). Since projects for the DoD usually have life and death implications, the DoD prefers to use ‘‘strongly typed’’ languages which, by their nature, are somewhat more verbose, but tend to avoid certain types of mistakes. This leads many people to speculate (incorrectly) that Verilog is easier to learn than VHDL. During the early days of HDLs, VHDL sported a number of advantages over Verilog in that there were a number of constructs that were simply not available in Verilog. Over the course of the last 15 or so years there have been a number of ‘‘upgrades’’ to both VHDL and Verilog which make the two languages nearly identical in capability. Theoretically, the same design implemented in VHDL and Verilog should produce identical net-lists, therefore, they should have the same performance. This, however, is rarely the case. Verilog tends to have fewer lines of code per module simply because it is a ‘‘loosely typed’’ language, that is, signals and variables (wires and variables in Verilog) don’t have to be defined prior to their use as is the case with VHDL, which occasionally leads to errors which have to be ferreted out later (usually by reading the detailed synthesis report) rather than being flagged up front during synthesis. Verilog also supports a different set of ‘‘scoping’’ rules – although in many instances convenient, it runs the risk of generating ‘‘side-effects’’ and may make the code more difficult to maintain although it might have been easier to write.
- The choices are shown in Figure 1.1. In Figure 1.1, the electronic components used are integrated circuits (ICs). These are electronic circuits packaged within a suitable housing that contain complete circuits ranging from a few dozen transistors to hundreds of millions of transistors, the complexity of the circuit depending on the designed functionality. Examples of packaged ICs are shown in Figure 1.2. In many circuits, the underlying technology will be based on IC, and a complete electronic circuit will consist of a number of ICs, together with other circuit components such as resistors and capacitors. Whether a standard product IC or ASIC design approach is taken, the type of IC used or developed will be one of four types: Fixed Functionality: These ICs have been designed to implement a specific functionality and cannot be changed. The designer would use a set of these ICs to implement a given overall circuit functionality. Changes to the circuit would require a complete redesign of the circuit and the use of different fixed functionality ICs. 2. Processor: The processor would be more familiar to the majority of people as it is in everyday use (the heart of the PC is a microprocessor). This component runs a software program to implement the required functionality. By changing the software program, the processor will operate a different function. The choice of processor will depend on the microprocessor (uP), the microcontroller (uC), or the digital signal processor (DSP). 3. Memory: Memory will be used to store, provide access to, and allow modification of data and program code for use within a processor-based electronic circuit or system. The two basic types of memory are ROM (read-only memory) and RAM (random access memory). ROM is used for holding program code that must be retained when the memory power is removed. It is considered to provide nonvolatile storage. The code can either be fixed when the memory is fabricated (mask programmable ROM) or electrically programmed once (PROM, Programmable ROM) or multiple times. Multiple programming capacity requires the ability to erase prior programming, which is available with EPROM (electrically programmable ROM, erased using ultraviolet [UV] light), EEPROM or E2PROM (electrically erasable PROM), or flash (also electrically erased). PROM is sometimes considered to be in the same category of circuit as programmable logic, although in this text, PROM is considered in the memory category only. RAM is used for holding data and program code that require fast access and the ability to modify the contents during normal operation. RAM differs from read-only memory (ROM) in that it can be both read from and written to in the normal circuit application. However, flash memory can also be referred to as nonvolatile RAM (NVRAM). RAM is considered to provide a volatile storage, because unlike ROM, the contents of RAM will be lost when the power is removed. There are two main types of RAM: static RAM (SRAM) and dynamic RAM (DRAM). 4. PLD: The programmable logic device is the main focus of this book; these are ICs that contain digital logic cells and programmable interconnect. The basic idea with these devices is to enable the designer to configure the logic cells and interconnect to form a digital electronic circuit within a single packaged IC. In this, the hardware resources will be configured to implement a required functionality. By changing the hardware configuration, the PLD will operate a different function. Three types of PLD are available: the simple programmable logic device (SPLD), the complex programmable logic device (CPLD), or the field programmable gate array (FPGA). An ASIC can be designed to create any one of the four standard product IC forms (fixed functionality, processor, memory, or PLD). An ASIC would be designed in the same manner as a standard product IC, so anyone who has access to an ASIC design, fabrication, and test facility can create an equivalent to a standard product IC (given that patent and general legal issues around IP [intellectual property] considerations for existing designs and devices are taken into account). In addition, an ASIC might also incorporate a programmable logic fabric alongside the fixed logic hardware.
- making use of the specialized resources within the FPGA is almost always the better choice as these specialized resources consume less power, fewer general purpose resources, and meet timing (performance goals) more easily. All errors generated by the synthesis tools must be resolved prior to moving to the next step. Most synthesis tools will also provide a copious list of warnings. Many of these warnings and informational messages will simply echo what you deliberately and intentionally specified; however, these messages should not be categorically ignored as they describe a number of ‘‘issues’’ that the synthesis tool has with your code and may reveal mistakes or unintended behaviors in your code. Many development environments provide additional support tools such as Register Transfer Level (RTL) viewers (graphical representations of the source code) and/or netlist viewers (graphical representation of how the source code will be implemented in fabric). These tools can be very helpful in tracking down certain types of coding issues. The output of this stage of the process is one or more netlists. These netlists come in one of several flavors, the most common being the EDIF/EDF/SEDIF and EDN formats. The Electronic Design Interchange Format (EDIF) is a more widely accepted format. The output of the Xilinx synthesis tools is a ngd file which stands for Netlist Generic Database and conveys the same information as EDIF, but in a binary (not ASCII) fashion. Xilinx provides tools to convert NGD to EDIF should a manual review of the netlist be necessary. Generally, reviewing the netlist is an unnecessary step which is only performed when there is sufficient reason to believe that there is an issue with the results of the synthesis tools.
- The basic synthesis process is shown in Figure 6.5. A synthesis tool requires specific information such as tool set-up routines, technology libraries, and synthesis directives. The tool set-up routines configure the synthesis tool to the particular computing platform on which it is installed. The technology libraries provide specific information relating to the target implementation technology. The synthesis directives are applied by the user to direct the synthesis tool during the design synthesis operation. Synthesis consists of seven steps, identified in Figure 6.5. The initial HDL description is translated (1) to anRTL level description. This formis optimized (2) and then translated (3) into a logic level description. This is optimized (4) and translated (mapped) to a gate level description (5). This is optimized (6), and the result is translated to the final netlist (7). At each step, the description created is closer to the final netlist. The designer sets up specific synthesis directives to direct the synthesis tool in creating the design netlist. Constraints are typically size, speed, and power consumption. Applying different synthesis constraints typically result in different final netlists. These considerations apply to logic synthesis (commonly referred to as synthesis). However, there is also physical synthesis which relates to the automatic synthesis of design layouts in integrated circuit (IC) design at the silicon level. However, physical synthesis will not be considered further in this text. When RTL code is synthesized, this is referred to as RTL synthesis. When behavioral level HDL code is synthesized, this is referred to as behavioral synthesis. Additionally, the initial HDL code must be created so that it is synthesizable. An HDL design description can be created as simulated and the correct operation ascertained, but in certain circumstances the HDL code written like this will be unsynthesizable.
- There are four primary locations for running simulation: A. Simulation run prior to synthesis is known as ‘‘behavioral’’ or ‘‘functional’’ simulation. Since only the source code is available and effectively no information about how the design is actually going to be implemented is available, this type of simulation is used for verifying the function of one or more source modules. This is the most frequently run simulation. There are very few reasons why every module of VHDL code shouldn’t be verified with this type of simulation. B. Post-synthesis simulation runs the netlist version of the design. The netlist contains more of the information regarding the silicon resources (i.e. the delays through each silicon resource), but still has no idea about their placement; therefore, no information about the routing (read ‘‘delays between silicon resources’’). With this information, the post-synthesis simulation will differ in timing from the pre-synthesis; however, the behavior should be the same. The major effect here is that now some of the delays through the silicon resources are known, and to check the fidelity of the netlist generation. C. Post-map simulation is rarely run. More knowledge about the specific implementation strategy, and occasionally the physical placement is known and this information is used to generate more detailed, but still approximated, timing simulation for the design. D. Post-Place-and-Route simulation is the most accurate simulation since all of the delays (both through the ultimate selection of the silicon resources, its location in the FPGA, and the routing among the various resources) are known. This is usually of ‘‘sign-off’’ quality, that is, if the design fully simulates, passes timing analysis,5 and the test bench is valid, then the FPGA should function as expected.6 Post-Place-and-Route simulation is the least frequently run simulation as it is the most time-consuming – both in processor time and in writing a quality test bench.
- Translate The job of the translator is to collect all of the netlists into one large netlist and verify that the constraints map to signals. Any missing modules (which are not detected by the synthesis tools) will be flagged at this stage. Translate also compares the netlist with the user-defined constraints and reports any missing signals. Map The traditional role of the mapper is to compare the resources specified in the single grand netlist produced by the translate stage against the resources in the targeted FPGA. If there are insufficient or incorrect resources specified, the mapper will display an error and halt implementation. As performance is often of concern, modern mappers do more than just compare resources, they may have a limited ability to change the type of resource specified in the netlist (without changing its functionality) to better use the silicon resources. Some mappers will also pre-place certain silicon resources thus taking over some of the role of the placer. Place and Route:Place-and-route (P&R) describes several processes where the netlist elements are physically places and mapped to the FPGA physical resources, to create a file that can be downloaded in the FPGA chip. Place and Route is an iterative process which first attempts to ‘‘place’’ the silicon resources, then ‘‘route’’ the signals among the resources such that the timing constraints are met.