Advanced eXtensible Interface (AXI), part of the ARM Advanced Microcontroller Bus Architecture (AMBA3) (AXI3) and 4 (AXI4) specifications.

1. AMBAAXI PROTOCOL
- HARINATH REDDY

2. Contents
• Introduction
• AXI revisions
• AXI Architecture
• Key features of AXI
• Channel definition
• Interface and interconnect
• Register slices
• Signal description
• Signal interface requirements
• Transaction attributes
• Multiple transactions
• AXI ordering model
• Atomic accessing
• Low power interface

3. Introduction
• Advanced eXtensible Interface (AXI), part of the ARM Advanced
Microcontroller Bus Architecture (AMBA3) (AXI3) and 4 (AXI4)
specifications.
• The AMBA AXI protocol supports high-performance, high-frequency system
designs.
• The AXI protocol is suitable for high-bandwidth and low-latency designs
• The AXI protocol is provides high-frequency operation without using
complex bridges.
• It meets the interface requirements of a wide range of components.
• AXI protocol suitable for memory controllers with high initial access
latency
• AXI protocol provides flexibility in the implementation of interconnect
architectures
• The AXI protocol is backward-compatible with existing AHB and APB
interfaces.

4. AMBHA AXI Revisions

5. Key features of the AXI protocol
• separate address/control and data phases
• support for unaligned data transfers, using byte strobes
• uses burst-based transactions with only the start address issued
• separate read and write data channels, that can provide low-cost
Direct Memory Access (DMA)
• support for issuing multiple outstanding addresses
• support for out-of-order transaction completion
• permits easy addition of register stages to provide timing closure
• The AXI protocol includes the optional extensions that cover signaling
for low-power operation.

6. AXI Architecture
• The AXI protocol is burst-based and defines the following
independent 5 transaction channels:
1)Read address channel
2) Read data channel
3) write address channel
4) write data channel
5) write response channel
• An address channel carries control information that describes the
nature of the data to be transferred.
• The data is transferred between master and slave using eithe write
data channel and read data channel.

7. AXI Architecture for Write
• A write data channel to transfer data from the master to the slave. In
a write transaction, the slave uses the write response channel to
signal the completion of the transfer to the master.

8. AXI Architecture For Read
• A read data channel to transfer data from the slave to the master.

9. Channel definition
Five independent channels which consists of two-way handshake
signals those are VALID, READY
VALID:
Asserts when valid data or control information are available on the channel
READY:
Asserts when receiver can accept the data
LAST:
Asserts while the final data completes

10. Interface and Interconnect
• A typical system consists of several master and slave devices connected
through some form of interconnect.
• Most systems use one of three interconnect topologies:
1) shared address and data buses
2) shared address buses and multiple data buses
3) multilayer, with multiple address and data buses

11. Register slices
• The AXI Register Slice can be used to register an AXI interconnect to
provide timing isolation (at the cost of clock latency).
• A register slice can be inserted at almost any point in any channel, at
the cost of an additional cycle of latency.

12. Signal Descriptions

13. Signal Descriptions (cont..)

14. Signal Descriptions (cont..)

15. Signal Descriptions (cont..)

16. Signal Descriptions (cont..)

17. Signal Descriptions (cont..)

18. Single Interface Requirements
• The source presents the data /control_info and drives the VALID
signal HIGH. The data/control_info from the source remains stable
until the destination drives the READY signal HIGH, indicating that it
accepts the data/control_info.

19. Basic Transactions

20. Basic Transactions(cont..)

21. Relationships between the channels
• The AXI protocol requires the following relationships to be
maintained:
• The VALID signal of the AXI interface sending information must not be
dependent on the READY signal of the AXI interface receiving that information
• An AXI interface that is receiving information can wait until it detects a VALID
signal before it asserts its corresponding READY signal.
• Write data can appear before or same cycle of Write address.
• Read data always come after Read address
• Write response always come after write data

22. Relationships between the channels(Contd..)
Note:
• single-headed arrows point to signals that can be asserted before or after the signal at the start of the
arrow
• double-headed arrows point to signals that must be asserted only after assertion of the signal at the
start of the arrow

23. AHB/AXI Burst Transfer
• AXI supports transaction IDs. The user may issue multiple outstanding
transactions per transaction ID but AHB won’t support these features.

24. AHB/AXI Burst Transfer (Cont..)
• An AXI 'burst' is a transaction in which multiple data items are
transferred based upon a single address, and it is each data item
transferred that is referred to as a 'beat'.

25. Burst Operation
Size

26. Burst Transfer Type
FIFO
CACHE ACCESS
SEQUENTIAL MEMORY ACCESS

27. Burst Control signals
• Every transaction must have the number of transfers
• No component can terminate a burst early to reduce the
number of data transfers.

28. Data read and write structure
• WSTRB : This signal indicates which byte lanes to update in memory.
There is one strobe for each eight bits of the write data bus.
• The WSTRB[n:0] signals when HIGH, specify the byte lanes of the data
bus that contain valid information. There is one write strobe for each
eight bits of the write data bus, therefore WSTRB[n] corresponds to
WDATA[(8n)+7:(8n)].
• Narrow transfers
• the burst has five transfers
• the starting address is 0
• each transfer is eight bits
• the transfers are on a 32-bit bus
• the burst type is INCR.

29. Byte invariance
• To access mixed-endian data structures in a single memory space, the
AXI protocol uses a byte-invariant endianness scheme.
• Byte-invariant endianness means that, for any multi-byte element in a
data structure the element uses the same continuous bytes of
memory, regardless of the endianness of the data

30. Unaligned transfers
• AXI supports unaligned transfers. For any burst that is made up of data
transfers wider than one byte, the first bytes accessed might be unaligned
with the natural address boundary.
• For example, a 32-bit data packet that starts at a byte address of 0x1002 is
not aligned to the natural 32-bit address boundary.
• From figure
• Address: 0x07
• Transfer size: 32 bits
• Burst type: incrementing
• Burst length: 4 transfers
• Note:For incrementing burst type, fist transfer can be unaligned transfers, but the rest transfers are aligned transfers

31. Aligned Transfers
• From figure:
• Address: 0x00 Note: For wrapping burst type, all transfers are aligned transfers
• Transfer size: 32 bits
• Burst type: incrementing
• Burst length: 4 transfers

32. Read and write Access/response structure
• OKAY Normal access success. Indicates that a normal
access has been successful. Can also indicate an
exclusive access has failed.
• EXOKAY Exclusive access okay. Indicates that either
the read or write portion of an exclusive access has been
successful.
• SLVERR Slave error. Used when the access has reached
the slave successfully, but the slave wishes to return
an error condition to the originating master.
• DECERR Decode error. Generated, typically by an
interconnect component, to indicate that there is no
slave at the transaction address.

33. Transaction attributes
• The AXI protocol defines ARCACHE and AWCACHE to support memory
and peripheral slaves.
AXI3 memory attribute signaling:
In AXI3, the AxCACHE[3:0] signals specify the Bufferable,
Cacheable, and Allocate attributes of the transaction. AxCACHE specify
ARCACHE&AWCACHE

34. Bufferable Bit
• Bufferable Bit(AxCACHE[0]): When this bit is asserted, The
interconnect or any component can delay the transaction for an
arbitrary number of cycles, usually only relevant to writes.
• IF a transaction is bufferable then It is acceptable for a bridge or system level
cache to provide write response.
• If non-bufferable then Final destination to provide response
Bufferable
Non Bufferable

35. Cache Support
• Cacheable Bit(AxCACHE[1]) :
Write : a number of different writes can be merged together
Read : a location can be pre-fetched or can be fetched just once
for multiple read transactions
• Read Allocate Bit(AxCACHE[2]):
If the transfer is a read and it misses in the cache, then it should
be allocated
• Write Allocate Bit(AxCACHE[3]):
If the transfer is a write and it misses in the cache, then it should
be allocated

36. AXI4 changes to memory attribute signaling
• AXI4 makes the following changes to the AXI3 memory attribute
signaling:
• the AxCACHE[1] bits are renamed as the Modifiable bits
• ordering requirements are defined for Non-modifiable transactions
• the meanings of Read-allocate and Write-allocate are updated.
Non-modifiable transactions (AxCACHE[1] LOW)
A Non-modifiable transaction must not be split into multiple
transactions or merged with other transactions also below parameters
must not be changed.

37. Modifiable transactions (AxCACHE[1] high)
• A Modifiable transaction can be modified in the following ways:
• a transaction can be broken into multiple transactions
• multiple transactions can be merged into a single transaction
• a read transaction can fetch more data than required
• a write transaction can access a larger address range than required, using the
WSTRB signals to ensure that only the appropriate locations are updated.
• AxLOCK, AxPROT must not be changed.
• in each generated transaction, the following signals can be modified:
• the transfer address, AxADDR
• the burst size, AxSIZE
• the burst length, AxLEN
• the burst type, AxBURST.

38. Access permissions
• The term AxPROT refers collectively to the ARPROT(read accesses )
and AWPROT(write accesses) signals.
• Normal/Privileged: This is used by some masters to indicate their
processing mode. A privileged processing mode typically has a greater
lever of access within a system(eg. CPU will get privileged access
compare to other normal masters)

39. Access permissions(Contd..)
• Secure / Non-secure: This is used in systems where a greater degree
of differentiation between processing modes is required.

40. Access permissions(Contd..)
• Data / Instruction: This bit gives an indication if the transaction is an
instruction or a data access.
• AxPROT[2] LOW to indicate a data access unless the access is
specifically known to be an instruction access.

41. Multiple Transactions
• The AXI protocol includes AXI ID transaction identifiers. A master can
use these to identify separate transactions that must be returned in
order.
• there is no restriction on the ordering of transactions with different ID
values means a single physical port can support out-of-order
transactions by acting as several logical ports.
• By using AXI IDs, a master can issue transactions without waiting for
earlier transactions to complete so that system performance can
improve also enable parallel processing of transaction.
• AXI4 removes the WID signals, to reduce
the pin-count of the interface.

42. AXI4 Ordering Model
• The AXI4 protocol supports an ordering model based on the use of
the AXI ID transaction identifier.
• The AXI ordering model requires that all transactions with the same
ID in the same direction must provide their responses in the order in
which they are issued.
• The order of response at the master to All transactions must be the
same as the order of issue.

43. AXI4 Ordering Model (contd..)

44. Atomic Accesses
• Exclusive accesses:
The AxLOCK signals select exclusive access, and the RRESP and BRESP signals
indicate the success or failure of the exclusive access read or write
respectively.
The master attempts to complete the exclusive operation by performing an
exclusive write to the same address, and with an AWID that matches the ARID
used for the exclusive read.

45. Atomic Accesses (cont..)

46. Locked accesses
• AXI4 does not support locked transactions. However, an AXI3
implementation must support locked transactions.
• When a master uses the AxLOCK signals for a transaction to show that
it is a locked transaction.
• Interconnect must ensure that only that master can access the
targeted slave region, until an unlocked transaction from the same
master completes.
• keep any locked transaction sequence within a single 4KB address
region.

47. QoS signalling
• AXI4 protocol support 4-bit Quality of Service (QoS), AxQOS indicates
AWQOS or ARQOS.
• A master can produce its own AxQOS values, and if it can produce
multiple streams of traffic, it can choose different QoS value for the
different streams.

48. Multiple region signalling & User-defined signalling
• Multiple region signalling:
• AXI4 protocol support 4-bit multiple region interfaces,AxREGION indicates
AWREGION or ARREGION.
• Region identifier Permits a single physical interface on a slave to be used for
multiple logical interfaces.
• The use of the region identifier means that the slave does not have to support
the address decode between the different logical interfaces.
• User-defined signalling:
• AXI4 interface signal set can include a set of User-defined signals, called the
User signals, on each AXI4 channel(AWUSER, ARUSER, WUSER, RUSER,
BUSER).
• The width of the User-defined signals is implementation defined and can be
different for each of the channels.

49. Low-power Interface
• Any peripheral that has no power-down sequence, and that can
indicate when its clocks can be turned off.
• Any peripheral that requires a power-down sequence, and that can
have its clocks turned off only after it enters a low-power state.
• The peripheral requires an indication from a system clock controller
to indicate when to initiate the power-down sequence and must then
signal when it has entered its low-power state.
Signal Source Description
CSYSREQ Clock controller System exit low-power state request. This signal is a request from the system
clock controller for the peripheral to exit from a low-power state.
CSYSACK Peripheral device Low-power request acknowledgement. This signal is the acknowledgement
from a peripheral of a system low-power request.
CACTIVE Peripheral device Clock active. This signal indicates that the peripheral requires its clock signal: 1
= peripheral clock required 0 = peripheral clock not required.

50. Power-down or power-up handshake
• CSYSREQ:
To request that the peripheral enter a low-power state, the
system clock controller drives the CSYSREQ signal LOW. During normal
operation, CSYSREQ is HIGH.
• CSYSACK:
The peripheral uses the CSYSACK signal to acknowledge both the
low power state request and the exit from the low-power state. Figure
shows CSYSREQ and CSYSACK handshake

51. Acceptance/ Denial of low-power request

52. Clock control sequence summary
• Requesting Entry for Low power state

53. Clock control sequence summary(contd..)
• Exit From Low power State:

54. AMBA AXI4-Lite
• AXI4-Lite is suitable for simpler control register-style interfaces that
do not require the full functionality of AXI4.
• The key functionality of AXI4-Lite operation is:
• all transactions are of burst length 1
• all data accesses use the full width of the data bus , AXI4-Lite supports a data
bus width of 32-bit or 64-bit.
• all accesses are Non-modifiable, Non-bufferable
• Exclusive accesses are not supported
• The EXOKAY response is not supported on the read data and write response
channels
• Length, Burst, Size related signals are not supported
• Bus Width can be 32/64 bit and support strobe

55. AMBA AXI4-Lite (Cont…)
• AXI4-Lite does not support data interleaving, the burst length is
defined as 1
• AXI4-Lite supports multiple outstanding transactions, but a slave can
restrict this by the appropriate use of the handshake signals
• AXI4-Lite does not support AXI IDs. This means all transactions must
be in order, and all accesses use a single fixed ID value
• AXI4-LITE Signals:

56. AMBA AXI4-Stream
• The AXI4-Stream protocol is used as a standard interface to connect
components that wish to exchange data.
• The protocol supports multiple data streams using the same set of
shared wires, allowing a generic interconnect to be constructed that
can perform upsizing, downsizing and routing operations.
• Byte Definitions(Data Type):

57. DATA Stream
• The transport of data from one source to one destination.
• A data stream can be:
• a series of individual byte transfers
• a series of byte transfers grouped together in packets.
• Data Streams take many forms like
• Byte stream: It is the transmission of a number of data and null bytes. On
each TVALID, TREADY handshake, any number of data bytes can be
transferred.
• Continuous aligned stream: It is the transmission of a number of data bytes where
every packet has no position or null bytes.
• Continuous unaligned stream: It is the transmission of a number of data bytes
where there are no position bytes between the first data byte and the last data
byte of each packet
• Sparse stream: It is the transmission of a number of data bytes and position
bytes.

58. AXI4 Stream Signal list

59. TVALID before TREADY handshake

60. Transfer Interleaving and Ordering
• Transfer interleaving:
• Transfer interleaving is the process of interleaving transfers from different streams on
a transfer-by-transfer basis.
• The interconnect is not required to constrain the interleaving of streams so that the
capabilities of a slave are not exceeded.
• Transfer ordering:
The AXI4-Stream protocol requires that all transfers remain ordered.
The advantages of not permitting reordering are:
• It ensures that reordering cannot increase the stream interleaving observed by a
slave
• The overall predictability of the system is improved
• It can be determined, independent of the TID of the transfers, that a given transfer
has reached a destination by observing that a later transfer from the same master
has reached the same destination
• The complexity of a system is reduced

61. AXI4 Stream Comparison with the AXI4 Write Data Channel
• The AXI4-Stream interface has many similarities to an AXI4 write data
channel. However, there are some key differences are:
• the AXI4 write data channel does not permit interleaving
• the AXI4-Stream interface does not have a defined or maximum burst or
packet length
• the AXI4-Stream interface allows the data width to be any integer number of
data bytes
• the AXI4-Stream interface includes TID and TDEST signals to indicate the
source and destination respectively
• the AXI4-Stream interface defines more precisely the manipulation of the
TUSER sideband signals
• the AXI4-Stream interface includes TKEEP signals to allow the insertion and
removal of null bytes.

62. AXI4 Feature Availability and IP Replacement

63. AXI DMA Interfaces

64. AXI revisions Description and usages

65. References
• https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-
and-AXI4-Protocol-Specification/Introduction/AXI-
Architecture/Interface-and-interconnect
• http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs
/AXI4_specification.
• https://www.xilinx.com/support/documentation/ip_documentation/
ug761_axi_reference_guide.pdf
• https://developer.arm.com/documentation/ihi0051/a/Interface-
Signals/Signal-list
• https://community.arm.com/cfs-file/__key/telligent-evolution-
components-attachments/01-1998-00-00-00-00-56-
8/QoS_2B00_QVN_2D00_FINAL.pdf