o 2.5+ years of experience in the embedded system domain o Expertise in C language, OS concepts and ARM cortex M3/M4 architecture o Strong Electronics engineering and research background

1. Gaurang Rathod gaurangdr@gmail.com
Ahmedabad, Gujarat 9898668308
 Summary
o 2.5+ years of experience in embedded system domain
o Expertise in C language, OS concepts and ARM cortex M3/M4 architecture
o Strong Electronics engineering and research background
 Experience
Associate Engineer Softnautics Pvt Ltd,
Ahmedabad, Gujarat
Sept 2017 – Present
Research Associate
NIT – Surat,
Gujarat
Apr 2016 – Sept 2017
 Education
M.E.
Electronics & Communication
Sarvajanik College of Engineering & Technology
Surat, Gujarat
8.09 CPI Aug 2012 – Jun 2014
B.E.
Electronics Engineering
Birla Vishvakarma Mahavidyalaya
Vallabhvidhya Nagar, Gujarat
6.98 CPI Aug 2008 – Jun 2012
H.S.C.
Navsari High School
Gujarat State Education Board, Gujarat
79.40 % Apr 2008
S.S.C.
Navsari High School
Gujarat State Education Board, Gujarat
86.00 % Apr 2006
 Certificates
o PG Diploma in Embedded System Design
73.29% | CDAC – ACTS, Pune
Aug 2015 – Feb 2016
o GATE – E.C.
Marks: 32.51 | Score: 443
March 2015
o UGC NET
65.14% | Electronics Science
Dec 2014
 Publication
o Energy efficient load balancing in WSN to extend life of sensor network Feb 2015
Conference: ICCU, IEEE Computer Society, Pune
ISBN: 978-1-4799-6892-3
o Energy efficient target coverage in wireless sensor network May 2015
Conference: International journal of advance research and innovative ideas in education
ISSN: (o):2395-4396
 Technical Skills
Programming Language C, C++, Python and MATLAB scripting
Microcontroller & development board used
8051, Adriano UNO, STM32F4 discovery board, AduCm360
from Analog devices, BBB
Protocol & peripheral explore
SPI, I2C, UART, CAN, ADC, DAC, Timer, I2S

2. Software
GIT, Wireshark, Keil, LTSpice,
Technology knowledge
 LTE (PHY, MAC, RLC & RRC layer) and its various
technical concepts like MIMO, OFDM
 Video codec – H.264
 DSP: FIR & IIR filters, DFT, FFT, DCT
 Analog & digital electronics
 VLSI: CMOS, basics of RTL designing
 AI: neural network, CNN, Tensorflow
 Projects
o Code optimization of convolution neural network simulator sensAI
 Description: The sensAI simulator of Lattice semiconductor is consuming time for inference
(prediction). After profiling the whole source code, optimizations is done in pooling & convolution
layer using multi-processing and also applies the concept of loop unrolling.
 Tool: anaconda environment, python2.7 & 3.5, pycharm
 Team : 3 members | Time duration: 6 months
o A TCP client-server application using socket programming
 Description: Made a multi-threaded server which creates thread for each client. After successful
connection establishment client starts reading a text file and sends it to server in 1KB chunks. On
receiving each chunk, server converts the text into all capital letter and sends it back to client. Client
writes the received data in output file. When whole file is converted to capital letters, client exits
gracefully by closing the connection. On this event, the request handler thread on server for the
client also terminates gracefully
 Tool: Socket programming, testing using Wireshark
o Implementation of ETHERCAT(Ethernet for Control Automation Technology) field bus protocol
 Description: Install one module of ETHERCAT in Linux pc which act as master and other module in
beagle bone black board which act as a slave, done a kernel level programming for slave side for
sending data with time stand and master side for receiving that data.
 Tool: ETHERCAT protocol source code from GIT , linux2.6 kernel build
o Test case development, integration and verification
 Description: For Xilinx’s Zynq, Zynqmp and microblaze boards, test cases are develope in regression
framework. Modify the framework according to new test suite integration.
 Team: 5 members | Time duration: 1.5 months
 Tool: bash scripting, regression testing

3. o Develop a FIR low pass filter on STM32F4 discovery board
 Description: A noisy analog input signal from function generator is converted into digital using ADC.
Using MATLAB’s fdatool, calculate the weights of FIR filter and using that weights implement FIR
filter for the 700 Hz cut off frequency. After successfully filtering, done digital to analog conversion
using DAC and verify the signal on DSO
 Tool: MATLAB, STM32F4 discovery board, function generator, DSO, Keil
o Develop impedance detector for glottography
 Description: Impedance glottography is a non-invasive technique for monitoring the variation of the
degree of contact between the vibrating vocal cords during voice production. Electrical impedance is
sensed using a pair of 2 or 4 channel electrodes placed on either side of the larynx, by injecting a
low-level high-frequency (Freq>32KHz, I<10mA) current. Modulated signal is obtain at electrode is
demodulated using synchronous demodulator, amplify the signal and pass it to digital low pass filter
which is made in STM32F4 Discovery board, convert the final output of low pass digital filter to
analog form.
 Team: 3 members | Time duration: 10 months
 Tool: LtSpice, MATLAB, Keil, Eagle PCB design
 Hardware: ADA2200-demodulator IC, STM32F4 Discovery Board, DSO, High frequency function
generator, DMM, analog components like op-amp, transistor etc.
o Develop a model that generate similar signal from human glottal
 Description: To test the working and uniformity of impedance detector, an impedance simulator
model is develop using a resistor array. Simulator generate impedance very similar pattern to the
gloater tissue of body.
 Tool: LtSpice, Eagle PCB design
 Hardware: Aurdino Uno, low impedance analog switching IC, resistor array
o Load balancing to extend the life of WSN
 Description: Lifetime of WSN is defined by life of first certain percentage of dying nodes. Load
balancing is a method to make energy consumption of all nodes equal which solve the energy hole
problem in WSN. Develop an algorithm that implement load balancing by monitoring the residual
energy of node and make energy consumption of all node balanced.
 Tool: MATLAB, NS2 simulator | Time: 8 months | Team: 1 member
 Work shops
o Xilinx tool training for Zybo/Zynq ARM/FPGA SoC trainer board Dec 2016
IISC Bangalore
o Analog mixed signal and RF system design Jun 2016
IIT Bombay

4.  Personal Information
o Address: 166, Prashant Society 2, Palanpur Jakatnaka, Surat 395009
o Date of birth: 09 August, 1990
o Marital status: Single
o Hobbies: Reading, swimming, exploring the nature