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Study on 32-bit Cortex- M3 Powered MCU: STM32F101 ,[object Object]
Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Features ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Applications ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The STM32 Key Benefits ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
STM32 Complete Family
STM32F10x Block Diagram
Memory Layout ,[object Object],[object Object],[object Object],[object Object],[object Object]
Power Control (PWR) ,[object Object],[object Object],[object Object],[object Object],[object Object]
Basic Structure of a Standard I/O Port bit ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Interrupts and Events ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
DMA Block Diagram
Analog-to-Digital Converter (ADC)
Digital-to-Analog converter (DAC) ●  Two DAC converters: one output channel each ●  8-bit or 12-bit monotonic output ●  Left or right data alignment in 12-bit mode ●  Synchronized update capability ●  Noise-wave generation ●  Triangular-wave generation ●  Dual DAC channel independent or simultaneous conversions ●  DMA capability for each channel ●  External triggers for conversion ●  Input voltage reference VREF+
Universal Synchronous Asynchronous Receiver Transmitter (USART) ●  Full duplex, asynchronous communications ●  NRZ  standard  format (Mark/Space) ●  Fractional baud rate generator systems baud rates up to 4.5 MBits/s ●  Programmable data word length (8 or 9 bits) ●  Configurable stop bits  ●  LIN Master Synchronous Break send capability and LIN slave break detection capability ●  IrDA SIR Encoder Decoder ●  Smartcard Emulation Capability: ISO 7816-3 standards, 0.5, 1.5 Stop Bits  ●  Single wire Half Duplex Communication ●  Multiprocessor communication  ●  Wake up from mute mode  ●  Two receiver wakeup modes: Address bit (MSB, 9th bit), Idle line ●  Ten interrupt sources with flags ●  Four error detection flags ●  Separate enable bits for Transmitter and Receiver
I2C Introduction
Controller Area Network (bxCAN) ●  Supports CAN protocol version 2.0 A, B Active. ●  Bit rates up to 1 Mbit/s. ●  Supports the Time Triggered Communication option. ●  Three transmit mailboxes. ●  Configurable transmit priority. ●  Time Stamp on SOF transmission.
USB Full Speed Device Interface (USB)
I2S Functional Description
SPI Functional Description The SPI peripheral contains a hardware CRC unit which is designed to support interfacing with multimedia and SD memory cards.
Development Tools Hitex Performance Stick ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],USB-to-JTAG Adapter
Debug Support (DBG)
Additional Resource ,[object Object],[object Object],[object Object],[object Object],[object Object],Newark Farnell

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Study on 32-bit Cortex - M3 Powered MCU: STM32F101

  • 1.
  • 2.
  • 3.
  • 4.
  • 5.
  • 8.
  • 9.
  • 10.
  • 11.
  • 14. Digital-to-Analog converter (DAC) ● Two DAC converters: one output channel each ● 8-bit or 12-bit monotonic output ● Left or right data alignment in 12-bit mode ● Synchronized update capability ● Noise-wave generation ● Triangular-wave generation ● Dual DAC channel independent or simultaneous conversions ● DMA capability for each channel ● External triggers for conversion ● Input voltage reference VREF+
  • 15. Universal Synchronous Asynchronous Receiver Transmitter (USART) ● Full duplex, asynchronous communications ● NRZ standard format (Mark/Space) ● Fractional baud rate generator systems baud rates up to 4.5 MBits/s ● Programmable data word length (8 or 9 bits) ● Configurable stop bits ● LIN Master Synchronous Break send capability and LIN slave break detection capability ● IrDA SIR Encoder Decoder ● Smartcard Emulation Capability: ISO 7816-3 standards, 0.5, 1.5 Stop Bits ● Single wire Half Duplex Communication ● Multiprocessor communication ● Wake up from mute mode ● Two receiver wakeup modes: Address bit (MSB, 9th bit), Idle line ● Ten interrupt sources with flags ● Four error detection flags ● Separate enable bits for Transmitter and Receiver
  • 17. Controller Area Network (bxCAN) ● Supports CAN protocol version 2.0 A, B Active. ● Bit rates up to 1 Mbit/s. ● Supports the Time Triggered Communication option. ● Three transmit mailboxes. ● Configurable transmit priority. ● Time Stamp on SOF transmission.
  • 18. USB Full Speed Device Interface (USB)
  • 20. SPI Functional Description The SPI peripheral contains a hardware CRC unit which is designed to support interfacing with multimedia and SD memory cards.
  • 21.
  • 23.