HCS08 Overview

8. Part Numbering Schema MC 9 S08 GB 60 MC = Fully Qualified PC = Product Engineering Memory Type 9 – Flash 7 – OTP 3 – ROM Core Type S08 – HCS08 Product Family Approximate Memory

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11. Memory Map Name Address Comment Direct-page registers $0000 - $00xx Up to 128 bytes RAM Beginning at $00xx Includes some direct page locations High page registers $1800 - $182B System configuration FLASH Memory -$FFFF Up to 60Kbytes Vectors $FFC0 - $FFFF Up to 32 x 2 bytes

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Hinweis der Redaktion

Welcome to the training module on Freescale HSC08 microcontroller family. The intent of this training module is to provide an overview of the HCS08 microcontroller family. We will discuss the general role of the HCS08, peripherals and devices such as Flash, internal clock generator module, and the internal clock source module, security features and protection, and low voltage protection features.
The S08 fits into the highest level of the Freescale 8-bit family, which originated with the HC05 family. The S08 seamlessly bridges from the HC08 family into the S12 family and beyond. In addition, Freescale offers a full range of other products and tools that are compatible with the S08 family as well as the HC08 and S12 families.
The S08 is to complement microcontrollers that already exist and to expand features and performance into a higher range than where the HC08 was originally targeted. The S08 has technology to extend battery life, low power enhancements, and increased performance at low voltage. The S08 uses the third generation of 0.25μ Flash technology, which is one of the fastest programming, densest arrays available in the 8-bit MCU market. The S08 also introduces an innovative on-chip debugger. This system eliminates the traditional need for a separate hardware emulator, and it allows users to emulate the systems using the actual silicon you will use in the final applications. The S08 also has robust EMC performance. Several enhancements improve the chip’s performance in noisy environments; EMC susceptibility has been reduced and minimized. Furthermore, S08 is 100 percent backwards code compatible with HC08, but it also has some expanded instructions and some addressing modes to improve C code generation efficiency. In addition, S08 has integrated a wide variety of peripherals, including serial communication ports, timers and ADCs.
The HCS08 family offers several features that should drastically improve the low-power performance of user applications. One of the first things that it offers is a true 1.8V operation. 1.8V is significant because it is basically equal to two alkaline batteries. More features include the multiple power-saving modes. There are up to three Stop modes and a Wait mode built into all HCS08s to improve power consumption while the CPU is not required. The HCS08s offer an extremely low-power real-time interrupt (RTI) with several different interrupt and timeout options. The clock sources permit switching to different frequencies, which allows the application to run the CPU at a speed that is beneficial for power savings yet fast enough to do the calculations and computation required for the application. Flash reprogrammability down to 1.8V allows the application to use Flash as EEPROM.
The S08 CPU executes all HC08 instructions, as well as a background (BGND) instruction and additional addressing modes on the LDHX, STHX, and CPHX instructions to improve compiler efficiency. The maximum clock speed for the CPU is 40 MHz (typically generated from a crystal or internal clock generator). The CPU performs operations at this 40 MHz rate and the maximum bus rate is 20 MHz (half the CPU clock frequency). The core includes support for up to 32 interrupt or reset sources with separate vectors. The peripheral modules provide local interrupt enable circuitry and flag registers.
The programmer’s model for the HCS08 CPU shown here includes the same registers as the M68HC08. These registers are not located in the memory map of the microcontroller. They are built directly inside the CPU logic. These include one 8-bit accumulator (A), a 16-bit index register made up of separately accessible upper (H) and lower (X) 8-bit halves, a 16-bit stack pointer (SP), a 16-bit program counter (PC) and an 8-bit condition code register (CCR) which includes five processor status flags (V, H, N, Z, and C) and the global interrupt mask (I).
Here is the product numbering system for HCS08 family.
Here shows basic connections that are common to typical application systems. The details are provided for power, oscillator, reset, mode and background interface connections. The example system uses the MC9S08Gb60, which is a representative device in the HCS08 family. VDD and VSS are the primary power supply pins for the HCS08 MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. This internal voltage regulator provides regulated 2.5-volt (nominal) power to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins. HCS08 derivatives can be operated with no external crystal or oscillator. When this occurs, the MCU uses an internally generated self-clocked rate equivalent to about 8-MHz crystal rate. The oscillator in the MC9S08GB60 is a traditional Pierce oscillator that can accommodate a crystal or ceramic resonator in either of two frequency ranges selected by the RANGE bit in the ICGC1 register. The low range is 32 kHz to 100 kHz and the high range is 1 MHz to 16 MHz. Not all HCS08 derivatives have a reset pin. When there is no reset pin, you can cause a reset by cycling power to force power-on reset (POR), using a background command to write to the BDFR bit in the SBDFR register, or using software to force something like an illegal opcode reset. In the MC9S08GB60, the reset pin is a dedicated pin with a pullup device built in. The background/mode select (BKGD/MS) pin includes an internal pullup device, input hysteresis, a 2-mA output driver, and no output slew rate control. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
An on-chip voltage regulator is a key feature of MCUs in Freescale’s HCS08 Family. The primary function of this regulator is to produce an internal 2.5-volt logic power supply from the MCU’s VDD power supply. This regulator has standby, passthrough, and power-down modes, which are used to place an 9S08GB/GT into stop1, stop2, and stop3 modes. Run mode is the normal operating mode for the HCS08 family. In this mode, the CPU execute code from internal memory with execution beginning at the address $FFFE:$FFFF after reset. The active background mode functions are managed through the background debug controller (BDC) in the HCS08 core. The S08s have four standard, low-power modes: Stop 1, Stop 2, Stop 3, and Wait. Stop 1 is the lowest power mode and, in this mode, the internal circuitry is powered off completely and just a very basic level of leakage current is all that's consumed by the device. In Stop 2 and Stop 3, the amount of functionality that is available within these low-power modes starts improving. Wait mode allows most of the peripherals to run while just shutting off clocks to the CPU.
The five major memory spaces that are defined by the core are shown in the Table. You may need to refer to the data sheet for a particular derivative for exact information about the size and boundaries of each of these blocks. Direct-page registers include the I/O port registers and most peripheral control and status registers. The RAM memory block starts immediately after the end of the direct-page register block and extends to higher addresses. High-page registers are located at $1800 to $182B. These are registers that are used less often than the direct-page registers so they are not located in the more valuable direct address space. FLASH memory fills the 64-Kbyte memory map to $FFFF. The starting address of this block depends on how much FLASH memory is included in the MCU. The vector space is part of the FLASH memory at $FFC0–$FFFF but it is separately decoded so that other HCS08 modules can recognize when an interrupt vector is being fetched.
Here is the block diagram for the internal clock generation module. The ICG generates the clocks used by the CPU and chip peripherals. The ICG is composed of Frequency-locked loop or FLL for short and the clock selection circuitry. There are two clock references available, an external clock input and oscillator, and a very accurate internal reference generator. The ICG module has four modes of operation: Self-clock mode (SCM), FLL engaged, internal clock (FEI) mode, FLL bypassed, external clock (FBE) mode, and FLL engaged, external clock mode (FEE). SCM is a simple, internally clocked mode. It's the default mode out of reset, and it provides a very reliable start-up from a power-off situation, or for wakeup from some Stop modes. Although it provides a very reliable clock source, is not the most accurate option available. The FEI mode is more accurate than the SCM. The third mode is FBE. This mode simply takes an external clock source presented at the MCU pins and uses that clock source directly to generate the system clocks. The fourth mode, FEE, is very similar to the FEI mode except instead of using an internal reference for the FLL, it uses an external clock reference. SCM and FEI require no external components, which reduces your system's cost and increases its reliability by not having additional components on your board. All four modes are software selectable; the user program can switch between modes as necessary within the system. The ICG module also has a clock monitor that automatically switches modes if a clock is lost.
Here is the block diagram for the internal clock source module. The ICS is very similar to the ICG module used on some other HCS08s. Like the ICG, the ICS is composed of FLL and the clock selection circuitry. There are two clock references available, an external clock input and oscillator, and a very accurate internal reference generator. The ICS module has four modes of operation, three of which are basically the same as the ICG: FEI mode, a new FLL bypassed, internal clock (FBI) mode, FBE mode, and FEE mode. Of the four modes, two modes (FEI, and FBI) require no external components, thereby increasing the system’s reliability and freeing up board space for other use. The internal reference of the ICS is trimmable, with a typical resolution of 0.1 percent. All of these modes are software selectable. The software can select between any of the four modes at any time, again allowing for very flexible clock applications to switch between high frequency, low frequency, and internal or external as needed by the application. The oscillator portion of the ICS has the same low power or high gain oscillator options as the ICG's oscillator. Finally, like the ICG, the bus frequency is one-half of the ICSOUT frequency.
The serial communication interface (SCI) module provides a basic two-wire, asynchronous communications interface that can connect to a PC, other peripherals, or controllers in an application. The maximum baud rate is 1.25 Mbps, with a maximum bus frequency of 20 MHz for most of the S08 family. The SCI module has a flexible, independent 13-bit modulo-based baud rate generator, which allows a wide variety of baud rates to match the bus frequency to external communication standards accurately. Advanced data sampling at 16x over sampling, which provides very reliable communications. When communicating through a cable to another board several feet away, you will still see reliable communications. Both the receive and transmit are double buffered. Double buffering allows the SCI to queue up an extra byte for transmit. Upon reception, it also allows the flexibility to wait until reading the data. The SCI also has a hardware parity and receiver wakeup to align the SCI with standard communications protocols on the market.
Here are main features of the TPM module. They include various configurations for the multiple channels on each timer: input capture, output compare, or buffered edge-aligned PWM. The input capture trigger can be rising edge, falling-edge, or any-edge. The output compare function has set, clear, and toggle options. PWM outputs have selectable polarity. Each TPM can also be configured for buffered, center-aligned PWM (CPWM) for all channels on a timer. The TPM has several clock source options: bus clock, fixed system clock, or a clock connected to an external pin. The clock source to prescaler for each TPM is independently selectable. Finally, the TPM module has these key features: a 16-bit free running counter with an up/down counting option, a 16-bit modulus register to control counter range, the ability to enable the timer system, and one interrupt per channel plus a terminal count interrupt.
The S08 has several security and system protection features. For enhanced security, two NVM bits have been reserved in a special register. If the security is enabled, then an 8-byte security code is required to access and read the Flash contents. This feature prevents a hacker from trying to get into an MCU to read out the code or any sort of data contents that are within the Flash. If security is not broken, the only Flash function that can be executed is a mass erase. With regards to system protection features on S08 MCUs, a Computer Operating Properly (COP) watchdog is available, and it has a periodic timeout if the COP is not fed by writing to a specific register within the timeout period. The COP can operate off of the bus clock or an internal clock source independent of the bus clock. When using the internal clock source, the COP can time out if the bus clock is lost and the CPU is not operating properly at the time. Another protection feature is illegal address and illegal opcode detect/reset. If an unimplemented address or unimplemented opcode attempts to execute, the system will reset. The Flash also has a protection feature that prevents unintentional changes to Flash memory.
Two features provide low voltage protection. The low voltage detect (LVD) module can be configured as a reset, an interrupt, or a software flag. The nominal trip point is 1.8V; this is the default out of a power on reset (POR). LVD can also be reconfigured to trip at 2.1V as a second software selectable trip point. In addition, this module can be set to function in Stop mode for protection while in the low power state. The second low voltage protection feature is the low voltage warning (LVW). This additional warning that VDD is falling is set at a higher trip point than the LVD. This additional low voltage warning flag allows a system to detect when batteries are getting low but still have enough power to put the MCU into a ready state for replacing batteries.
Thank you for taking the time to view this presentation on HCS08 overview. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Freescale site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.

HCS08 Overview

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Hinweis der Redaktion