1. Chapter 7 Counters and Registers

2. 7-1 Asynchronous(ripple)counters

8. Frequency division In any counter, the signal at the output of the last FF(i.e., the MSB) will have a frequency equal to the input clock frequency divided by the MOD number of the counter. Such circuits are known as divide-by-N counters .

12. 7-2 Counters with MOD NUMBER < 2 N MOD-6 counter produced by clearing a MOD-8 counter when a count of six occurs.

13. State Transition Diagram

15. Changing the MOD number Determine the MOD number of the counter in Figure 7-6(a). Also determine the frequency at the D output

16. Changing the MOD number Construct a MOD-10 counter that will count from 0000(zero) through 1001(decimal 9)

20. 7-3 IC Asynchronous counters

26. 7-4 Asychronous Down counter

28. 7-5 Propagation delay in ripple counters

32. Circuit operation Only those FFs that are supposed to toggle on that NGT should have J=K=1 when that NGT occurs.

36. 7-7 Synchronous Down and UP/Down counters

38. Presettable counters

41. The 74ALS193/HC193

42. Example

43. Example

44. Variable MOD Number using the 74ALS193/HC193

45. Multistage Arrangement

48. Active-High Decoding

50. Active-LOW Decoding

51. BCD Counter Decoding

53. 7-12 Decoding Glitches

54. Strobing

56. Cascading BCD counters

57. 7-15 Shift-Register Counters

58. Starting a Ring Counter

59. Johnson Counter

60. Decoding A Johnson Counter